--- /dev/null
+From 498cd5c32be6e32bc0f8efcad48ab094bb2bfdf3 Mon Sep 17 00:00:00 2001
+From: Marc Zyngier <marc.zyngier@arm.com>
+Date: Mon, 16 Nov 2015 10:28:18 +0000
+Subject: arm64: KVM: Add workaround for Cortex-A57 erratum 834220
+
+From: Marc Zyngier <marc.zyngier@arm.com>
+
+commit 498cd5c32be6e32bc0f8efcad48ab094bb2bfdf3 upstream.
+
+Cortex-A57 parts up to r1p2 can misreport Stage 2 translation faults
+when a Stage 1 permission fault or device alignment fault should
+have been reported.
+
+This patch implements the workaround (which is to validate that the
+Stage-1 translation actually succeeds) by using code patching.
+
+Reviewed-by: Will Deacon <will.deacon@arm.com>
+Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
+Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm64/Kconfig | 21 +++++++++++++++++++++
+ arch/arm64/include/asm/cpufeature.h | 3 ++-
+ arch/arm64/kernel/cpu_errata.c | 9 +++++++++
+ arch/arm64/kvm/hyp.S | 6 ++++++
+ 4 files changed, 38 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/Kconfig
++++ b/arch/arm64/Kconfig
+@@ -311,6 +311,27 @@ config ARM64_ERRATUM_832075
+
+ If unsure, say Y.
+
++config ARM64_ERRATUM_834220
++ bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
++ depends on KVM
++ default y
++ help
++ This option adds an alternative code sequence to work around ARM
++ erratum 834220 on Cortex-A57 parts up to r1p2.
++
++ Affected Cortex-A57 parts might report a Stage 2 translation
++ fault as a the result of a Stage 1 fault for a load crossing
++ a page boundary when there is a Stage 1 permission or device
++ memory alignment fault and a Stage 2 translation fault
++
++ The workaround is to verify that the Stage-1 translation
++ doesn't generate a fault before handling the Stage-2 fault.
++ Please note that this does not necessarily enable the workaround,
++ as it depends on the alternative framework, which will only patch
++ the kernel if an affected CPU is detected.
++
++ If unsure, say Y.
++
+ config ARM64_ERRATUM_845719
+ bool "Cortex-A53: 845719: a load might read incorrect data"
+ depends on COMPAT
+--- a/arch/arm64/include/asm/cpufeature.h
++++ b/arch/arm64/include/asm/cpufeature.h
+@@ -27,8 +27,9 @@
+ #define ARM64_HAS_SYSREG_GIC_CPUIF 3
+ #define ARM64_HAS_PAN 4
+ #define ARM64_HAS_LSE_ATOMICS 5
++#define ARM64_WORKAROUND_834220 6
+
+-#define ARM64_NCAPS 6
++#define ARM64_NCAPS 7
+
+ #ifndef __ASSEMBLY__
+
+--- a/arch/arm64/kernel/cpu_errata.c
++++ b/arch/arm64/kernel/cpu_errata.c
+@@ -74,6 +74,15 @@ const struct arm64_cpu_capabilities arm6
+ (1 << MIDR_VARIANT_SHIFT) | 2),
+ },
+ #endif
++#ifdef CONFIG_ARM64_ERRATUM_834220
++ {
++ /* Cortex-A57 r0p0 - r1p2 */
++ .desc = "ARM erratum 834220",
++ .capability = ARM64_WORKAROUND_834220,
++ MIDR_RANGE(MIDR_CORTEX_A57, 0x00,
++ (1 << MIDR_VARIANT_SHIFT) | 2),
++ },
++#endif
+ #ifdef CONFIG_ARM64_ERRATUM_845719
+ {
+ /* Cortex-A53 r0p[01234] */
+--- a/arch/arm64/kvm/hyp.S
++++ b/arch/arm64/kvm/hyp.S
+@@ -1007,9 +1007,15 @@ el1_trap:
+ b.ne 1f // Not an abort we care about
+
+ /* This is an abort. Check for permission fault */
++alternative_if_not ARM64_WORKAROUND_834220
+ and x2, x1, #ESR_ELx_FSC_TYPE
+ cmp x2, #FSC_PERM
+ b.ne 1f // Not a permission fault
++alternative_else
++ nop // Force a Stage-1 translation to occur
++ nop // and return to the guest if it failed
++ nop
++alternative_endif
+
+ /*
+ * Check for Stage-1 page table walk, which is guaranteed
--- /dev/null
+From 92e788b749862ebe9920360513a718e5dd4da7a9 Mon Sep 17 00:00:00 2001
+From: Yang Shi <yang.shi@linaro.org>
+Date: Wed, 18 Nov 2015 10:48:55 -0800
+Subject: arm64: restore bogomips information in /proc/cpuinfo
+
+From: Yang Shi <yang.shi@linaro.org>
+
+commit 92e788b749862ebe9920360513a718e5dd4da7a9 upstream.
+
+As previously reported, some userspace applications depend on bogomips
+showed by /proc/cpuinfo. Although there is much less legacy impact on
+aarch64 than arm, it does break libvirt.
+
+This patch reverts commit 326b16db9f69 ("arm64: delay: don't bother
+reporting bogomips in /proc/cpuinfo"), but with some tweak due to
+context change and without the pr_info().
+
+Fixes: 326b16db9f69 ("arm64: delay: don't bother reporting bogomips in /proc/cpuinfo")
+Signed-off-by: Yang Shi <yang.shi@linaro.org>
+Acked-by: Will Deacon <will.deacon@arm.com>
+Cc: <stable@vger.kernel.org> # 3.12+
+Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm64/kernel/setup.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/arm64/kernel/setup.c
++++ b/arch/arm64/kernel/setup.c
+@@ -558,6 +558,10 @@ static int c_show(struct seq_file *m, vo
+ */
+ seq_printf(m, "processor\t: %d\n", i);
+
++ seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
++ loops_per_jiffy / (500000UL/HZ),
++ loops_per_jiffy / (5000UL/HZ) % 100);
++
+ /*
+ * Dump out the common processor features in a single line.
+ * Userspace should read the hwcaps with getauxval(AT_HWCAP)
projects / thirdparty / kernel / stable-queue.git / commitdiff
