RISC-V: Improve bitwise and ashift reassociation for single-bit immediate without...

When zbs is not available, there's nothing special with single-bit
immediates and we should perform reassociation as normal immediates.

gcc/ChangeLog:

	PR target/115921
	* config/riscv/riscv.md (<optab>_shift_reverse): Only check
	popcount_hwi if !TARGET_ZBS.

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 0922cab4402c4df4997ef4b65c87bdcd6dcca460..0a76ed63f0d10227c86279e4db1496d20ed771c6 100644 (file)
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2969,9 +2969,9 @@
 ;; for IOR/XOR.  It probably doesn't matter for AND.
 ;;
 ;; We also don't want to do this if the immediate already fits in a simm12
-;; field, or is a single bit operand, or when we might be able to generate
-;; a shift-add sequence via the splitter in bitmanip.md
-;; in bitmanip.md for masks that are a run of consecutive ones.
+;; field, or it is a single bit operand and zbs is available, or when we
+;; might be able to generate a shift-add sequence via the splitter in
+;; bitmanip.md for masks that are a run of consecutive ones.
 (define_insn_and_split "<optab>_shift_reverse<X:mode>"
   [(set (match_operand:X 0 "register_operand" "=r")
     (any_bitwise:X (ashift:X (match_operand:X 1 "register_operand" "r")
@@ -2979,7 +2979,7 @@
                   (match_operand 3 "immediate_operand" "n")))]
   "(!SMALL_OPERAND (INTVAL (operands[3]))
     && SMALL_OPERAND (INTVAL (operands[3]) >> INTVAL (operands[2]))
-    && popcount_hwi (INTVAL (operands[3])) > 1
+    && (!TARGET_ZBS || popcount_hwi (INTVAL (operands[3])) > 1)
     && (!(TARGET_64BIT && TARGET_ZBA)
        || !consecutive_bits_operand (operands[3], VOIDmode)
        || !imm123_operand (operands[2], VOIDmode))