s390: Vector shift: Add 128-bit integer support

Add 128-bit vector shift support.  Deprecate vector shift by byte
builtins where the shift amount is not of type unsigned character.

gcc/ChangeLog:

	* config/s390/s390-builtins.def: Add 128-bit variants.
	* config/s390/s390-builtin-types.def: Update accordingly.
	* config/s390/vector.md (<vec_shifts_name><mode>3): Add 128-bit
	variants.
	* config/s390/vx-builtins.md: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/s390/vector/vec-shift-10.c: New test.
	* gcc.target/s390/vector/vec-shift-11.c: New test.
	* gcc.target/s390/vector/vec-shift-12.c: New test.
	* gcc.target/s390/vector/vec-shift-3.c: New test.
	* gcc.target/s390/vector/vec-shift-4.c: New test.
	* gcc.target/s390/vector/vec-shift-5.c: New test.
	* gcc.target/s390/vector/vec-shift-6.c: New test.
	* gcc.target/s390/vector/vec-shift-7.c: New test.
	* gcc.target/s390/vector/vec-shift-8.c: New test.
	* gcc.target/s390/vector/vec-shift-9.c: New test.

diff --git a/gcc/config/s390/s390-builtin-types.def b/gcc/config/s390/s390-builtin-types.def
index dc61c04848ea6c7d1edb6664bcc8ba6cbbded8e6..37783734453f6a9092a2f77adaa3305aa99ba0d0 100644 (file)
--- a/gcc/config/s390/s390-builtin-types.def
+++ b/gcc/config/s390/s390-builtin-types.def
@@ -607,12 +607,17 @@ DEF_OV_TYPE (BT_OV_UV1TI_LONG_UINT128CONSTPTR, BT_UV1TI, BT_LONG, BT_UINT128CONS
 DEF_OV_TYPE (BT_OV_UV1TI_UINT128, BT_UV1TI, BT_UINT128)
 DEF_OV_TYPE (BT_OV_UV1TI_UINT128CONSTPTR_USHORT, BT_UV1TI, BT_UINT128CONSTPTR, BT_USHORT)
 DEF_OV_TYPE (BT_OV_UV1TI_UV1TI, BT_UV1TI, BT_UV1TI)
+DEF_OV_TYPE (BT_OV_UV1TI_UV1TI_UV16QI, BT_UV1TI, BT_UV1TI, BT_UV16QI)
 DEF_OV_TYPE (BT_OV_UV1TI_UV1TI_UV1TI, BT_UV1TI, BT_UV1TI, BT_UV1TI)
 DEF_OV_TYPE (BT_OV_UV1TI_UV1TI_UV1TI_BV1TI, BT_UV1TI, BT_UV1TI, BT_UV1TI, BT_BV1TI)
+DEF_OV_TYPE (BT_OV_UV1TI_UV1TI_UV1TI_INT, BT_UV1TI, BT_UV1TI, BT_UV1TI, BT_INT)
+DEF_OV_TYPE (BT_OV_UV1TI_UV1TI_UV1TI_UINT, BT_UV1TI, BT_UV1TI, BT_UV1TI, BT_UINT)
+DEF_OV_TYPE (BT_OV_UV1TI_UV1TI_UV1TI_ULONGLONG, BT_UV1TI, BT_UV1TI, BT_UV1TI, BT_ULONGLONG)
 DEF_OV_TYPE (BT_OV_UV1TI_UV1TI_UV1TI_UV16QI, BT_UV1TI, BT_UV1TI, BT_UV1TI, BT_UV16QI)
 DEF_OV_TYPE (BT_OV_UV1TI_UV1TI_UV1TI_UV1TI, BT_UV1TI, BT_UV1TI, BT_UV1TI, BT_UV1TI)
 DEF_OV_TYPE (BT_OV_UV1TI_UV1TI_UV1TI_UV1TI_INT, BT_UV1TI, BT_UV1TI, BT_UV1TI, BT_UV1TI, BT_INT)
 DEF_OV_TYPE (BT_OV_UV1TI_UV1TI_UV1TI_V1TI, BT_UV1TI, BT_UV1TI, BT_UV1TI, BT_V1TI)
+DEF_OV_TYPE (BT_OV_UV1TI_UV1TI_V1TI, BT_UV1TI, BT_UV1TI, BT_V1TI)
 DEF_OV_TYPE (BT_OV_UV1TI_UV2DI, BT_UV1TI, BT_UV2DI)
 DEF_OV_TYPE (BT_OV_UV1TI_UV2DI_UV2DI, BT_UV1TI, BT_UV2DI, BT_UV2DI)
 DEF_OV_TYPE (BT_OV_UV1TI_UV2DI_UV2DI_UV1TI, BT_UV1TI, BT_UV2DI, BT_UV2DI, BT_UV1TI)
@@ -768,9 +773,14 @@ DEF_OV_TYPE (BT_OV_V1TI_INT128CONSTPTR_USHORT, BT_V1TI, BT_INT128CONSTPTR, BT_US
 DEF_OV_TYPE (BT_OV_V1TI_LONG_INT128CONSTPTR, BT_V1TI, BT_LONG, BT_INT128CONSTPTR)
 DEF_OV_TYPE (BT_OV_V1TI_UV1TI_V1TI_V1TI, BT_V1TI, BT_UV1TI, BT_V1TI, BT_V1TI)
 DEF_OV_TYPE (BT_OV_V1TI_V1TI, BT_V1TI, BT_V1TI)
+DEF_OV_TYPE (BT_OV_V1TI_V1TI_UV16QI, BT_V1TI, BT_V1TI, BT_UV16QI)
+DEF_OV_TYPE (BT_OV_V1TI_V1TI_UV1TI, BT_V1TI, BT_V1TI, BT_UV1TI)
 DEF_OV_TYPE (BT_OV_V1TI_V1TI_UV1TI_UV1TI, BT_V1TI, BT_V1TI, BT_UV1TI, BT_UV1TI)
 DEF_OV_TYPE (BT_OV_V1TI_V1TI_V1TI, BT_V1TI, BT_V1TI, BT_V1TI)
 DEF_OV_TYPE (BT_OV_V1TI_V1TI_V1TI_BV1TI, BT_V1TI, BT_V1TI, BT_V1TI, BT_BV1TI)
+DEF_OV_TYPE (BT_OV_V1TI_V1TI_V1TI_INT, BT_V1TI, BT_V1TI, BT_V1TI, BT_INT)
+DEF_OV_TYPE (BT_OV_V1TI_V1TI_V1TI_UINT, BT_V1TI, BT_V1TI, BT_V1TI, BT_UINT)
+DEF_OV_TYPE (BT_OV_V1TI_V1TI_V1TI_ULONGLONG, BT_V1TI, BT_V1TI, BT_V1TI, BT_ULONGLONG)
 DEF_OV_TYPE (BT_OV_V1TI_V1TI_V1TI_UV16QI, BT_V1TI, BT_V1TI, BT_V1TI, BT_UV16QI)
 DEF_OV_TYPE (BT_OV_V1TI_V1TI_V1TI_UV1TI, BT_V1TI, BT_V1TI, BT_V1TI, BT_UV1TI)
 DEF_OV_TYPE (BT_OV_V1TI_V1TI_V1TI_V1TI, BT_V1TI, BT_V1TI, BT_V1TI, BT_V1TI)
@@ -792,6 +802,7 @@ DEF_OV_TYPE (BT_OV_V2DF_V2DF, BT_V2DF, BT_V2DF)
 DEF_OV_TYPE (BT_OV_V2DF_V2DF_BV2DI, BT_V2DF, BT_V2DF, BT_BV2DI)
 DEF_OV_TYPE (BT_OV_V2DF_V2DF_UCHAR, BT_V2DF, BT_V2DF, BT_UCHAR)
 DEF_OV_TYPE (BT_OV_V2DF_V2DF_UCHAR_UCHAR, BT_V2DF, BT_V2DF, BT_UCHAR, BT_UCHAR)
+DEF_OV_TYPE (BT_OV_V2DF_V2DF_UV16QI, BT_V2DF, BT_V2DF, BT_UV16QI)
 DEF_OV_TYPE (BT_OV_V2DF_V2DF_UV2DI, BT_V2DF, BT_V2DF, BT_UV2DI)
 DEF_OV_TYPE (BT_OV_V2DF_V2DF_UV2DI_DBLCONSTPTR_UCHAR, BT_V2DF, BT_V2DF, BT_UV2DI, BT_DBLCONSTPTR, BT_UCHAR)
 DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF, BT_V2DF, BT_V2DF, BT_V2DF)
@@ -856,6 +867,7 @@ DEF_OV_TYPE (BT_OV_V4SF_V4SF, BT_V4SF, BT_V4SF)
 DEF_OV_TYPE (BT_OV_V4SF_V4SF_BV4SI, BT_V4SF, BT_V4SF, BT_BV4SI)
 DEF_OV_TYPE (BT_OV_V4SF_V4SF_UCHAR, BT_V4SF, BT_V4SF, BT_UCHAR)
 DEF_OV_TYPE (BT_OV_V4SF_V4SF_UCHAR_UCHAR, BT_V4SF, BT_V4SF, BT_UCHAR, BT_UCHAR)
+DEF_OV_TYPE (BT_OV_V4SF_V4SF_UV16QI, BT_V4SF, BT_V4SF, BT_UV16QI)
 DEF_OV_TYPE (BT_OV_V4SF_V4SF_UV4SI, BT_V4SF, BT_V4SF, BT_UV4SI)
 DEF_OV_TYPE (BT_OV_V4SF_V4SF_UV4SI_FLTCONSTPTR_UCHAR, BT_V4SF, BT_V4SF, BT_UV4SI, BT_FLTCONSTPTR, BT_UCHAR)
 DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF, BT_V4SF, BT_V4SF, BT_V4SF)

diff --git a/gcc/config/s390/s390-builtins.def b/gcc/config/s390/s390-builtins.def
index b1c3938abe5c9a24d32f61c2f2710ae06f3d51e3..24941ed03515ce515a7bc8dcb0a235c7d2b28289 100644 (file)
--- a/gcc/config/s390/s390-builtins.def
+++ b/gcc/config/s390/s390-builtins.def
@@ -2214,7 +2214,7 @@ B_DEF      (s390_verimh,                verimv8hi,          0,
 B_DEF      (s390_verimf,                verimv4si,          0,                  B_VX,               O4_U8,              BT_FN_UV4SI_UV4SI_UV4SI_UV4SI_INT)
 B_DEF      (s390_verimg,                verimv2di,          0,                  B_VX,               O4_U8,              BT_FN_UV2DI_UV2DI_UV2DI_UV2DI_INT)
 
-OB_DEF     (s390_vec_sll,               s390_vec_sll_u8q,   s390_vec_sll_b64s,  B_VX,               BT_FN_OV4SI_OV4SI_OV4SI)
+OB_DEF     (s390_vec_sll,               s390_vec_sll_u8q,   s390_vec_sll_s128,  B_VX,               BT_FN_OV4SI_OV4SI_OV4SI)
 OB_DEF_VAR (s390_vec_sll_u8q,           s390_vsl,           0,                  0,                  BT_OV_UV16QI_UV16QI_UV16QI)
 OB_DEF_VAR (s390_vec_sll_u8h,           s390_vsl,           B_DEP,              0,                  BT_OV_UV16QI_UV16QI_UV8HI)
 OB_DEF_VAR (s390_vec_sll_u8s,           s390_vsl,           B_DEP,              0,                  BT_OV_UV16QI_UV16QI_UV4SI)
@@ -2251,46 +2251,64 @@ OB_DEF_VAR (s390_vec_sll_s64s,          s390_vsl,           B_DEP,
 OB_DEF_VAR (s390_vec_sll_b64q,          s390_vsl,           B_DEP,              0,                  BT_OV_BV2DI_BV2DI_UV16QI)
 OB_DEF_VAR (s390_vec_sll_b64h,          s390_vsl,           B_DEP,              0,                  BT_OV_BV2DI_BV2DI_UV8HI)
 OB_DEF_VAR (s390_vec_sll_b64s,          s390_vsl,           B_DEP,              0,                  BT_OV_BV2DI_BV2DI_UV4SI)
+OB_DEF_VAR (s390_vec_sll_u128,          s390_vsl,           0,                  0,                  BT_OV_UV1TI_UV1TI_UV16QI)
+OB_DEF_VAR (s390_vec_sll_s128,          s390_vsl,           0,                  0,                  BT_OV_V1TI_V1TI_UV16QI)
 
 B_DEF      (s390_vsl,                   vec_sllv16qiv16qi,  0,                  B_VX,               0,                  BT_FN_UV16QI_UV16QI_UV16QI)
 
-OB_DEF     (s390_vec_slb,               s390_vec_slb_u8_u8, s390_vec_slb_dbl_s64,B_VX,              BT_FN_OV4SI_OV4SI_OV4SI)
+OB_DEF     (s390_vec_slb,               s390_vec_slb_u8_s8, s390_vec_slb_dbl_u8,B_VX,               BT_FN_OV4SI_OV4SI_OV4SI)
+OB_DEF_VAR (s390_vec_slb_u8_s8,         s390_vslb,          B_DEP,              0,                  BT_OV_UV16QI_UV16QI_V16QI)
+OB_DEF_VAR (s390_vec_slb_s8_s8,         s390_vslb,          B_DEP,              0,                  BT_OV_V16QI_V16QI_V16QI)
+OB_DEF_VAR (s390_vec_slb_u16_u16,       s390_vslb,          B_DEP,              0,                  BT_OV_UV8HI_UV8HI_UV8HI)
+OB_DEF_VAR (s390_vec_slb_u16_s16,       s390_vslb,          B_DEP,              0,                  BT_OV_UV8HI_UV8HI_V8HI)
+OB_DEF_VAR (s390_vec_slb_s16_u16,       s390_vslb,          B_DEP,              0,                  BT_OV_V8HI_V8HI_UV8HI)
+OB_DEF_VAR (s390_vec_slb_s16_s16,       s390_vslb,          B_DEP,              0,                  BT_OV_V8HI_V8HI_V8HI)
+OB_DEF_VAR (s390_vec_slb_u32_u32,       s390_vslb,          B_DEP,              0,                  BT_OV_UV4SI_UV4SI_UV4SI)
+OB_DEF_VAR (s390_vec_slb_u32_s32,       s390_vslb,          B_DEP,              0,                  BT_OV_UV4SI_UV4SI_V4SI)
+OB_DEF_VAR (s390_vec_slb_s32_u32,       s390_vslb,          B_DEP,              0,                  BT_OV_V4SI_V4SI_UV4SI)
+OB_DEF_VAR (s390_vec_slb_s32_s32,       s390_vslb,          B_DEP,              0,                  BT_OV_V4SI_V4SI_V4SI)
+OB_DEF_VAR (s390_vec_slb_u64_u64,       s390_vslb,          B_DEP,              0,                  BT_OV_UV2DI_UV2DI_UV2DI)
+OB_DEF_VAR (s390_vec_slb_u64_s64,       s390_vslb,          B_DEP,              0,                  BT_OV_UV2DI_UV2DI_V2DI)
+OB_DEF_VAR (s390_vec_slb_s64_u64,       s390_vslb,          B_DEP,              0,                  BT_OV_V2DI_V2DI_UV2DI)
+OB_DEF_VAR (s390_vec_slb_s64_s64,       s390_vslb,          B_DEP,              0,                  BT_OV_V2DI_V2DI_V2DI)
+OB_DEF_VAR (s390_vec_slb_u128_u128,     s390_vslb,          B_DEP,              0,                  BT_OV_UV1TI_UV1TI_UV1TI)
+OB_DEF_VAR (s390_vec_slb_u128_s128,     s390_vslb,          B_DEP,              0,                  BT_OV_UV1TI_UV1TI_V1TI)
+OB_DEF_VAR (s390_vec_slb_s128_u128,     s390_vslb,          B_DEP,              0,                  BT_OV_V1TI_V1TI_UV1TI)
+OB_DEF_VAR (s390_vec_slb_s128_s128,     s390_vslb,          B_DEP,              0,                  BT_OV_V1TI_V1TI_V1TI)
+OB_DEF_VAR (s390_vec_slb_flt_u64,       s390_vslb,          B_DEP | B_VXE,      0,                  BT_OV_V4SF_V4SF_UV4SI)
+OB_DEF_VAR (s390_vec_slb_dbl_u64,       s390_vslb,          B_DEP,              0,                  BT_OV_V2DF_V2DF_UV2DI)
+OB_DEF_VAR (s390_vec_slb_flt_s64,       s390_vslb,          B_DEP | B_VXE,      0,                  BT_OV_V4SF_V4SF_V4SI)
+OB_DEF_VAR (s390_vec_slb_dbl_s64,       s390_vslb,          B_DEP,              0,                  BT_OV_V2DF_V2DF_V2DI)
 OB_DEF_VAR (s390_vec_slb_u8_u8,         s390_vslb,          0,                  0,                  BT_OV_UV16QI_UV16QI_UV16QI)
-OB_DEF_VAR (s390_vec_slb_u8_s8,         s390_vslb,          0,                  0,                  BT_OV_UV16QI_UV16QI_V16QI)
 OB_DEF_VAR (s390_vec_slb_s8_u8,         s390_vslb,          0,                  0,                  BT_OV_V16QI_V16QI_UV16QI)
-OB_DEF_VAR (s390_vec_slb_s8_s8,         s390_vslb,          0,                  0,                  BT_OV_V16QI_V16QI_V16QI)
-OB_DEF_VAR (s390_vec_slb_u16_u16,       s390_vslb,          0,                  0,                  BT_OV_UV8HI_UV8HI_UV8HI)
-OB_DEF_VAR (s390_vec_slb_u16_s16,       s390_vslb,          0,                  0,                  BT_OV_UV8HI_UV8HI_V8HI)
-OB_DEF_VAR (s390_vec_slb_s16_u16,       s390_vslb,          0,                  0,                  BT_OV_V8HI_V8HI_UV8HI)
-OB_DEF_VAR (s390_vec_slb_s16_s16,       s390_vslb,          0,                  0,                  BT_OV_V8HI_V8HI_V8HI)
-OB_DEF_VAR (s390_vec_slb_u32_u32,       s390_vslb,          0,                  0,                  BT_OV_UV4SI_UV4SI_UV4SI)
-OB_DEF_VAR (s390_vec_slb_u32_s32,       s390_vslb,          0,                  0,                  BT_OV_UV4SI_UV4SI_V4SI)
-OB_DEF_VAR (s390_vec_slb_s32_u32,       s390_vslb,          0,                  0,                  BT_OV_V4SI_V4SI_UV4SI)
-OB_DEF_VAR (s390_vec_slb_s32_s32,       s390_vslb,          0,                  0,                  BT_OV_V4SI_V4SI_V4SI)
-OB_DEF_VAR (s390_vec_slb_u64_u64,       s390_vslb,          0,                  0,                  BT_OV_UV2DI_UV2DI_UV2DI)
-OB_DEF_VAR (s390_vec_slb_u64_s64,       s390_vslb,          0,                  0,                  BT_OV_UV2DI_UV2DI_V2DI)
-OB_DEF_VAR (s390_vec_slb_s64_u64,       s390_vslb,          0,                  0,                  BT_OV_V2DI_V2DI_UV2DI)
-OB_DEF_VAR (s390_vec_slb_s64_s64,       s390_vslb,          0,                  0,                  BT_OV_V2DI_V2DI_V2DI)
-OB_DEF_VAR (s390_vec_slb_flt_u64,       s390_vslb,          B_VXE,              0,                  BT_OV_V4SF_V4SF_UV4SI)
-OB_DEF_VAR (s390_vec_slb_dbl_u64,       s390_vslb,          0,                  0,                  BT_OV_V2DF_V2DF_UV2DI)
-OB_DEF_VAR (s390_vec_slb_flt_s64,       s390_vslb,          B_VXE,              0,                  BT_OV_V4SF_V4SF_V4SI)
-OB_DEF_VAR (s390_vec_slb_dbl_s64,       s390_vslb,          0,                  0,                  BT_OV_V2DF_V2DF_V2DI)
+OB_DEF_VAR (s390_vec_slb_u16_u8,        s390_vslb,          0,                  0,                  BT_OV_UV8HI_UV8HI_UV16QI)
+OB_DEF_VAR (s390_vec_slb_s16_u8,        s390_vslb,          0,                  0,                  BT_OV_V8HI_V8HI_UV16QI)
+OB_DEF_VAR (s390_vec_slb_u32_u8,        s390_vslb,          0,                  0,                  BT_OV_UV4SI_UV4SI_UV16QI)
+OB_DEF_VAR (s390_vec_slb_s32_u8,        s390_vslb,          0,                  0,                  BT_OV_V4SI_V4SI_UV16QI)
+OB_DEF_VAR (s390_vec_slb_u64_u8,        s390_vslb,          0,                  0,                  BT_OV_UV2DI_UV2DI_UV16QI)
+OB_DEF_VAR (s390_vec_slb_s64_u8,        s390_vslb,          0,                  0,                  BT_OV_V2DI_V2DI_UV16QI)
+OB_DEF_VAR (s390_vec_slb_u128_u8,       s390_vslb,          0,                  0,                  BT_OV_UV1TI_UV1TI_UV16QI)
+OB_DEF_VAR (s390_vec_slb_s128_u8,       s390_vslb,          0,                  0,                  BT_OV_V1TI_V1TI_UV16QI)
+OB_DEF_VAR (s390_vec_slb_flt_u8,        s390_vslb,          B_VXE,              0,                  BT_OV_V4SF_V4SF_UV16QI)
+OB_DEF_VAR (s390_vec_slb_dbl_u8,        s390_vslb,          0,                  0,                  BT_OV_V2DF_V2DF_UV16QI)
 
 B_DEF      (s390_vslb,                  vec_slbv16qi,       0,                  B_VX,               0,                  BT_FN_UV16QI_UV16QI_UV16QI)
 
 OB_DEF     (s390_vec_sld,               s390_vec_sld_b8,    s390_vec_sld_dbl,   B_VX,               BT_FN_OV4SI_OV4SI_OV4SI_ULONGLONG)
-OB_DEF_VAR (s390_vec_sld_b8,            s390_vsldb,         0,                  O3_U4,              BT_OV_BV16QI_BV16QI_BV16QI_ULONGLONG)
+OB_DEF_VAR (s390_vec_sld_b8,            s390_vsldb,         B_DEP,              O3_U4,              BT_OV_BV16QI_BV16QI_BV16QI_ULONGLONG)
 OB_DEF_VAR (s390_vec_sld_s8,            s390_vsldb,         0,                  O3_U4,              BT_OV_V16QI_V16QI_V16QI_ULONGLONG)
 OB_DEF_VAR (s390_vec_sld_u8,            s390_vsldb,         0,                  O3_U4,              BT_OV_UV16QI_UV16QI_UV16QI_ULONGLONG)
-OB_DEF_VAR (s390_vec_sld_b16,           s390_vsldb,         0,                  O3_U4,              BT_OV_BV8HI_BV8HI_BV8HI_ULONGLONG)
+OB_DEF_VAR (s390_vec_sld_b16,           s390_vsldb,         B_DEP,              O3_U4,              BT_OV_BV8HI_BV8HI_BV8HI_ULONGLONG)
 OB_DEF_VAR (s390_vec_sld_s16,           s390_vsldb,         0,                  O3_U4,              BT_OV_V8HI_V8HI_V8HI_ULONGLONG)
 OB_DEF_VAR (s390_vec_sld_u16,           s390_vsldb,         0,                  O3_U4,              BT_OV_UV8HI_UV8HI_UV8HI_ULONGLONG)
-OB_DEF_VAR (s390_vec_sld_b32,           s390_vsldb,         0,                  O3_U4,              BT_OV_BV4SI_BV4SI_BV4SI_ULONGLONG)
+OB_DEF_VAR (s390_vec_sld_b32,           s390_vsldb,         B_DEP,              O3_U4,              BT_OV_BV4SI_BV4SI_BV4SI_ULONGLONG)
 OB_DEF_VAR (s390_vec_sld_s32,           s390_vsldb,         0,                  O3_U4,              BT_OV_V4SI_V4SI_V4SI_ULONGLONG)
 OB_DEF_VAR (s390_vec_sld_u32,           s390_vsldb,         0,                  O3_U4,              BT_OV_UV4SI_UV4SI_UV4SI_ULONGLONG)
-OB_DEF_VAR (s390_vec_sld_b64,           s390_vsldb,         0,                  O3_U4,              BT_OV_BV2DI_BV2DI_BV2DI_ULONGLONG)
+OB_DEF_VAR (s390_vec_sld_b64,           s390_vsldb,         B_DEP,              O3_U4,              BT_OV_BV2DI_BV2DI_BV2DI_ULONGLONG)
 OB_DEF_VAR (s390_vec_sld_s64,           s390_vsldb,         0,                  O3_U4,              BT_OV_V2DI_V2DI_V2DI_ULONGLONG)
 OB_DEF_VAR (s390_vec_sld_u64,           s390_vsldb,         0,                  O3_U4,              BT_OV_UV2DI_UV2DI_UV2DI_ULONGLONG)
+OB_DEF_VAR (s390_vec_sld_s128,          s390_vsldb,         0,                  O3_U4,              BT_OV_V1TI_V1TI_V1TI_ULONGLONG)
+OB_DEF_VAR (s390_vec_sld_u128,          s390_vsldb,         0,                  O3_U4,              BT_OV_UV1TI_UV1TI_UV1TI_ULONGLONG)
 OB_DEF_VAR (s390_vec_sld_flt,           s390_vsldb,         B_VXE,              O3_U4,              BT_OV_V4SF_V4SF_V4SF_ULONGLONG)
 OB_DEF_VAR (s390_vec_sld_dbl,           s390_vsldb,         0,                  O3_U4,              BT_OV_V2DF_V2DF_V2DF_ULONGLONG)
 
@@ -2305,11 +2323,13 @@ OB_DEF_VAR (s390_vec_sldw_s32,          s390_vsldw,         0,
 OB_DEF_VAR (s390_vec_sldw_u32,          s390_vsldw,         0,                  O3_U4,              BT_OV_UV4SI_UV4SI_UV4SI_INT)
 OB_DEF_VAR (s390_vec_sldw_s64,          s390_vsldw,         0,                  O3_U4,              BT_OV_V2DI_V2DI_V2DI_INT)
 OB_DEF_VAR (s390_vec_sldw_u64,          s390_vsldw,         0,                  O3_U4,              BT_OV_UV2DI_UV2DI_UV2DI_INT)
+OB_DEF_VAR (s390_vec_sldw_s128,         s390_vsldw,         0,                  O3_U4,              BT_OV_V1TI_V1TI_V1TI_INT)
+OB_DEF_VAR (s390_vec_sldw_u128,         s390_vsldw,         0,                  O3_U4,              BT_OV_UV1TI_UV1TI_UV1TI_INT)
 OB_DEF_VAR (s390_vec_sldw_dbl,          s390_vsldw,         B_DEP,              O3_U4,              BT_OV_V2DF_V2DF_V2DF_INT)
 
 B_DEF      (s390_vsldw,                 vec_sldwv16qi,      0,                  B_VX,               O3_U4,              BT_FN_UV16QI_UV16QI_UV16QI_INT)
 
-OB_DEF     (s390_vec_sral,              s390_vec_sral_u8q,  s390_vec_sral_b64s, B_VX,               BT_FN_OV4SI_OV4SI_OV4SI)
+OB_DEF     (s390_vec_sral,              s390_vec_sral_u8q,  s390_vec_sral_s128, B_VX,               BT_FN_OV4SI_OV4SI_OV4SI)
 OB_DEF_VAR (s390_vec_sral_u8q,          s390_vsra,          0,                  0,                  BT_OV_UV16QI_UV16QI_UV16QI)
 OB_DEF_VAR (s390_vec_sral_u8h,          s390_vsra,          B_DEP,              0,                  BT_OV_UV16QI_UV16QI_UV8HI)
 OB_DEF_VAR (s390_vec_sral_u8s,          s390_vsra,          B_DEP,              0,                  BT_OV_UV16QI_UV16QI_UV4SI)
@@ -2346,34 +2366,50 @@ OB_DEF_VAR (s390_vec_sral_s64s,         s390_vsra,          B_DEP,
 OB_DEF_VAR (s390_vec_sral_b64q,         s390_vsra,          B_DEP,              0,                  BT_OV_BV2DI_BV2DI_UV16QI)
 OB_DEF_VAR (s390_vec_sral_b64h,         s390_vsra,          B_DEP,              0,                  BT_OV_BV2DI_BV2DI_UV8HI)
 OB_DEF_VAR (s390_vec_sral_b64s,         s390_vsra,          B_DEP,              0,                  BT_OV_BV2DI_BV2DI_UV4SI)
+OB_DEF_VAR (s390_vec_sral_u128,         s390_vsra,          0,                  0,                  BT_OV_UV1TI_UV1TI_UV16QI)
+OB_DEF_VAR (s390_vec_sral_s128,         s390_vsra,          0,                  0,                  BT_OV_V1TI_V1TI_UV16QI)
 
 B_DEF      (s390_vsra,                  vec_sralv16qiv16qi, 0,                  B_VX,               0,                  BT_FN_UV16QI_UV16QI_UV16QI)
 
-OB_DEF     (s390_vec_srab,              s390_vec_srab_u8_u8,s390_vec_srab_dbl_s64,B_VX,             BT_FN_OV4SI_OV4SI_OV4SI)
+OB_DEF     (s390_vec_srab,              s390_vec_srab_u8_s8,s390_vec_srab_dbl_u8,B_VX,              BT_FN_OV4SI_OV4SI_OV4SI)
+OB_DEF_VAR (s390_vec_srab_u8_s8,        s390_vsrab,         B_DEP,              0,                  BT_OV_UV16QI_UV16QI_V16QI)
+OB_DEF_VAR (s390_vec_srab_s8_s8,        s390_vsrab,         B_DEP,              0,                  BT_OV_V16QI_V16QI_V16QI)
+OB_DEF_VAR (s390_vec_srab_u16_u16,      s390_vsrab,         B_DEP,              0,                  BT_OV_UV8HI_UV8HI_UV8HI)
+OB_DEF_VAR (s390_vec_srab_u16_s16,      s390_vsrab,         B_DEP,              0,                  BT_OV_UV8HI_UV8HI_V8HI)
+OB_DEF_VAR (s390_vec_srab_s16_u16,      s390_vsrab,         B_DEP,              0,                  BT_OV_V8HI_V8HI_UV8HI)
+OB_DEF_VAR (s390_vec_srab_s16_s16,      s390_vsrab,         B_DEP,              0,                  BT_OV_V8HI_V8HI_V8HI)
+OB_DEF_VAR (s390_vec_srab_u32_u32,      s390_vsrab,         B_DEP,              0,                  BT_OV_UV4SI_UV4SI_UV4SI)
+OB_DEF_VAR (s390_vec_srab_u32_s32,      s390_vsrab,         B_DEP,              0,                  BT_OV_UV4SI_UV4SI_V4SI)
+OB_DEF_VAR (s390_vec_srab_s32_u32,      s390_vsrab,         B_DEP,              0,                  BT_OV_V4SI_V4SI_UV4SI)
+OB_DEF_VAR (s390_vec_srab_s32_s32,      s390_vsrab,         B_DEP,              0,                  BT_OV_V4SI_V4SI_V4SI)
+OB_DEF_VAR (s390_vec_srab_u64_u64,      s390_vsrab,         B_DEP,              0,                  BT_OV_UV2DI_UV2DI_UV2DI)
+OB_DEF_VAR (s390_vec_srab_u64_s64,      s390_vsrab,         B_DEP,              0,                  BT_OV_UV2DI_UV2DI_V2DI)
+OB_DEF_VAR (s390_vec_srab_s64_u64,      s390_vsrab,         B_DEP,              0,                  BT_OV_V2DI_V2DI_UV2DI)
+OB_DEF_VAR (s390_vec_srab_s64_s64,      s390_vsrab,         B_DEP,              0,                  BT_OV_V2DI_V2DI_V2DI)
+OB_DEF_VAR (s390_vec_srab_u128_u128,    s390_vsrab,         B_DEP,              0,                  BT_OV_UV1TI_UV1TI_UV1TI)
+OB_DEF_VAR (s390_vec_srab_u128_s128,    s390_vsrab,         B_DEP,              0,                  BT_OV_UV1TI_UV1TI_V1TI)
+OB_DEF_VAR (s390_vec_srab_s128_u128,    s390_vsrab,         B_DEP,              0,                  BT_OV_V1TI_V1TI_UV1TI)
+OB_DEF_VAR (s390_vec_srab_s128_s128,    s390_vsrab,         B_DEP,              0,                  BT_OV_V1TI_V1TI_V1TI)
+OB_DEF_VAR (s390_vec_srab_flt_u64,      s390_vsrab,         B_DEP | B_VXE,      0,                  BT_OV_V4SF_V4SF_UV4SI)
+OB_DEF_VAR (s390_vec_srab_dbl_u64,      s390_vsrab,         B_DEP,              0,                  BT_OV_V2DF_V2DF_UV2DI)
+OB_DEF_VAR (s390_vec_srab_flt_s64,      s390_vsrab,         B_DEP | B_VXE,      0,                  BT_OV_V4SF_V4SF_V4SI)
+OB_DEF_VAR (s390_vec_srab_dbl_s64,      s390_vsrab,         B_DEP,              0,                  BT_OV_V2DF_V2DF_V2DI)
 OB_DEF_VAR (s390_vec_srab_u8_u8,        s390_vsrab,         0,                  0,                  BT_OV_UV16QI_UV16QI_UV16QI)
-OB_DEF_VAR (s390_vec_srab_u8_s8,        s390_vsrab,         0,                  0,                  BT_OV_UV16QI_UV16QI_V16QI)
 OB_DEF_VAR (s390_vec_srab_s8_u8,        s390_vsrab,         0,                  0,                  BT_OV_V16QI_V16QI_UV16QI)
-OB_DEF_VAR (s390_vec_srab_s8_s8,        s390_vsrab,         0,                  0,                  BT_OV_V16QI_V16QI_V16QI)
-OB_DEF_VAR (s390_vec_srab_u16_u16,      s390_vsrab,         0,                  0,                  BT_OV_UV8HI_UV8HI_UV8HI)
-OB_DEF_VAR (s390_vec_srab_u16_s16,      s390_vsrab,         0,                  0,                  BT_OV_UV8HI_UV8HI_V8HI)
-OB_DEF_VAR (s390_vec_srab_s16_u16,      s390_vsrab,         0,                  0,                  BT_OV_V8HI_V8HI_UV8HI)
-OB_DEF_VAR (s390_vec_srab_s16_s16,      s390_vsrab,         0,                  0,                  BT_OV_V8HI_V8HI_V8HI)
-OB_DEF_VAR (s390_vec_srab_u32_u32,      s390_vsrab,         0,                  0,                  BT_OV_UV4SI_UV4SI_UV4SI)
-OB_DEF_VAR (s390_vec_srab_u32_s32,      s390_vsrab,         0,                  0,                  BT_OV_UV4SI_UV4SI_V4SI)
-OB_DEF_VAR (s390_vec_srab_s32_u32,      s390_vsrab,         0,                  0,                  BT_OV_V4SI_V4SI_UV4SI)
-OB_DEF_VAR (s390_vec_srab_s32_s32,      s390_vsrab,         0,                  0,                  BT_OV_V4SI_V4SI_V4SI)
-OB_DEF_VAR (s390_vec_srab_u64_u64,      s390_vsrab,         0,                  0,                  BT_OV_UV2DI_UV2DI_UV2DI)
-OB_DEF_VAR (s390_vec_srab_u64_s64,      s390_vsrab,         0,                  0,                  BT_OV_UV2DI_UV2DI_V2DI)
-OB_DEF_VAR (s390_vec_srab_s64_u64,      s390_vsrab,         0,                  0,                  BT_OV_V2DI_V2DI_UV2DI)
-OB_DEF_VAR (s390_vec_srab_s64_s64,      s390_vsrab,         0,                  0,                  BT_OV_V2DI_V2DI_V2DI)
-OB_DEF_VAR (s390_vec_srab_flt_u64,      s390_vsrab,         B_VXE,              0,                  BT_OV_V4SF_V4SF_UV4SI)
-OB_DEF_VAR (s390_vec_srab_dbl_u64,      s390_vsrab,         0,                  0,                  BT_OV_V2DF_V2DF_UV2DI)
-OB_DEF_VAR (s390_vec_srab_flt_s64,      s390_vsrab,         B_VXE,              0,                  BT_OV_V4SF_V4SF_V4SI)
-OB_DEF_VAR (s390_vec_srab_dbl_s64,      s390_vsrab,         0,                  0,                  BT_OV_V2DF_V2DF_V2DI)
+OB_DEF_VAR (s390_vec_srab_u16_u8,       s390_vsrab,         0,                  0,                  BT_OV_UV8HI_UV8HI_UV16QI)
+OB_DEF_VAR (s390_vec_srab_s16_u8,       s390_vsrab,         0,                  0,                  BT_OV_V8HI_V8HI_UV16QI)
+OB_DEF_VAR (s390_vec_srab_u32_u8,       s390_vsrab,         0,                  0,                  BT_OV_UV4SI_UV4SI_UV16QI)
+OB_DEF_VAR (s390_vec_srab_s32_u8,       s390_vsrab,         0,                  0,                  BT_OV_V4SI_V4SI_UV16QI)
+OB_DEF_VAR (s390_vec_srab_u64_u8,       s390_vsrab,         0,                  0,                  BT_OV_UV2DI_UV2DI_UV16QI)
+OB_DEF_VAR (s390_vec_srab_s64_u8,       s390_vsrab,         0,                  0,                  BT_OV_V2DI_V2DI_UV16QI)
+OB_DEF_VAR (s390_vec_srab_u128_u8,      s390_vsrab,         0,                  0,                  BT_OV_UV1TI_UV1TI_UV16QI)
+OB_DEF_VAR (s390_vec_srab_s128_u8,      s390_vsrab,         0,                  0,                  BT_OV_V1TI_V1TI_UV16QI)
+OB_DEF_VAR (s390_vec_srab_flt_u8,       s390_vsrab,         B_VXE,              0,                  BT_OV_V4SF_V4SF_UV16QI)
+OB_DEF_VAR (s390_vec_srab_dbl_u8,       s390_vsrab,         0,                  0,                  BT_OV_V2DF_V2DF_UV16QI)
 
 B_DEF      (s390_vsrab,                 vec_srabv16qi,      0,                  B_VX,               0,                  BT_FN_UV16QI_UV16QI_UV16QI)
 
-OB_DEF     (s390_vec_srl,               s390_vec_srl_u8q,   s390_vec_srl_b64s,  B_VX,               BT_FN_OV4SI_OV4SI_OV4SI)
+OB_DEF     (s390_vec_srl,               s390_vec_srl_u8q,   s390_vec_srl_s128,  B_VX,               BT_FN_OV4SI_OV4SI_OV4SI)
 OB_DEF_VAR (s390_vec_srl_u8q,           s390_vsrl,          0,                  0,                  BT_OV_UV16QI_UV16QI_UV16QI)
 OB_DEF_VAR (s390_vec_srl_u8h,           s390_vsrl,          B_DEP,              0,                  BT_OV_UV16QI_UV16QI_UV8HI)
 OB_DEF_VAR (s390_vec_srl_u8s,           s390_vsrl,          B_DEP,              0,                  BT_OV_UV16QI_UV16QI_UV4SI)
@@ -2410,30 +2446,46 @@ OB_DEF_VAR (s390_vec_srl_s64s,          s390_vsrl,          B_DEP,
 OB_DEF_VAR (s390_vec_srl_b64q,          s390_vsrl,          B_DEP,              0,                  BT_OV_BV2DI_BV2DI_UV16QI)
 OB_DEF_VAR (s390_vec_srl_b64h,          s390_vsrl,          B_DEP,              0,                  BT_OV_BV2DI_BV2DI_UV8HI)
 OB_DEF_VAR (s390_vec_srl_b64s,          s390_vsrl,          B_DEP,              0,                  BT_OV_BV2DI_BV2DI_UV4SI)
+OB_DEF_VAR (s390_vec_srl_u128,          s390_vsrl,          0,                  0,                  BT_OV_UV1TI_UV1TI_UV16QI)
+OB_DEF_VAR (s390_vec_srl_s128,          s390_vsrl,          0,                  0,                  BT_OV_V1TI_V1TI_UV16QI)
 
 B_DEF      (s390_vsrl,                  vec_srlv16qiv16qi,  0,                  B_VX,               0,                  BT_FN_UV16QI_UV16QI_UV16QI)
 
-OB_DEF     (s390_vec_srb,               s390_vec_srb_u8_u8, s390_vec_srb_dbl_s64,B_VX,              BT_FN_OV4SI_OV4SI_OV4SI)
+OB_DEF     (s390_vec_srb,               s390_vec_srb_u8_s8, s390_vec_srb_dbl_u8,B_VX,               BT_FN_OV4SI_OV4SI_OV4SI)
+OB_DEF_VAR (s390_vec_srb_u8_s8,         s390_vsrlb,         B_DEP,              0,                  BT_OV_UV16QI_UV16QI_V16QI)
+OB_DEF_VAR (s390_vec_srb_s8_s8,         s390_vsrlb,         B_DEP,              0,                  BT_OV_V16QI_V16QI_V16QI)
+OB_DEF_VAR (s390_vec_srb_u16_u16,       s390_vsrlb,         B_DEP,              0,                  BT_OV_UV8HI_UV8HI_UV8HI)
+OB_DEF_VAR (s390_vec_srb_u16_s16,       s390_vsrlb,         B_DEP,              0,                  BT_OV_UV8HI_UV8HI_V8HI)
+OB_DEF_VAR (s390_vec_srb_s16_u16,       s390_vsrlb,         B_DEP,              0,                  BT_OV_V8HI_V8HI_UV8HI)
+OB_DEF_VAR (s390_vec_srb_s16_s16,       s390_vsrlb,         B_DEP,              0,                  BT_OV_V8HI_V8HI_V8HI)
+OB_DEF_VAR (s390_vec_srb_u32_u32,       s390_vsrlb,         B_DEP,              0,                  BT_OV_UV4SI_UV4SI_UV4SI)
+OB_DEF_VAR (s390_vec_srb_u32_s32,       s390_vsrlb,         B_DEP,              0,                  BT_OV_UV4SI_UV4SI_V4SI)
+OB_DEF_VAR (s390_vec_srb_s32_u32,       s390_vsrlb,         B_DEP,              0,                  BT_OV_V4SI_V4SI_UV4SI)
+OB_DEF_VAR (s390_vec_srb_s32_s32,       s390_vsrlb,         B_DEP,              0,                  BT_OV_V4SI_V4SI_V4SI)
+OB_DEF_VAR (s390_vec_srb_u64_u64,       s390_vsrlb,         B_DEP,              0,                  BT_OV_UV2DI_UV2DI_UV2DI)
+OB_DEF_VAR (s390_vec_srb_u64_s64,       s390_vsrlb,         B_DEP,              0,                  BT_OV_UV2DI_UV2DI_V2DI)
+OB_DEF_VAR (s390_vec_srb_s64_u64,       s390_vsrlb,         B_DEP,              0,                  BT_OV_V2DI_V2DI_UV2DI)
+OB_DEF_VAR (s390_vec_srb_s64_s64,       s390_vsrlb,         B_DEP,              0,                  BT_OV_V2DI_V2DI_V2DI)
+OB_DEF_VAR (s390_vec_srb_u128_u128,     s390_vsrlb,         B_DEP,              0,                  BT_OV_UV1TI_UV1TI_UV1TI)
+OB_DEF_VAR (s390_vec_srb_u128_s128,     s390_vsrlb,         B_DEP,              0,                  BT_OV_UV1TI_UV1TI_V1TI)
+OB_DEF_VAR (s390_vec_srb_s128_u128,     s390_vsrlb,         B_DEP,              0,                  BT_OV_V1TI_V1TI_UV1TI)
+OB_DEF_VAR (s390_vec_srb_s128_s128,     s390_vsrlb,         B_DEP,              0,                  BT_OV_V1TI_V1TI_V1TI)
+OB_DEF_VAR (s390_vec_srb_flt_u64,       s390_vsrlb,         B_DEP | B_VXE,      0,                  BT_OV_V4SF_V4SF_UV4SI)
+OB_DEF_VAR (s390_vec_srb_dbl_u64,       s390_vsrlb,         B_DEP,              0,                  BT_OV_V2DF_V2DF_UV2DI)
+OB_DEF_VAR (s390_vec_srb_flt_s64,       s390_vsrlb,         B_DEP | B_VXE,      0,                  BT_OV_V4SF_V4SF_V4SI)
+OB_DEF_VAR (s390_vec_srb_dbl_s64,       s390_vsrlb,         B_DEP,              0,                  BT_OV_V2DF_V2DF_V2DI)
 OB_DEF_VAR (s390_vec_srb_u8_u8,         s390_vsrlb,         0,                  0,                  BT_OV_UV16QI_UV16QI_UV16QI)
-OB_DEF_VAR (s390_vec_srb_u8_s8,         s390_vsrlb,         0,                  0,                  BT_OV_UV16QI_UV16QI_V16QI)
 OB_DEF_VAR (s390_vec_srb_s8_u8,         s390_vsrlb,         0,                  0,                  BT_OV_V16QI_V16QI_UV16QI)
-OB_DEF_VAR (s390_vec_srb_s8_s8,         s390_vsrlb,         0,                  0,                  BT_OV_V16QI_V16QI_V16QI)
-OB_DEF_VAR (s390_vec_srb_u16_u16,       s390_vsrlb,         0,                  0,                  BT_OV_UV8HI_UV8HI_UV8HI)
-OB_DEF_VAR (s390_vec_srb_u16_s16,       s390_vsrlb,         0,                  0,                  BT_OV_UV8HI_UV8HI_V8HI)
-OB_DEF_VAR (s390_vec_srb_s16_u16,       s390_vsrlb,         0,                  0,                  BT_OV_V8HI_V8HI_UV8HI)
-OB_DEF_VAR (s390_vec_srb_s16_s16,       s390_vsrlb,         0,                  0,                  BT_OV_V8HI_V8HI_V8HI)
-OB_DEF_VAR (s390_vec_srb_u32_u32,       s390_vsrlb,         0,                  0,                  BT_OV_UV4SI_UV4SI_UV4SI)
-OB_DEF_VAR (s390_vec_srb_u32_s32,       s390_vsrlb,         0,                  0,                  BT_OV_UV4SI_UV4SI_V4SI)
-OB_DEF_VAR (s390_vec_srb_s32_u32,       s390_vsrlb,         0,                  0,                  BT_OV_V4SI_V4SI_UV4SI)
-OB_DEF_VAR (s390_vec_srb_s32_s32,       s390_vsrlb,         0,                  0,                  BT_OV_V4SI_V4SI_V4SI)
-OB_DEF_VAR (s390_vec_srb_u64_u64,       s390_vsrlb,         0,                  0,                  BT_OV_UV2DI_UV2DI_UV2DI)
-OB_DEF_VAR (s390_vec_srb_u64_s64,       s390_vsrlb,         0,                  0,                  BT_OV_UV2DI_UV2DI_V2DI)
-OB_DEF_VAR (s390_vec_srb_s64_u64,       s390_vsrlb,         0,                  0,                  BT_OV_V2DI_V2DI_UV2DI)
-OB_DEF_VAR (s390_vec_srb_s64_s64,       s390_vsrlb,         0,                  0,                  BT_OV_V2DI_V2DI_V2DI)
-OB_DEF_VAR (s390_vec_srb_flt_u64,       s390_vsrlb,         B_VXE,              0,                  BT_OV_V4SF_V4SF_UV4SI)
-OB_DEF_VAR (s390_vec_srb_dbl_u64,       s390_vsrlb,         0,                  0,                  BT_OV_V2DF_V2DF_UV2DI)
-OB_DEF_VAR (s390_vec_srb_flt_s64,       s390_vsrlb,         B_VXE,              0,                  BT_OV_V4SF_V4SF_V4SI)
-OB_DEF_VAR (s390_vec_srb_dbl_s64,       s390_vsrlb,         0,                  0,                  BT_OV_V2DF_V2DF_V2DI)
+OB_DEF_VAR (s390_vec_srb_u16_u8,        s390_vsrlb,         0,                  0,                  BT_OV_UV8HI_UV8HI_UV16QI)
+OB_DEF_VAR (s390_vec_srb_s16_u8,        s390_vsrlb,         0,                  0,                  BT_OV_V8HI_V8HI_UV16QI)
+OB_DEF_VAR (s390_vec_srb_u32_u8,        s390_vsrlb,         0,                  0,                  BT_OV_UV4SI_UV4SI_UV16QI)
+OB_DEF_VAR (s390_vec_srb_s32_u8,        s390_vsrlb,         0,                  0,                  BT_OV_V4SI_V4SI_UV16QI)
+OB_DEF_VAR (s390_vec_srb_u64_u8,        s390_vsrlb,         0,                  0,                  BT_OV_UV2DI_UV2DI_UV16QI)
+OB_DEF_VAR (s390_vec_srb_s64_u8,        s390_vsrlb,         0,                  0,                  BT_OV_V2DI_V2DI_UV16QI)
+OB_DEF_VAR (s390_vec_srb_u128_u8,       s390_vsrlb,         0,                  0,                  BT_OV_UV1TI_UV1TI_UV16QI)
+OB_DEF_VAR (s390_vec_srb_s128_u8,       s390_vsrlb,         0,                  0,                  BT_OV_V1TI_V1TI_UV16QI)
+OB_DEF_VAR (s390_vec_srb_flt_u8,        s390_vsrlb,         B_VXE,              0,                  BT_OV_V4SF_V4SF_UV16QI)
+OB_DEF_VAR (s390_vec_srb_dbl_u8,        s390_vsrlb,         0,                  0,                  BT_OV_V2DF_V2DF_UV16QI)
 
 B_DEF      (s390_vsrlb,                 vec_srbv16qi,       0,                  B_VX,               0,                  BT_FN_UV16QI_UV16QI_UV16QI)
 
@@ -3193,6 +3245,8 @@ OB_DEF_VAR (s390_vec_sldb_s32,          s390_vsld,          0,
 OB_DEF_VAR (s390_vec_sldb_u32,          s390_vsld,          0,                  O3_U3,              BT_OV_UV4SI_UV4SI_UV4SI_UINT)
 OB_DEF_VAR (s390_vec_sldb_s64,          s390_vsld,          0,                  O3_U3,              BT_OV_V2DI_V2DI_V2DI_UINT)
 OB_DEF_VAR (s390_vec_sldb_u64,          s390_vsld,          0,                  O3_U3,              BT_OV_UV2DI_UV2DI_UV2DI_UINT)
+OB_DEF_VAR (s390_vec_sldb_s128,         s390_vsld,          0,                  O3_U3,              BT_OV_V1TI_V1TI_V1TI_UINT)
+OB_DEF_VAR (s390_vec_sldb_u128,         s390_vsld,          0,                  O3_U3,              BT_OV_UV1TI_UV1TI_UV1TI_UINT)
 OB_DEF_VAR (s390_vec_sldb_flt,          s390_vsld,          0,                  O3_U3,              BT_OV_V4SF_V4SF_V4SF_UINT)
 OB_DEF_VAR (s390_vec_sldb_dbl,          s390_vsld,          0,                  O3_U3,              BT_OV_V2DF_V2DF_V2DF_UINT)
 
@@ -3207,6 +3261,8 @@ OB_DEF_VAR (s390_vec_srdb_s32,          s390_vsrd,          0,
 OB_DEF_VAR (s390_vec_srdb_u32,          s390_vsrd,          0,                  O3_U3,              BT_OV_UV4SI_UV4SI_UV4SI_UINT)
 OB_DEF_VAR (s390_vec_srdb_s64,          s390_vsrd,          0,                  O3_U3,              BT_OV_V2DI_V2DI_V2DI_UINT)
 OB_DEF_VAR (s390_vec_srdb_u64,          s390_vsrd,          0,                  O3_U3,              BT_OV_UV2DI_UV2DI_UV2DI_UINT)
+OB_DEF_VAR (s390_vec_srdb_s128,         s390_vsrd,          0,                  O3_U3,              BT_OV_V1TI_V1TI_V1TI_UINT)
+OB_DEF_VAR (s390_vec_srdb_u128,         s390_vsrd,          0,                  O3_U3,              BT_OV_UV1TI_UV1TI_UV1TI_UINT)
 OB_DEF_VAR (s390_vec_srdb_flt,          s390_vsrd,          0,                  O3_U3,              BT_OV_V4SF_V4SF_V4SF_UINT)
 OB_DEF_VAR (s390_vec_srdb_dbl,          s390_vsrd,          0,                  O3_U3,              BT_OV_V2DF_V2DF_V2DF_UINT)
 

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 952c3afdec01cd030619a9d0ed549ca681df6145..7247e89807c07717b13537555afce021808858a0 100644 (file)
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -1469,10 +1469,41 @@
 
 ; Each vector element rotated by a scalar
 (define_expand "<vec_shifts_name><mode>3"
-  [(set (match_operand:VI 0 "register_operand" "")
-       (VEC_SHIFTS:VI (match_operand:VI 1 "register_operand" "")
-                      (match_operand:QI 2 "shift_count_operand" "")))]
-  "TARGET_VX")
+  [(set (match_operand:VIT 0 "register_operand" "")
+       (VEC_SHIFTS:VIT (match_operand:VIT 1 "register_operand" "")
+                       (match_operand:QI  2 "shift_count_operand" "")))]
+  "TARGET_VX && ((<MODE>mode != V1TImode && <MODE>mode != TImode) || <CODE> != ROTATE)"
+{
+  if (<MODE>mode == V1TImode || <MODE>mode == TImode)
+    {
+      rtx shift_count = gen_reg_rtx (V16QImode);
+      emit_insn (gen_vec_splatsv16qi (shift_count, operands[2]));
+
+      if (!CONST_INT_P (operands[2]) || UINTVAL (operands[2]) > 7)
+       switch (<CODE>)
+         {
+         case ASHIFT: emit_insn (gen_vec_slb (<MODE>mode, operands[0], operands[1], shift_count)); break;
+         case ASHIFTRT: emit_insn (gen_vec_srab (<MODE>mode, operands[0], operands[1], shift_count)); break;
+         case LSHIFTRT: emit_insn (gen_vec_srb (<MODE>mode, operands[0], operands[1], shift_count)); break;
+         default: gcc_unreachable ();
+         }
+      else
+       emit_move_insn (operands[0], operands[1]);
+
+      if (!CONST_INT_P (operands[2]) || (UINTVAL (operands[2]) & 7) != 0)
+       {
+         switch (<CODE>)
+           {
+           case ASHIFT: emit_insn (gen_vec_sll (<MODE>mode, V16QImode, operands[0], operands[0], shift_count)); break;
+           case ASHIFTRT: emit_insn (gen_vec_sral (<MODE>mode, V16QImode, operands[0], operands[0], shift_count)); break;
+           case LSHIFTRT: emit_insn (gen_vec_srl (<MODE>mode, V16QImode, operands[0], operands[0], shift_count)); break;
+           default: gcc_unreachable ();
+           }
+       }
+
+      DONE;
+    }
+})
 
 ; verllb, verllh, verllf, verllg
 ; veslb,  veslh,  veslf,  veslg
@@ -1540,8 +1571,8 @@
 
 ; Pattern used by e.g. popcount
 (define_insn "*vec_srb<mode>"
-  [(set (match_operand:V_128                0 "register_operand" "=v")
-       (unspec:V_128 [(match_operand:V_128 1 "register_operand"  "v")
+  [(set (match_operand:V_HW3                0 "register_operand" "=v")
+       (unspec:V_HW3 [(match_operand:V_HW3 1 "register_operand"  "v")
                       (match_operand:V16QI 2 "register_operand"  "v")]
                   UNSPEC_VEC_SRLB))]
   "TARGET_VX"
@@ -1552,8 +1583,8 @@
 ; Vector shift left by byte
 
 (define_insn "*vec_slb<mode>"
-  [(set (match_operand:V_128                0 "register_operand" "=v")
-       (unspec:V_128 [(match_operand:V_128 1 "register_operand"  "v")
+  [(set (match_operand:V_HW3                0 "register_operand" "=v")
+       (unspec:V_HW3 [(match_operand:V_HW3 1 "register_operand"  "v")
                    (match_operand:V16QI    2 "register_operand"  "v")]
                   UNSPEC_VEC_SLB))]
   "TARGET_VX"

diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md
index a25122db3b28fc5a402ae367de35f8828af23244..a7bb7ff92f5e71cb2d5dc23a32caf7cb485c12a4 100644 (file)
--- a/gcc/config/s390/vx-builtins.md
+++ b/gcc/config/s390/vx-builtins.md
@@ -1041,9 +1041,9 @@
 
 ; Vector shift left
 
-(define_insn "vec_sll<VI_HW:mode><VI_HW_QHS:mode>"
-  [(set (match_operand:VI_HW                    0 "register_operand" "=v")
-       (unspec:VI_HW [(match_operand:VI_HW     1 "register_operand"  "v")
+(define_insn "@vec_sll<V_HW3:mode><VI_HW_QHS:mode>"
+  [(set (match_operand:V_HW3                    0 "register_operand" "=v")
+       (unspec:V_HW3 [(match_operand:V_HW3     1 "register_operand"  "v")
                       (match_operand:VI_HW_QHS 2 "register_operand"  "v")]
                      UNSPEC_VEC_SLL))]
   "TARGET_VX"
@@ -1054,15 +1054,12 @@
 ; Vector shift left by byte
 
 ; Pattern definition in vector.md, see vec_vslb
-(define_expand "vec_slb<mode>"
-  [(set (match_operand:V_HW 0 "register_operand"                     "")
-       (unspec:V_HW [(match_operand:V_HW 1 "register_operand"       "")
-                     (match_operand:<TOINTVEC> 2 "register_operand" "")]
+(define_expand "@vec_slb<mode>"
+  [(set (match_operand:V_HW3 0 "register_operand"                     "")
+       (unspec:V_HW3 [(match_operand:V_HW3 1 "register_operand"       "")
+                     (match_operand:V16QI 2 "register_operand" "")]
                     UNSPEC_VEC_SLB))]
-  "TARGET_VX"
-{
-  PUT_MODE (operands[2], V16QImode);
-})
+  "TARGET_VX")
 
 ; Vector shift left double by byte
 
@@ -1113,9 +1110,9 @@
 
 ; Vector shift right arithmetic
 
-(define_insn "vec_sral<VI_HW:mode><VI_HW_QHS:mode>"
-  [(set (match_operand:VI_HW                    0 "register_operand" "=v")
-       (unspec:VI_HW [(match_operand:VI_HW     1 "register_operand"  "v")
+(define_insn "@vec_sral<V_HW3:mode><VI_HW_QHS:mode>"
+  [(set (match_operand:V_HW3                    0 "register_operand" "=v")
+       (unspec:V_HW3 [(match_operand:V_HW3     1 "register_operand"  "v")
                       (match_operand:VI_HW_QHS 2 "register_operand"  "v")]
                      UNSPEC_VEC_SRAL))]
   "TARGET_VX"
@@ -1125,10 +1122,10 @@
 
 ; Vector shift right arithmetic by byte
 
-(define_insn "vec_srab<mode>"
-  [(set (match_operand:V_HW 0 "register_operand"                    "=v")
-       (unspec:V_HW [(match_operand:V_HW 1 "register_operand"       "v")
-                     (match_operand:<TOINTVEC> 2 "register_operand" "v")]
+(define_insn "@vec_srab<mode>"
+  [(set (match_operand:V_HW3 0 "register_operand"               "=v")
+       (unspec:V_HW3 [(match_operand:V_HW3 1 "register_operand" "v")
+                      (match_operand:V16QI 2 "register_operand" "v")]
                     UNSPEC_VEC_SRAB))]
   "TARGET_VX"
   "vsrab\t%v0,%v1,%v2"
@@ -1137,9 +1134,9 @@
 
 ; Vector shift right logical
 
-(define_insn "vec_srl<VI_HW:mode><VI_HW_QHS:mode>"
-  [(set (match_operand:VI_HW                    0 "register_operand" "=v")
-       (unspec:VI_HW [(match_operand:VI_HW     1 "register_operand"  "v")
+(define_insn "@vec_srl<V_HW3:mode><VI_HW_QHS:mode>"
+  [(set (match_operand:V_HW3                    0 "register_operand" "=v")
+       (unspec:V_HW3 [(match_operand:V_HW3     1 "register_operand"  "v")
                       (match_operand:VI_HW_QHS 2 "register_operand"  "v")]
                      UNSPEC_VEC_SRL))]
   "TARGET_VX"
@@ -1150,15 +1147,12 @@
 ; Vector shift right logical by byte
 
 ; Pattern definition in vector.md, see vec_vsrb
-(define_expand "vec_srb<mode>"
-  [(set (match_operand:V_HW 0 "register_operand"                     "")
-       (unspec:V_HW [(match_operand:V_HW 1 "register_operand"       "")
-                     (match_operand:<TOINTVEC> 2 "register_operand" "")]
-                    UNSPEC_VEC_SRLB))]
-  "TARGET_VX"
-{
-  PUT_MODE (operands[2], V16QImode);
-})
+(define_expand "@vec_srb<mode>"
+  [(set (match_operand:V_HW3 0 "register_operand"                     "")
+       (unspec:V_HW3 [(match_operand:V_HW3 1 "register_operand"      "")
+                      (match_operand:V16QI 2 "register_operand" "")]
+                     UNSPEC_VEC_SRLB))]
+  "TARGET_VX")
 
 ; Vector subtract
 

diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-shift-10.c b/gcc/testsuite/gcc.target/s390/vector/vec-shift-10.c
new file mode 100644 (file)
index 0000000..7e4fcaa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/vec-shift-10.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -march=z13 -save-temps" } */
+/* { dg-require-effective-target int128 } */
+/* { dg-final { scan-assembler "\tvsra\t" } } */
+/* { dg-final { scan-assembler "\tvsrab\t" } } */
+
+#include <assert.h>
+
+typedef __attribute__ ((vector_size (16))) signed long long v2di;
+typedef __attribute__ ((vector_size (16))) signed __int128 v1ti;
+
+__attribute__ ((noipa)) v1ti
+dyn_shift (v1ti x, v1ti n)
+{
+  return x >> n;
+}
+
+int
+main (void)
+{
+  v2di x, y;
+
+  x = (v2di){ 0xcafed00ddeadbeef, 0xcafed00ddeadbeef };
+  y = (v2di){ 0xe57f6806ef56df77, 0xe57f6806ef56df77 };
+  x = (v2di) dyn_shift ((v1ti) x, (v1ti){1});
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  x = (v2di){ 0x4afed00dbeadbeee, 0xcafed00ddeadbeef };
+  y = (v2di){ 0x257f6806df56df77, 0x657f6806ef56df77 };
+  x = (v2di) dyn_shift ((v1ti) x, (v1ti){1});
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  x = (v2di){ 0xcafed00ddeadbeef, 0xcafed00ddeadbeef };
+  y = (v2di){ 0xffffcafed00ddead, 0xbeefcafed00ddead };
+  x = (v2di) dyn_shift ((v1ti) x, (v1ti){16});
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  x = (v2di){ 0x4afed00ddead3eef, 0xcafed00ddeadbeef };
+  y = (v2di){ 0x00004afed00ddead, 0x3eefcafed00ddead };
+  x = (v2di) dyn_shift ((v1ti) x, (v1ti){16});
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  x = (v2di){ 0xcafed00ddeadbeef, 0xcafed00ddeadbeef };
+  y = (v2di){ 0xfffffffffff2bfb4, 0x377ab6fbbf2bfb4 };
+  x = (v2di) dyn_shift ((v1ti) x, (v1ti){42});
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  x = (v2di){ 0x4afed00ddeadbeee, 0xcafed00ddeadbeef };
+  y = (v2di){ 0x000000000012bfb4, 0x0377ab6fbbb2bfb4 };
+  x = (v2di) dyn_shift ((v1ti) x, (v1ti){42});
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  return 0;
+}

diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-shift-11.c b/gcc/testsuite/gcc.target/s390/vector/vec-shift-11.c
new file mode 100644 (file)
index 0000000..e34a0e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/vec-shift-11.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -march=z13 -save-temps" } */
+/* { dg-require-effective-target int128 } */
+/* { dg-final { scan-assembler "\tvsrl\t" } } */
+/* { dg-final { scan-assembler "\tvsrlb\t" } } */
+
+#include <assert.h>
+
+typedef __attribute__ ((vector_size (16))) unsigned long long uv2di;
+typedef __attribute__ ((vector_size (16))) unsigned __int128 uv1ti;
+
+__attribute__ ((noipa)) uv1ti
+dyn_shift (uv1ti x, unsigned int n)
+{
+  return x >> n;
+}
+
+int
+main (void)
+{
+  uv2di x, y;
+
+  x = (uv2di){ 0xcafed00ddeadbeef, 0xcafed00ddeadbeef };
+  y = (uv2di){ 0x657f6806ef56df77, 0xe57f6806ef56df77 };
+  x = (uv2di) dyn_shift ((uv1ti) x, 1);
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  x = (uv2di){ 0xcafed00ddeadbeef, 0xcafed00ddeadbeef };
+  y = (uv2di){ 0x0000cafed00ddead, 0xbeefcafed00ddead };
+  x = (uv2di) dyn_shift ((uv1ti) x, 16);
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  x = (uv2di){ 0xcafed00ddeadbeef, 0xcafed00ddeadbeef };
+  y = (uv2di){ 0x000000000032bfb4, 0x0377ab6fbbf2bfb4 };
+  x = (uv2di) dyn_shift ((uv1ti) x, 42);
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  return 0;
+}

diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-shift-12.c b/gcc/testsuite/gcc.target/s390/vector/vec-shift-12.c
new file mode 100644 (file)
index 0000000..d01c29b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/vec-shift-12.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -march=z13 -save-temps" } */
+/* { dg-require-effective-target int128 } */
+/* { dg-final { scan-assembler "\tvsrl\t" } } */
+/* { dg-final { scan-assembler "\tvsrlb\t" } } */
+
+#include <assert.h>
+
+typedef __attribute__ ((vector_size (16))) unsigned long long uv2di;
+typedef __attribute__ ((vector_size (16))) unsigned __int128 uv1ti;
+
+__attribute__ ((noipa)) uv1ti
+dyn_shift (uv1ti x, uv1ti n)
+{
+  return x >> n;
+}
+
+int
+main (void)
+{
+  uv2di x, y;
+
+  x = (uv2di){ 0xcafed00ddeadbeef, 0xcafed00ddeadbeef };
+  y = (uv2di){ 0x657f6806ef56df77, 0xe57f6806ef56df77 };
+  x = (uv2di) dyn_shift ((uv1ti) x, (uv1ti){1});
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  x = (uv2di){ 0xcafed00ddeadbeef, 0xcafed00ddeadbeef };
+  y = (uv2di){ 0x0000cafed00ddead, 0xbeefcafed00ddead };
+  x = (uv2di) dyn_shift ((uv1ti) x, (uv1ti){16});
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  x = (uv2di){ 0xcafed00ddeadbeef, 0xcafed00ddeadbeef };
+  y = (uv2di){ 0x000000000032bfb4, 0x0377ab6fbbf2bfb4 };
+  x = (uv2di) dyn_shift ((uv1ti) x, (uv1ti){42});
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  return 0;
+}

diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-shift-3.c b/gcc/testsuite/gcc.target/s390/vector/vec-shift-3.c
new file mode 100644 (file)
index 0000000..c5b92fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/vec-shift-3.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -march=z13 -save-temps" } */
+/* { dg-require-effective-target int128 } */
+/* { dg-final { scan-assembler "\tvsra\t" } } */
+/* { dg-final { scan-assembler-not "\tvsrab\t" } } */
+
+#include <assert.h>
+
+typedef __attribute__ ((vector_size (16))) signed long long v2di;
+typedef __attribute__ ((vector_size (16))) signed __int128 v1ti;
+
+__attribute__ ((noipa)) v1ti
+const_shift (v1ti x)
+{
+  return x >> 1;
+}
+
+int
+main (void)
+{
+  v2di x, y;
+
+  x = (v2di){ 0xcafed00ddeadbeef, 0xcafed00ddeadbeef };
+  y = (v2di){ 0xe57f6806ef56df77, 0xe57f6806ef56df77 };
+  x = (v2di) const_shift ((v1ti) x);
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  x = (v2di){ 0x4afed00dbeadbeee, 0xcafed00ddeadbeef };
+  y = (v2di){ 0x257f6806df56df77, 0x657f6806ef56df77 };
+  x = (v2di) const_shift ((v1ti) x);
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  return 0;
+}

diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-shift-4.c b/gcc/testsuite/gcc.target/s390/vector/vec-shift-4.c
new file mode 100644 (file)
index 0000000..0759c01
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/vec-shift-4.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -march=z13 -save-temps" } */
+/* { dg-require-effective-target int128 } */
+/* { dg-final { scan-assembler "\tvsrl\t" } } */
+/* { dg-final { scan-assembler-not "\tvsrlb\t" } } */
+
+#include <assert.h>
+
+typedef __attribute__ ((vector_size (16))) unsigned long long uv2di;
+typedef __attribute__ ((vector_size (16))) unsigned __int128 uv1ti;
+
+__attribute__ ((noipa)) uv1ti
+const_shift (uv1ti x)
+{
+  return x >> 1;
+}
+
+int
+main (void)
+{
+  uv2di x, y;
+
+  x = (uv2di){ 0xcafed00ddeadbeef, 0xcafed00ddeadbeef };
+  y = (uv2di){ 0x657f6806ef56df77, 0xe57f6806ef56df77 };
+  x = (uv2di) const_shift ((uv1ti) x);
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  return 0;
+}

diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-shift-5.c b/gcc/testsuite/gcc.target/s390/vector/vec-shift-5.c
new file mode 100644 (file)
index 0000000..66cfb12
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/vec-shift-5.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -march=z13 -save-temps" } */
+/* { dg-require-effective-target int128 } */
+/* { dg-final { scan-assembler "\tvsrab\t" } } */
+/* { dg-final { scan-assembler-not "\tvsra\t" } } */
+
+#include <assert.h>
+
+typedef __attribute__ ((vector_size (16))) signed long long v2di;
+typedef __attribute__ ((vector_size (16))) signed __int128 v1ti;
+
+__attribute__ ((noipa)) v1ti
+const_shift (v1ti x)
+{
+  return x >> 16;
+}
+
+int
+main (void)
+{
+  v2di x, y;
+
+  x = (v2di){ 0xcafed00ddeadbeef, 0xcafed00ddeadbeef };
+  y = (v2di){ 0xffffcafed00ddead, 0xbeefcafed00ddead };
+  x = (v2di) const_shift ((v1ti) x);
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  x = (v2di){ 0x4afed00ddead3eef, 0xcafed00ddeadbeef };
+  y = (v2di){ 0x00004afed00ddead, 0x3eefcafed00ddead };
+  x = (v2di) const_shift ((v1ti) x);
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  return 0;
+}

diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-shift-6.c b/gcc/testsuite/gcc.target/s390/vector/vec-shift-6.c
new file mode 100644 (file)
index 0000000..b92141e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/vec-shift-6.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -march=z13 -save-temps" } */
+/* { dg-require-effective-target int128 } */
+/* { dg-final { scan-assembler "\tvsrlb\t" } } */
+/* { dg-final { scan-assembler-not "\tvsrl\t" } } */
+
+#include <assert.h>
+
+typedef __attribute__ ((vector_size (16))) unsigned long long uv2di;
+typedef __attribute__ ((vector_size (16))) unsigned __int128 uv1ti;
+
+__attribute__ ((noipa)) uv1ti
+const_shift (uv1ti x)
+{
+  return x >> 16;
+}
+
+int
+main (void)
+{
+  uv2di x, y;
+
+  x = (uv2di){ 0xcafed00ddeadbeef, 0xcafed00ddeadbeef };
+  y = (uv2di){ 0x0000cafed00ddead, 0xbeefcafed00ddead };
+  x = (uv2di) const_shift ((uv1ti) x);
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  return 0;
+}

diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-shift-7.c b/gcc/testsuite/gcc.target/s390/vector/vec-shift-7.c
new file mode 100644 (file)
index 0000000..c0277ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/vec-shift-7.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -march=z13 -save-temps" } */
+/* { dg-require-effective-target int128 } */
+/* { dg-final { scan-assembler "\tvsra\t" } } */
+/* { dg-final { scan-assembler "\tvsrab\t" } } */
+
+#include <assert.h>
+
+typedef __attribute__ ((vector_size (16))) signed long long v2di;
+typedef __attribute__ ((vector_size (16))) signed __int128 v1ti;
+
+__attribute__ ((noipa)) v1ti
+const_shift (v1ti x)
+{
+  return x >> 42;
+}
+
+int
+main (void)
+{
+  v2di x, y;
+
+  x = (v2di){ 0xcafed00ddeadbeef, 0xcafed00ddeadbeef };
+  y = (v2di){ 0xfffffffffff2bfb4, 0x377ab6fbbf2bfb4 };
+  x = (v2di) const_shift ((v1ti) x);
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  x = (v2di){ 0x4afed00ddeadbeee, 0xcafed00ddeadbeef };
+  y = (v2di){ 0x000000000012bfb4, 0x0377ab6fbbb2bfb4 };
+  x = (v2di) const_shift ((v1ti) x);
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  return 0;
+}

diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-shift-8.c b/gcc/testsuite/gcc.target/s390/vector/vec-shift-8.c
new file mode 100644 (file)
index 0000000..308aadd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/vec-shift-8.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -march=z13 -save-temps" } */
+/* { dg-require-effective-target int128 } */
+/* { dg-final { scan-assembler "\tvsrl\t" } } */
+/* { dg-final { scan-assembler "\tvsrlb\t" } } */
+
+#include <assert.h>
+
+typedef __attribute__ ((vector_size (16))) unsigned long long uv2di;
+typedef __attribute__ ((vector_size (16))) unsigned __int128 uv1ti;
+
+__attribute__ ((noipa)) uv1ti
+const_shift (uv1ti x)
+{
+  return x >> 42;
+}
+
+int
+main (void)
+{
+  uv2di x, y;
+
+  x = (uv2di){ 0xcafed00ddeadbeef, 0xcafed00ddeadbeef };
+  y = (uv2di){ 0x000000000032bfb4, 0x0377ab6fbbf2bfb4 };
+  x = (uv2di) const_shift ((uv1ti) x);
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  return 0;
+}

diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-shift-9.c b/gcc/testsuite/gcc.target/s390/vector/vec-shift-9.c
new file mode 100644 (file)
index 0000000..929fa0d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/vec-shift-9.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -march=z13 -save-temps" } */
+/* { dg-require-effective-target int128 } */
+/* { dg-final { scan-assembler "\tvsra\t" } } */
+/* { dg-final { scan-assembler "\tvsrab\t" } } */
+
+#include <assert.h>
+
+typedef __attribute__ ((vector_size (16))) signed long long v2di;
+typedef __attribute__ ((vector_size (16))) signed __int128 v1ti;
+
+__attribute__ ((noipa)) v1ti
+dyn_shift (v1ti x, unsigned int n)
+{
+  return x >> n;
+}
+
+int
+main (void)
+{
+  v2di x, y;
+
+  x = (v2di){ 0xcafed00ddeadbeef, 0xcafed00ddeadbeef };
+  y = (v2di){ 0xe57f6806ef56df77, 0xe57f6806ef56df77 };
+  x = (v2di) dyn_shift ((v1ti) x, 1);
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  x = (v2di){ 0x4afed00dbeadbeee, 0xcafed00ddeadbeef };
+  y = (v2di){ 0x257f6806df56df77, 0x657f6806ef56df77 };
+  x = (v2di) dyn_shift ((v1ti) x, 1);
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  x = (v2di){ 0xcafed00ddeadbeef, 0xcafed00ddeadbeef };
+  y = (v2di){ 0xffffcafed00ddead, 0xbeefcafed00ddead };
+  x = (v2di) dyn_shift ((v1ti) x, 16);
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  x = (v2di){ 0x4afed00ddead3eef, 0xcafed00ddeadbeef };
+  y = (v2di){ 0x00004afed00ddead, 0x3eefcafed00ddead };
+  x = (v2di) dyn_shift ((v1ti) x, 16);
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  x = (v2di){ 0xcafed00ddeadbeef, 0xcafed00ddeadbeef };
+  y = (v2di){ 0xfffffffffff2bfb4, 0x377ab6fbbf2bfb4 };
+  x = (v2di) dyn_shift ((v1ti) x, 42);
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  x = (v2di){ 0x4afed00ddeadbeee, 0xcafed00ddeadbeef };
+  y = (v2di){ 0x000000000012bfb4, 0x0377ab6fbbb2bfb4 };
+  x = (v2di) dyn_shift ((v1ti) x, 42);
+  assert (x[0] == y[0] && x[1] == y[1]);
+
+  return 0;
+}