+2016-10-10 Christophe Lyon <christophe.lyon@linaro.org>
+ Backport from mainline
+ 2016-09-28 Christophe Lyon <christophe.lyon@linaro.org>
+
+ PR ld/20608
+ * elf32-arm.c (arm_type_of_stub): Handle the case when the pre-PLT
+ Thumb-ARM stub is too far.
+
+2016-09-06 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
+
+ Backport from mainline
+ 2016-09-02 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
+
+ PR ld/20545
+ * elf32-avr.c (elf32_avr_relax_delete_bytes): Add parameter
+ delete_shrinks_insn. Modify computation of shrinked_insn_address.
+ Compute shrink_boundary and adjust addend only if
+ addend_within_shrink_boundary.
+ (elf32_avr_relax_section): Modify calls to
+ elf32_avr_relax_delete_bytes to pass extra parameter.
+
+2016-09-01 Alan Modra <amodra@gmail.com>
+
+ * elf64-ppc.c (synthetic_opd): New static var.
+ (compare_symbols): Don't treat symbols in .opd specially for ELFv2.
+ (ppc64_elf_get_synthetic_symtab): Likewise. Comment.
+
+2016-08-30 Alan Modra <amodra@gmail.com>
+
+ PR 20531
+ * elf32-ppc.c (_bfd_elf_ppc_set_arch): Add missing "break".
+
2016-08-19 Alan Modra <amodra@gmail.com>
PR 20472
/* Note when dealing with PLT entries: the main PLT stub is in
ARM mode, so if the branch is in Thumb mode, another
Thumb->ARM stub will be inserted later just before the ARM
- PLT stub. We don't take this extra distance into account
- here, because if a long branch stub is needed, we'll add a
- Thumb->Arm one and branch directly to the ARM PLT entry
- because it avoids spreading offset corrections in several
- places. */
+ PLT stub. If a long branch stub is needed, we'll add a
+ Thumb->Arm one and branch directly to the ARM PLT entry.
+ Here, we have to check if a pre-PLT Thumb->ARM stub
+ is needed and if it will be close enough. */
destination = (splt->output_section->vma
+ splt->output_offset
+ root_plt->offset);
st_type = STT_FUNC;
- branch_type = ST_BRANCH_TO_ARM;
+
+ /* Thumb branch/call to PLT: it can become a branch to ARM
+ or to Thumb. We must perform the same checks and
+ corrections as in elf32_arm_final_link_relocate. */
+ if ((r_type == R_ARM_THM_CALL)
+ || (r_type == R_ARM_THM_JUMP24))
+ {
+ if (globals->use_blx
+ && r_type == R_ARM_THM_CALL
+ && !thumb_only)
+ {
+ /* If the Thumb BLX instruction is available, convert
+ the BL to a BLX instruction to call the ARM-mode
+ PLT entry. */
+ branch_type = ST_BRANCH_TO_ARM;
+ }
+ else
+ {
+ if (!thumb_only)
+ /* Target the Thumb stub before the ARM PLT entry. */
+ destination -= PLT_THUMB_STUB_SIZE;
+ branch_type = ST_BRANCH_TO_THUMB;
+ }
+ }
+ else
+ {
+ branch_type = ST_BRANCH_TO_ARM;
+ }
}
}
/* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
|| (r_type == R_ARM_THM_JUMP19))
&& !use_plt))
{
+ /* If we need to insert a Thumb-Thumb long branch stub to a
+ PLT, use one that branches directly to the ARM PLT
+ stub. If we pretended we'd use the pre-PLT Thumb->ARM
+ stub, undo this now. */
+ if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only) {
+ branch_type = ST_BRANCH_TO_ARM;
+ branch_offset += PLT_THUMB_STUB_SIZE;
+ }
+
if (branch_type == ST_BRANCH_TO_THUMB)
{
/* Thumb to thumb. */
/* Delete some bytes from a section while changing the size of an instruction.
The parameter "addr" denotes the section-relative offset pointing just
behind the shrinked instruction. "addr+count" point at the first
- byte just behind the original unshrinked instruction. */
+ byte just behind the original unshrinked instruction. If delete_shrinks_insn
+ is FALSE, we are deleting redundant padding bytes from relax_info prop
+ record handling. In that case, addr is section-relative offset of start
+ of padding, and count is the number of padding bytes to delete. */
static bfd_boolean
elf32_avr_relax_delete_bytes (bfd *abfd,
asection *sec,
bfd_vma addr,
- int count)
+ int count,
+ bfd_boolean delete_shrinks_insn)
{
Elf_Internal_Shdr *symtab_hdr;
unsigned int sec_shndx;
struct avr_relax_info *relax_info;
struct avr_property_record *prop_record = NULL;
bfd_boolean did_shrink = FALSE;
+ bfd_boolean did_pad = FALSE;
symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
to remember we didn't delete anything i.e. don't set did_shrink,
so that we don't corrupt reloc offsets or symbol values.*/
memset (contents + toaddr - count, fill, count);
+ did_pad = TRUE;
/* Adjust the TOADDR to avoid moving symbols located at the address
of the property record, which has not moved. */
continue;
shrinked_insn_address = (sec->output_section->vma
- + sec->output_offset + addr - count);
+ + sec->output_offset + addr);
+ if (delete_shrinks_insn)
+ shrinked_insn_address -= count;
irel = elf_section_data (isec)->relocs;
/* PR 12161: Read in the relocs for this section if necessary. */
a symbol or section associated with it. */
if (sym_sec == sec)
{
+ /* If there is an alignment boundary, we only need to
+ adjust addends that end up below the boundary. */
+ bfd_vma shrink_boundary = (reloc_toaddr
+ + sec->output_section->vma
+ + sec->output_offset);
+ bfd_boolean addend_within_shrink_boundary = FALSE;
+
symval += sym_sec->output_section->vma
+ sym_sec->output_offset;
(unsigned int) (symval + irel->r_addend),
(unsigned int) shrinked_insn_address);
+ /* If we padded bytes, then the boundary didn't change,
+ so there's no need to adjust addends pointing at the boundary.
+ If we didn't pad, then we actually shrank the boundary, so
+ addends pointing at the boundary need to be adjusted too. */
+ addend_within_shrink_boundary = did_pad
+ ? ((symval + irel->r_addend) < shrink_boundary)
+ : ((symval + irel->r_addend) <= shrink_boundary);
+
if (symval <= shrinked_insn_address
- && (symval + irel->r_addend) > shrinked_insn_address)
+ && (symval + irel->r_addend) > shrinked_insn_address
+ && addend_within_shrink_boundary)
{
if (elf32_avr_is_diff_reloc (irel))
{
{
/* Delete two bytes of data. */
if (!elf32_avr_relax_delete_bytes (abfd, sec,
- irel->r_offset + 2, 2))
+ irel->r_offset + 2, 2,
+ TRUE))
goto error_return;
/* That will change things, so, we should relax again.
/* Delete two bytes of data. */
if (!elf32_avr_relax_delete_bytes (abfd, sec,
- irel->r_offset + insn_size, 2))
+ irel->r_offset + insn_size, 2,
+ TRUE))
goto error_return;
/* That will change things, so, we should relax
record->offset -= count;
elf32_avr_relax_delete_bytes (abfd, sec,
addr - count,
- count);
+ count, FALSE);
*again = TRUE;
}
}
case PPC_APUINFO_BRLOCK:
if (mach != bfd_mach_ppc_vle)
mach = bfd_mach_ppc_e500;
+ break;
case PPC_APUINFO_VLE:
mach = bfd_mach_ppc_vle;
\f
/* Parameters for the qsort hook. */
static bfd_boolean synthetic_relocatable;
+static asection *synthetic_opd;
/* qsort comparison function for ppc64_elf_get_synthetic_symtab. */
return 1;
/* then .opd symbols. */
- if (strcmp (a->section->name, ".opd") == 0
- && strcmp (b->section->name, ".opd") != 0)
- return -1;
- if (strcmp (a->section->name, ".opd") != 0
- && strcmp (b->section->name, ".opd") == 0)
- return 1;
+ if (synthetic_opd != NULL)
+ {
+ if (strcmp (a->section->name, ".opd") == 0
+ && strcmp (b->section->name, ".opd") != 0)
+ return -1;
+ if (strcmp (a->section->name, ".opd") != 0
+ && strcmp (b->section->name, ".opd") == 0)
+ return 1;
+ }
/* then other code symbols. */
if ((a->section->flags & (SEC_CODE | SEC_ALLOC | SEC_THREAD_LOCAL))
memcpy (syms, static_syms, (symcount + 1) * sizeof (*syms));
synthetic_relocatable = relocatable;
+ synthetic_opd = opd;
qsort (syms, symcount, sizeof (*syms), compare_symbols);
if (!relocatable && symcount > 1)
}
i = 0;
- if (strcmp (syms[i]->section->name, ".opd") == 0)
+ /* Note that here and in compare_symbols we can't compare opd and
+ sym->section directly. With separate debug info files, the
+ symbols will be extracted from the debug file while abfd passed
+ to this function is the real binary. */
+ if (opd != NULL && strcmp (syms[i]->section->name, ".opd") == 0)
++i;
codesecsym = i;
break;
secsymend = i;
- for (; i < symcount; ++i)
- if (strcmp (syms[i]->section->name, ".opd") != 0)
- break;
+ if (opd != NULL)
+ for (; i < symcount; ++i)
+ if (strcmp (syms[i]->section->name, ".opd") != 0)
+ break;
opdsymend = i;
for (; i < symcount; ++i)
-#define BFD_VERSION_DATE 20160829
+#define BFD_VERSION_DATE 20161019
#define BFD_VERSION @bfd_version@
#define BFD_VERSION_STRING @bfd_version_package@ @bfd_version_string@
#define REPORT_BUGS_TO @report_bugs_to@
+2016-09-16 Peter Bergner <bergner@vnet.ibm.com>
+
+ Apply from master.
+ 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
+
+ * testsuite/gas/ppc/power9.d <slbiag, cpabort> New tests.
+ <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
+ xor3, cp_abort, copy_first, paste, paste_last, sync>: Remove tests.
+ <copy, paste.>: Update tests.
+ * testsuite/gas/ppc/power9.s: Likewise.
+
2016-08-25 Thomas Preud'homme <thomas.preudhomme@arm.com>
Backport from mainline
.*: (7f a8 49 80|80 49 a8 7f) cmprb cr7,1,r8,r9
.*: (7d e0 01 00|00 01 e0 7d) setb r15,cr0
.*: (7d fc 01 00|00 01 fc 7d) setb r15,cr7
-.*: (7e 00 01 01|01 01 00 7e) setbool r16,lt
-.*: (7e 01 01 01|01 01 01 7e) setbool r16,gt
-.*: (7e 02 01 01|01 01 02 7e) setbool r16,eq
-.*: (7e 03 01 01|01 01 03 7e) setbool r16,so
-.*: (7e 1c 01 01|01 01 1c 7e) setbool r16,4\*cr7\+lt
-.*: (7e 1d 01 01|01 01 1d 7e) setbool r16,4\*cr7\+gt
-.*: (7e 1e 01 01|01 01 1e 7e) setbool r16,4\*cr7\+eq
-.*: (7e 1f 01 01|01 01 1f 7e) setbool r16,4\*cr7\+so
.*: (7f 40 52 1a|1a 52 40 7f) lxvl vs26,0,r10
.*: (7f 14 52 1b|1b 52 14 7f) lxvl vs56,r20,r10
.*: (7f 60 5b 1a|1a 5b 60 7f) stxvl vs27,0,r11
.*: (4c e0 80 04|04 80 e0 4c) addpcis r7,-32768
.*: (4c e0 80 04|04 80 e0 4c) addpcis r7,-32768
.*: (7c 00 02 a4|a4 02 00 7c) slbsync
+.*: (7d 40 06 a4|a4 06 40 7d) slbiag r10
.*: (7d 40 5b a4|a4 5b 40 7d) slbieg r10,r11
.*: (7c 60 27 26|26 27 60 7c) slbmfee r3,r4
.*: (7c 60 27 26|26 27 60 7c) slbmfee r3,r4
.*: (7c 00 1a 24|24 1a 00 7c) tlbiel r3
.*: (7c 00 1a 24|24 1a 00 7c) tlbiel r3
.*: (7c 8f 1a 24|24 1a 8f 7c) tlbiel r3,r4,3,1,1
-.*: (7c 0c 6e 0c|0c 6e 0c 7c) copy r12,r13
-.*: (7c 2c 6e 0c|0c 6e 2c 7c) copy_first r12,r13
-.*: (7c 2c 6e 0c|0c 6e 2c 7c) copy_first r12,r13
-.*: (7c 0a 5f 0c|0c 5f 0a 7c) paste r10,r11
-.*: (7c 0a 5f 0c|0c 5f 0a 7c) paste r10,r11
-.*: (7c 2a 5f 0d|0d 5f 2a 7c) paste_last r10,r11
-.*: (7c 2a 5f 0d|0d 5f 2a 7c) paste_last r10,r11
-.*: (7c 00 06 8c|8c 06 00 7c) cp_abort
+.*: (7c 2c 6e 0c|0c 6e 2c 7c) copy r12,r13
+.*: (7c 2a 5f 0d|0d 5f 2a 7c) paste\. r10,r11
+.*: (7c 00 06 8c|8c 06 00 7c) cpabort
.*: (7c 00 04 ac|ac 04 00 7c) hwsync
.*: (7c 00 04 ac|ac 04 00 7c) hwsync
.*: (7c 00 04 ac|ac 04 00 7c) hwsync
.*: (7c 20 04 ac|ac 04 20 7c) lwsync
.*: (7c 40 04 ac|ac 04 40 7c) ptesync
.*: (7c 40 04 ac|ac 04 40 7c) ptesync
-.*: (7c 07 04 ac|ac 04 07 7c) sync 0,7
-.*: (7c 28 04 ac|ac 04 28 7c) sync 1,8
.*: (7e 80 04 cc|cc 04 80 7e) ldat r20,0,0
.*: (7e 8a e4 cc|cc e4 8a 7e) ldat r20,r10,28
.*: (7e a0 04 8c|8c 04 a0 7e) lwat r21,0,0
.*: (7c 00 f6 e4|e4 f6 00 7c) rmieg r30
.*: (7d 40 7a 6a|6a 7a 40 7d) ldmx r10,0,r15
.*: (7d 43 7a 6a|6a 7a 43 7d) ldmx r10,r3,r15
-.*: (7d 60 83 6a|6a 83 60 7d) lwzmx r11,0,r16
-.*: (7d 63 83 6a|6a 83 63 7d) lwzmx r11,r3,r16
.*: (4c 00 02 e4|e4 02 00 4c) stop
.*: (7c 00 00 3c|3c 00 00 7c) wait
.*: (7c 00 00 3c|3c 00 00 7c) wait
.*: (7d 6c 69 54|54 69 6c 7d) addex r11,r12,r13,0
.*: (7d 6c 6b 54|54 6b 6c 7d) addex r11,r12,r13,1
.*: (7d 6c 6d 54|54 6d 6c 7d) addex r11,r12,r13,2
-.*: (7e b6 b9 55|55 b9 b6 7e) addex\. r21,r22,r23,0
-.*: (7e b6 bb 55|55 bb b6 7e) addex\. r21,r22,r23,1
-.*: (7e b6 bd 55|55 bd b6 7e) addex\. r21,r22,r23,2
.*: (ff 20 04 8e|8e 04 20 ff) mffs f25
.*: (ff 20 04 8f|8f 04 20 ff) mffs\. f25
.*: (ff 41 04 8e|8e 04 41 ff) mffsce f26
.*: (ff d7 04 8e|8e 04 d7 ff) mffscrni f30,0
.*: (ff d7 1c 8e|8e 1c d7 ff) mffscrni f30,3
.*: (ff f8 04 8e|8e 04 f8 ff) mffsl f31
-.*: (7e 8a 01 76|76 01 8a 7e) brd r10,r20
-.*: (7e ab 01 b6|b6 01 ab 7e) brh r11,r21
-.*: (7e cc 01 36|36 01 cc 7e) brw r12,r22
-.*: (11 6a 63 77|77 63 6a 11) nandxor r10,r11,r12,r13
-.*: (12 b4 b5 f6|f6 b5 b4 12) xor3 r20,r21,r22,r23
-.*: (11 6a 60 34|34 60 6a 11) rldixor r10,r11,0,r12
-.*: (11 6a 66 f4|f4 66 6a 11) rldixor r10,r11,27,r12
-.*: (11 6a 67 f5|f5 67 6a 11) rldixor r10,r11,63,r12
#pass
cmprb 7,1,8,9
setb 15,0
setb 15,7
- setbool 16,0
- setbool 16,1
- setbool 16,2
- setbool 16,3
- setbool 16,28
- setbool 16,29
- setbool 16,30
- setbool 16,31
lxvl 26,0,10
lxvl 56,20,10
stxvl 27,0,11
addpcis 7,-0x8000
subpcis 7,0x8000
slbsync
+ slbiag 10
slbieg 10,11
slbmfee 3,4
slbmfee 3,4,0
tlbiel 3
tlbiel 3,0,0,0,0
tlbiel 3,4,3,1,1
- copy 12,13,0
- copy_first 12,13
- copy 12,13,1
- paste 10,11,0
- paste 10,11
- paste. 10,11,1
- paste_last 10,11
- cp_abort
+ copy 12,13
+ paste. 10,11
+ cpabort
hwsync
sync
- sync 0,0x0
+ sync 0
lwsync
- sync 1,0x0
+ sync 1
ptesync
- sync 2,0x0
- sync 0,0x7
- sync 1,0x8
+ sync 2
ldat 20,0,0x0
ldat 20,10,0x1c
lwat 21,0,0x0
rmieg 30
ldmx 10,0,15
ldmx 10,3,15
- lwzmx 11,0,16
- lwzmx 11,3,16
stop
wait
wait 0
addex 11,12,13,0
addex 11,12,13,1
addex 11,12,13,2
- addex. 21,22,23,0
- addex. 21,22,23,1
- addex. 21,22,23,2
mffs 25
mffs. 25
mffsce 26
mffscrni 30,0
mffscrni 30,3
mffsl 31
- brd 10,20
- brh 11,21
- brw 12,22
- nandxor 10,11,12,13
- xor3 20,21,22,23
- rldixor 10,11,0,12
- rldixor 10,11,27,12
- rldixor 10,11,63,12
+2016-09-26 Cary Coutant <ccoutant@gmail.com>
+
+ PR gold/20238
+ * symtab.cc (Symbol_table::define_default_version): Check that
+ unversioned symbol is defined.
+
2016-08-23 Roland McGrath <roland@hack.frob.com>
* options.h (General_options): Grok -z stack-size.
;
else if (pdef->second->is_from_dynobj()
&& sym->is_from_dynobj()
+ && pdef->second->is_defined()
&& pdef->second->object() != sym->object())
;
else
+2016-10-14 Alan Modra <amodra@gmail.com>
+
+ * scripttempl/DWARF.sc: Add .debug_addr.
+
+2016-10-10 Christophe Lyon <christophe.lyon@linaro.org>
+
+ Backport from mainline
+ 2016-09-28 Christophe Lyon <christophe.lyon@linaro.org>
+
+ PR ld/20608
+ * testsuite/ld-arm/arm-elf.exp: Handle new testcase.
+ * testsuite/ld-arm/farcall-mixed-app2.d: New file.
+ * testsuite/ld-arm/farcall-mixed-app2.r: Likewise.
+ * testsuite/ld-arm/farcall-mixed-app2.s: Likewise.
+ * testsuite/ld-arm/farcall-mixed-app2.sym: Likewise.
+
+2016-09-06 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
+
+ Backport from mainline
+ 2016-09-02 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
+
+ PR ld/20545
+ * testsuite/ld-avr/avr-prop-7.d: New test.
+ * testsuite/ld-avr/avr-prop-7.s: New test.
+ * testsuite/ld-avr/avr-prop-8.d: New test.
+ * testsuite/ld-avr/avr-prop-8.s: New test.
+
2016-08-09 Roland McGrath <roland@hack.frob.com>
* emulparams/armelf.sh (GENERATE_PIE_SCRIPT): Set to yes.
/* DWARF Extension. */
.debug_macro 0 : { *(.debug_macro) }
+ .debug_addr 0 : { *(.debug_addr) }
EOF
{readelf -Ds farcall-mixed-app.sym}}
"farcall-mixed-app-v5"}
+ {"Mixed ARM/Thumb2 dynamic application with farcalls" "tmpdir/mixed-lib.so -T arm-dyn.ld --section-start .mid_thumb=0x10081c0 --section-start .far_arm=0x2100000 --section-start .far_thumb=0x2200000" "" ""
+ {farcall-mixed-app2.s}
+ {{objdump -fdw farcall-mixed-app2.d} {objdump -Rw farcall-mixed-app2.r}
+ {readelf -Ds farcall-mixed-app2.sym}}
+ "farcall-mixed-app2"}
+
{"Mixed ARM/Thumb shared library with long branches (v4t)" "-shared -T arm-lib.ld" "" "-march=armv4t"
{farcall-mixed-lib1.s farcall-mixed-lib2.s}
{{objdump -fdw farcall-mixed-lib-v4t.d}}
--- /dev/null
+
+tmpdir/farcall-mixed-app2: file format elf32-(little|big)arm
+architecture: arm.*, flags 0x00000112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address 0x.*
+
+Disassembly of section .plt:
+
+.* <lib_func2@plt-0x14>:
+ .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+ .*: e59fe004 ldr lr, \[pc, #4\] ; .* <lib_func2@plt-0x4>
+ .*: e08fe00e add lr, pc, lr
+ .*: e5bef008 ldr pc, \[lr, #8\]!
+ .*: .*
+.* <lib_func2@plt>:
+ .*: 4778 bx pc
+ .*: 46c0 nop ; \(mov r8, r8\)
+ .*: e28fc6.* add ip, pc, #.*
+ .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e5bcf.* ldr pc, \[ip, #.*\]!.*
+.* <lib_func1@plt>:
+ .*: e28fc6.* add ip, pc, #.*
+ .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e5bcf.* ldr pc, \[ip, #.*\]!.*
+
+Disassembly of section .text:
+
+.* <_start>:
+ .*: e1a0c00d mov ip, sp
+ .*: e92dd800 push {fp, ip, lr, pc}
+ .*: eb000008 bl .* <__app_func_veneer>
+ .*: ebfffff6 bl .* <lib_func1@plt>
+ .*: ebfffff2 bl .* <lib_func2@plt\+0x4>
+ .*: e89d6800 ldm sp, {fp, sp, lr}
+ .*: e12fff1e bx lr
+ .*: e1a00000 nop ; \(mov r0, r0\)
+
+.* <app_tfunc_close>:
+ .*: b500 push {lr}
+ .*: f7ff efde blx 81e0 <lib_func2@plt\+0x4>
+ .*: bd00 pop {pc}
+ .*: 4770 bx lr
+ .*: 46c0 nop ; \(mov r8, r8\)
+#...
+
+.* <__app_func_veneer>:
+ .*: e51ff004 ldr pc, \[pc, #-4\] ; 8234 <__app_func_veneer\+0x4>
+ .*: 02100000 .word 0x02100000
+
+Disassembly of section .mid_thumb:
+
+.* <mid_tfunc>:
+#...
+ .*: f400 9000 b.w .* <lib_func2@plt>
+ .*: f000 b800 b.w .* <__lib_func2_from_thumb>
+
+.* <__lib_func2_from_thumb>:
+ .*: 4778 bx pc
+ .*: 46c0 nop ; \(mov r8, r8\)
+ .*: e51ff004 ldr pc, \[pc, #-4\] ; 10081e8 <__lib_func2_from_thumb\+0x8>
+ .*: 000081e0 .word 0x000081e0
+ .*: 00000000 .word 0x00000000
+
+Disassembly of section .far_arm:
+
+.* <app_func>:
+ .*: e1a0c00d mov ip, sp
+ .*: e92dd800 push {fp, ip, lr, pc}
+ .*: eb000006 bl .* <__lib_func1_veneer>
+ .*: eb000007 bl .* <__lib_func2_veneer>
+ .*: e89d6800 ldm sp, {fp, sp, lr}
+ .*: e12fff1e bx lr
+ .*: e1a00000 nop ; \(mov r0, r0\)
+ .*: e1a00000 nop ; \(mov r0, r0\)
+
+.* <app_func2>:
+ .*: e12fff1e bx lr
+#...
+
+.* <__lib_func1_veneer>:
+ .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__lib_func1_veneer\+0x4>
+ .*: 000081ec .word 0x000081ec
+.* <__lib_func2_veneer>:
+ .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__lib_func2_veneer\+0x4>
+ .*: 000081e0 .word 0x000081e0
+
+Disassembly of section .far_thumb:
+
+.* <app_tfunc>:
+ .*: b500 push {lr}
+ .*: f000 e806 blx .* <__lib_func2_from_thumb>
+ .*: bd00 pop {pc}
+ .*: 4770 bx lr
+ .*: 46c0 nop ; \(mov r8, r8\)
+#...
+
+.* <__lib_func2_from_thumb>:
+ .*: e51ff004 ldr pc, \[pc, #-4\] ; 2200014 <__lib_func2_from_thumb\+0x4>
+ .*: 000081e0 .word 0x000081e0
--- /dev/null
+
+tmpdir/farcall-mixed-app.*: file format elf32-(little|big)arm
+
+DYNAMIC RELOCATION RECORDS
+OFFSET TYPE VALUE
+.* R_ARM_COPY data_obj
+.* R_ARM_JUMP_SLOT lib_func2
+.* R_ARM_JUMP_SLOT lib_func1
+
+
--- /dev/null
+ .text
+ .p2align 4
+ .globl _start
+_start:
+ mov ip, sp
+ stmdb sp!, {r11, ip, lr, pc}
+ bl app_func
+ bl lib_func1
+ bl lib_func2
+ ldmia sp, {r11, sp, lr}
+ bx lr
+
+ .p2align 4
+ .globl app_tfunc_close
+ .type app_tfunc_close,%function
+ .thumb_func
+ .code 16
+app_tfunc_close:
+ push {lr}
+ bl lib_func2
+ pop {pc}
+ bx lr
+
+@ We will place the section .mid_thumb at 0xFFFEF8.
+@ Just far enough for XXXX
+ .section .mid_thumb, "xa"
+
+ .p2align 4
+ .globl mid_tfunc
+ .type mid_tfunc,%function
+ .thumb_func
+ .code 16
+mid_tfunc:
+ .syntax unified
+ .space 24
+ b.w lib_func2
+ b.w lib_func2
+
+@ We will place the section .far_arm at 0x2100000.
+ .section .far_arm, "xa"
+
+ .arm
+ .p2align 4
+ .globl app_func
+ .type app_func,%function
+app_func:
+ mov ip, sp
+ stmdb sp!, {r11, ip, lr, pc}
+ bl lib_func1
+ bl lib_func2
+ ldmia sp, {r11, sp, lr}
+ bx lr
+
+ .arm
+ .p2align 4
+ .globl app_func2
+ .type app_func2,%function
+app_func2:
+ bx lr
+
+@ We will place the section .far_thumb at 0x2200000.
+ .section .far_thumb, "xa"
+
+ .p2align 4
+ .globl app_tfunc
+ .type app_tfunc,%function
+ .thumb_func
+ .code 16
+app_tfunc:
+ push {lr}
+ bl lib_func2
+ pop {pc}
+ bx lr
+
+ .data
+ .long data_obj
--- /dev/null
+
+Symbol table for image:
+ +Num +Buc: +Value +Size +Type +Bind +Vis +Ndx +Name
+ +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +11 _edata
+ +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +12 __bss_start__
+ +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +12 _end
+ +.. +..: ........ +4 +OBJECT +GLOBAL +DEFAULT +12 data_obj
+ +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +12 __bss_end__
+ +.. +..: 0*[^0]*.* +0 +FUNC +GLOBAL +DEFAULT +UND lib_func1
+ +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +11 __data_start
+ +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +12 __end__
+ +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +12 __bss_start
+ +.. +..: .......0 +0 +FUNC +GLOBAL +DEFAULT +15 app_func2
+ +.. +..: 0*[^0]*.* +0 +FUNC +GLOBAL +DEFAULT +UND lib_func2
+ +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +12 _bss_end__
--- /dev/null
+#name: AVR .avr.prop, AVR_7_PCREL after align
+#as: -mavrxmega2 -mlink-relax
+#ld: -mavrxmega2 --relax
+#source: avr-prop-7.s
+#objdump: -S
+#target: avr-*-*
+
+#...
+00000000 <__ctors_end>:
+ 0: 04 d0 rcall .+8 ; 0xa <foo>
+ 2: 00 00 nop
+ 4: 00 00 nop
+ 6: 86 e0 ldi r24, 0x06 ; 6
+ 8: f0 f7 brcc .-4 ; 0x6 <__ctors_end\+0x6>
+#...
--- /dev/null
+ call foo
+ nop
+ .p2align 1
+ nop
+.L618:
+ ldi r24,lo8(6)
+ brsh .L618
+foo: nop
--- /dev/null
+#name: AVR .avr.prop, AVR_7_PCREL just before align
+#as: -mavrxmega2 -mlink-relax
+#ld: -mavrxmega2 --relax
+#source: avr-prop-8.s
+#objdump: -S
+#target: avr-*-*
+
+#...
+00000000 <__ctors_end>:
+ 0: ff cf rjmp .-2 ; 0x0 <__ctors_end>
+ 2: fe df rcall .-4 ; 0x0 <__ctors_end>
+ 4: f8 f7 brcc .-2 ; 0x4 <__ctors_end\+0x4>
+#...
--- /dev/null
+foo:
+ jmp foo
+ call foo
+.L1:
+ brsh .L1
+.p2align 1
+ nop
+2016-09-16 Peter Bergner <bergner@vnet.ibm.com>
+
+ Apply from master.
+ 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
+ <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
+ xor3>: Delete mnemonics.
+ <cp_abort>: Rename mnemonic from ...
+ <cpabort>: ...to this.
+ <setb>: Change to a X form instruction.
+ <sync>: Change to 1 operand form.
+ <copy>: Delete mnemonic.
+ <copy_first>: Rename mnemonic from ...
+ <copy>: ...to this.
+ <paste, paste.>: Delete mnemonics.
+ <paste_last>: Rename mnemonic from ...
+ <paste.>: ...to this.
+
2016-08-03 Tristan Gingold <gingold@adacore.com>
* configure: Regenerate.
{"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
-{"rldixor", VXASH(4,26), VXASH_MASK, POWER9, 0, {RA, RS, SH6, RB}},
{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
{"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
-{"xor3", VXA(4, 54), VXA_MASK, POWER9, 0, {RA, RS, RB, RC}},
-{"nandxor", VXA(4, 55), VXA_MASK, POWER9, 0, {RA, RS, RB, RC}},
{"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
{"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
-{"setb", VX(31,256), VXVB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
-{"setbool", VX(31,257), VXVB_MASK, POWER9, 0, {RT, BA}},
+{"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}},
{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}},
-{"brw", X(31,155), XRB_MASK, POWER9, 0, {RA, RS}},
-
{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
{"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
-{"addex.", ZRC(31,170,1), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
{"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}},
{"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
{"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}},
-{"brd", X(31,187), XRB_MASK, POWER9, 0, {RA, RS}},
-
{"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}},
{"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},
{"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
{"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
-{"brh", X(31,219), XRB_MASK, POWER9, 0, {RA, RS}},
-
{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
{"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}},
{"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
-{"lwzmx", X(31,437), X_MASK, POWER9, 0, {RT, RA0, RB}},
-
{"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
{"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
{"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},
{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}},
-{"sync", X(31,598), XSYNCLE_MASK, POWER9|E6500, 0, {LS, ESYNC}},
-{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476|POWER9, {LS}},
+{"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}},
+{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}},
{"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}},
{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
{"lwsync", X(31,598), 0xffffffff, E500, 0, {0}},
{"lvsm", X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
-{"copy_first", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},
-{"copy", X(31,774), XLRT_MASK, POWER9, 0, {RA0, RB, L}},
+{"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},
{"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
{"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},
{"lvtlxl", X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
-{"cp_abort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}},
+{"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}},
{"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
{"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
{"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}},
+{"slbiag", X(31,850), XRARB_MASK, POWER9, 0, {RS}},
{"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
{"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}},
{"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}},
{"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}},
-{"paste", XRC(31,902,0), XLRT_MASK, POWER9, 0, {RA0, RB, L0}},
-{"paste_last", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}},
-{"paste.", XRC(31,902,1), XLRT_MASK, POWER9, 0, {RA0, RB, L1}},
+{"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}},
{"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},
{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
projects / thirdparty / binutils-gdb.git / commitdiff
