-j$(sysctl -n hw.logicalcpu)
displayName: 'Perform tools-only build'
+ - job: check_for_migrated_symbols_in_board_header
+ displayName: 'Check for migrated symbols in board header'
+ pool:
+ vmImage: $(ubuntu_vm)
+ container:
+ image: $(ci_runner_image)
+ options: $(container_option)
+ steps:
+ - script: |
+ KSYMLST=`mktemp`
+ KUSEDLST=`mktemp`
+ cat `find . -name "Kconfig*"` | \
+ sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
+ -e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
+ | sort -u > $KSYMLST
+ for CFG in `find include/configs -name "*.h"`; do
+ grep '#define[[:blank:]]CONFIG_' $CFG | \
+ sed -n 's/#define.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p' | \
+ sort -u > ${KUSEDLST} || true
+ NUM=`comm -12 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} | \
+ cut -d , -f 3`
+ if [[ $NUM -ne 0 ]]; then
+ echo "Unmigrated symbols found in $CFG"
+ exit 1
+ fi
+ done
+
- job: cppcheck
displayName: 'Static code analysis with cppcheck'
pool:
exit $ret;
fi;
+check for migrated symbols in board header:
+ stage: testsuites
+ script:
+ - KSYMLST=`mktemp`;
+ KUSEDLST=`mktemp`;
+ cat `find . -name "Kconfig*"` |
+ sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p'
+ -e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p'
+ | sort -u > $KSYMLST;
+ for CFG in `find include/configs -name "*.h"`; do
+ grep '#define[[:blank:]]CONFIG_' $CFG |
+ sed -n 's/#define.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p' |
+ sort -u > ${KUSEDLST} || true;
+ NUM=`comm -12 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} |
+ cut -d , -f 3`;
+ if [[ $NUM -ne 0 ]]; then
+ echo "Unmigrated symbols found in $CFG";
+ exit 1;
+ fi;
+ done
+
# QA jobs for code analytics
# static code analysis with cppcheck (we can add --enable=all later)
cppcheck:
boards with QUICC Engines require OF_QE to set UCC MAC
addresses
- CONFIG_OF_BOARD_SETUP
-
- Board code has addition modification that it wants to make
- to the flat device tree before handing it off to the kernel
-
CONFIG_OF_SYSTEM_SETUP
Other code has addition modification that it wants to make
Note: If a "bootargs" environment is defined, it will override
the defaults discussed just above.
-- Cache Configuration:
- CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot
-
- Cache Configuration for ARM:
CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache
controller
example "env grep" and "setexpr".
- Watchdog:
- CONFIG_WATCHDOG
- If this variable is defined, it enables watchdog
- support for the SoC. There must be support in the SoC
- specific code for a watchdog. For the 8xx
- CPUs, the SIU Watchdog feature is enabled in the SYPCR
- register. When supported for a specific SoC is
- available, then no further board specific code should
- be needed to use it.
-
- CONFIG_HW_WATCHDOG
- When using a watchdog circuitry external to the used
- SoC, then define this variable and provide board
- specific code for the "hw_watchdog_reset" function.
-
CONFIG_SYS_WATCHDOG_FREQ
Some platforms automatically call WATCHDOG_RESET()
from the timer interrupt handler every
sending again an USB request to the device.
- Journaling Flash filesystem support:
- CONFIG_JFFS2_NAND
- Define these for a default partition on a NAND device
-
CONFIG_SYS_JFFS2_FIRST_SECTOR,
CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
Define these for a default partition on a NOR device
SPI EEPROM, also an instance works with Crystal A/D and
D/As on the SACSng board)
- CONFIG_SOFT_SPI
-
- Enables a software (bit-bang) SPI driver rather than
- using hardware support. This is a general purpose
- driver that only requires three general I/O port pins
- (two outputs, one input) to function. If this is
- defined, the board configuration must define several
- SPI configuration items (port pins to use, etc). For
- an example, see include/configs/sacsng.h.
-
CONFIG_SYS_SPI_MXC_WAIT
Timeout for waiting until spi transfer completed.
default: (CONFIG_SYS_HZ/100) /* 10 ms */
Time to wait after FPGA configuration. The default is
200 ms.
-- Configuration Management:
-
- CONFIG_IDENT_STRING
-
- If defined, this string will be added to the U-Boot
- version information (U_BOOT_VERSION)
-
- Vendor Parameter Protection:
U-Boot considers the values of the environment
CONFIG_SPL_INIT_MINIMAL
Arch init code should be built for a very small image
- CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
- Partition on the MMC to load U-Boot from when the MMC is being
- used in raw mode
-
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
Sector to load kernel uImage from when MMC is being
used in raw mode (for Falcon mode)
+config ARCH_MAP_SYSMEM
+ depends on SANDBOX || NDS32
+ def_bool y
+
config CREATE_ARCH_SYMLINK
bool
Note that, its up to the individual architectures to implement
this functionality.
+config SYS_IMMR
+ hex
+ depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
+ default 0xFF000000 if MPC8xx
+ default 0xF0000000 if ARCH_MPC8313
+ default 0xE0000000 if MPC83xx && !ARCH_MPC8313
+ default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
+ default SYS_CCSRBAR_DEFAULT
+ help
+ Address for the Internal Memory-Mapped Registers (IMMR) window used
+ to configure the features of many Freescale / NXP SoCs.
+
config SKIP_LOWLEVEL_INIT
bool "Skip the calls to certain low level initialization functions"
depends on ARM || NDS32 || MIPS || RISCV
*/
#include <common.h>
+#include <clock_legacy.h>
#include <init.h>
#include <malloc.h>
#include <vsprintf.h>
{
timer_init();
- gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
+ gd->cpu_clk = get_board_sys_clk();
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
cache_init();
select SYS_CACHE_SHIFT_5
imply SYS_ARM_MMU
+config CPU_PXA27X
+ bool
+ select CPU_PXA
+
config CPU_SA1100
bool
select SYS_CACHE_SHIFT_5
config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
- select CPU_PXA
+ select CPU_PXA27X
select GPIO_EXTRA_HEADER
config ARCH_UNIPHIER
select OF_LIVE
select BOARD_LATE_INIT
select SYS_CACHE_SHIFT_7
+ select SYS_PCI_64BIT if PCI
imply OF_HAS_PRIOR_STAGE
config ARCH_OCTEONTX2
select OF_LIVE
select BOARD_LATE_INIT
select SYS_CACHE_SHIFT_7
+ select SYS_PCI_64BIT if PCI
imply OF_HAS_PRIOR_STAGE
config TARGET_THUNDERX_88XX
image headers.
endif
+config SYS_KWD_CONFIG
+ string "kwbimage config file path"
+ depends on ARCH_KIRKWOOD || ARCH_MVEBU
+ default "arch/arm/mach-mvebu/kwbimage.cfg"
+ help
+ Path within the source directory to the kwbimage.cfg file to use
+ when packaging the U-Boot image for use.
+
source "arch/arm/mach-apple/Kconfig"
source "arch/arm/mach-aspeed/Kconfig"
*/
#include <common.h>
+#include <clock_legacy.h>
#include <asm/arch/ep93xx.h>
#include <asm/io.h>
#include <div64.h>
/*
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ * get_board_sys_clk() should be defined as the input frequency of the PLL.
*
* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
* the specified bus in HZ.
/*
* return the PLL output frequency
*
- * PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
+ * PLL rate = get_board_sys_clk() * (X1FBD + 1) * (X2FBD + 1)
* / (X2IPD + 1) / 2^PS
*/
static ulong get_PLLCLK(uint32_t *pllreg)
{
uint8_t i;
const uint32_t clkset = readl(pllreg);
- uint64_t rate = CONFIG_SYS_CLK_FREQ;
+ uint64_t rate = get_board_sys_clk();
rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */
const uint32_t value = readl(&syscon->pwrcnt);
if (value & SYSCON_PWRCNT_UART_BAUD)
- uclk_rate = CONFIG_SYS_CLK_FREQ;
+ uclk_rate = get_board_sys_clk();
else
- uclk_rate = CONFIG_SYS_CLK_FREQ / 2;
+ uclk_rate = get_board_sys_clk() / 2;
return uclk_rate;
}
#include <common.h>
#if defined (CONFIG_IMX)
+#include <clock_legacy.h>
#include <asm/arch/imx-regs.h>
/* ------------------------------------------------------------------------- */
/* NOTE: This describes the proper use of this file.
*
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ * get_board_sys_clk() should be defined as the input frequency of the PLL.
* SH FIXME: 16780000 in our case
* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
* the specified bus in HZ.
mfi = mfi<=5 ? 5 : mfi;
- return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
+ return (2*(get_board_sys_clk()>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
}
ulong get_FCLK(void)
config ARCH_LS1021A
bool
+ select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
select SYS_FSL_DDR_BE if SYS_FSL_DDR
select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
select SYS_FSL_ERRATUM_A008378
uint i;
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
- unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+ unsigned long sysclk = get_board_sys_clk();
sys_info->freq_systembus = sysclk;
#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
sysclk_path = fdt_get_alias(blob, "sysclk");
if (sysclk_path)
do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
- CONFIG_SYS_CLK_FREQ, 1);
+ get_board_sys_clk(), 1);
do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
- "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+ "clock-frequency", get_board_sys_clk(), 1);
#if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
#define UBOOT_HEAD_LEN 0x1000
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
select FSL_TZASC_1
+ select FSL_TZPC_BP147
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_855873 if !TFABOOT
+ select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
select FSL_LAYERSCAPE
select FSL_LSCH2
select GICV2
config ARCH_LS1046A
bool
select ARMV8_SET_SMPEN
+ select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
select FSL_LAYERSCAPE
select FSL_LSCH2
select GICV2
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_855873 if !TFABOOT
+ select FSL_IFC
select FSL_LAYERSCAPE
select FSL_LSCH3
select GICV3
select ARM_ERRATA_828024
select ARM_ERRATA_829520
select ARM_ERRATA_833471
+ select FSL_IFC
select FSL_LAYERSCAPE
select FSL_LSCH3
select GICV3
select FSL_DDR_INTERACTIVE
select FSL_LAYERSCAPE
select FSL_LSCH3
+ select FSL_TZPC_BP147
select GICV3
select NXP_LSCH3_2
select SYS_HAS_SERDES
select SYS_FSL_HAS_DDR4
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
+ select SYS_PCI_64BIT if PCI
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
select FSL_DDR_INTERACTIVE
select FSL_LAYERSCAPE
select FSL_LSCH3
+ select FSL_TZPC_BP147
select GICV3
select HAS_FSL_XHCI_USB if USB_HOST
select NXP_LSCH3_2
select SYS_FSL_HAS_DDR4
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
+ select SYS_PCI_64BIT if PCI
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
menu "Layerscape clock tree configuration"
depends on FSL_LSCH2 || FSL_LSCH3
-config SYS_FSL_CLK
- bool "Enable clock tree initialization"
- default y
-
config CLUSTER_CLK_FREQ
int "Reference clock of core cluster"
depends on ARCH_LS1012A
*/
#include <common.h>
+#include <clock_legacy.h>
#include <cpu_func.h>
#include <env.h>
#include <fsl_ddr_sdram.h>
* controller is used, SYSCLK must meet the additional requirement
* of 100 MHz.
*/
- if (CONFIG_SYS_CLK_FREQ != 100000000) {
+ if (get_board_sys_clk() != 100000000) {
off = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3");
while (off != -FDT_ERR_NOTFOUND) {
fdt_status_disabled(blob, off);
#endif
do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",
- CONFIG_SYS_CLK_FREQ, 1);
+ get_board_sys_clk(), 1);
#ifdef CONFIG_GIC_V3_ITS
ls_gic_rd_tables_init(blob);
uint i, cluster;
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
- unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+ unsigned long sysclk = get_board_sys_clk();
unsigned long cluster_clk;
sys_info->freq_systembus = sysclk;
#ifndef CONFIG_CLUSTER_CLK_FREQ
-#define CONFIG_CLUSTER_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_CLUSTER_CLK_FREQ get_board_sys_clk()
#endif
cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
#endif
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
- unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+ unsigned long sysclk = get_board_sys_clk();
int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
u32 c_pll_sel, cplx_pll;
void *offset;
*/
#include <common.h>
+#include <clock_legacy.h>
#include <cpu_func.h>
#include <image.h>
#include <log.h>
i2c_init_all();
#endif
#endif
-#ifdef CONFIG_VID
+#if defined(CONFIG_VID) && (defined(CONFIG_ARCH_LS1088A) || \
+ defined(CONFIG_ARCH_LX2160A) || \
+ defined(CONFIG_ARCH_LX2162A))
init_func_vid();
#endif
dram_init();
#elif defined(CONFIG_ARCH_LS1028A)
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
-#define CONFIG_FSL_TZPC_BP147
#define CONFIG_FSL_TZASC_400
/* TZ Protection Controller Definitions */
#include <linux/bitops.h>
#endif
-#define CONFIG_SYS_IMMR 0x01000000
#define CONFIG_SYS_DCSRBAR 0x20000000
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
#ifndef __ARCH_FSL_LSCH3_IMMAP_H_
#define __ARCH_FSL_LSCH3_IMMAP_H_
-#define CONFIG_SYS_IMMR 0x01000000
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
#define OCRAM_BASE_S_ADDR 0x10010000
#define OCRAM_S_SIZE 0x00010000
-#define CONFIG_SYS_IMMR 0x01000000
#define CONFIG_SYS_DCSRBAR 0x20000000
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
config SYS_MALLOC_F_LEN
default 0x4000
+config LNX_KRNL_IMG_TEXT_OFFSET_BASE
+ default SYS_TEXT_BASE
+
endif
*/
#include <common.h>
+#include <clock_legacy.h>
#include <init.h>
#include <asm/arch/hardware.h>
#include <asm/global_data.h>
gd->bd->bi_dsp_freq = 0;
return 0;
}
+
+unsigned long get_board_sys_clk(void)
+{
+ return clk_get(DAVINCI_ARM_CLKID);
+}
*/
#include <common.h>
+#include <clock_legacy.h>
#include <log.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
/* SDIV [2:0] */
s = r & 0x7;
- freq = CONFIG_SYS_CLK_FREQ;
+ freq = get_board_sys_clk();
if (pllreg == EPLL || pllreg == RPLL) {
k = k & 0xffff;
RPLL};
sclk = get_pll_clk(reg_map[sel]);
} else
- sclk = CONFIG_SYS_CLK_FREQ;
+ sclk = get_board_sys_clk();
/*
* CLK_DIV_DISP10
* FIMD1_RATIO [3:0]
config IMXRT
bool
+ select SYS_FSL_ERRATUM_ESDHC135
config IMXRT1020
bool
if ARCH_KIRKWOOD
+config FEROCEON_88FR131
+ bool
+
+config KW88F6192
+ bool
+
+config KW88F6281
+ bool
+
+config SHEEVA_88SV131
+ bool
+
choice
prompt "Marvell Kirkwood board select"
optional
config TARGET_OPENRD
bool "Marvell OpenRD Board"
+ select KW88F6281
+ select SHEEVA_88SV131
config TARGET_DREAMPLUG
bool "DreamPlug Board"
+ select KW88F6281
+ select SHEEVA_88SV131
config TARGET_DS109
bool "Synology DS109"
+ select KW88F6281
+ select SHEEVA_88SV131
config TARGET_GURUPLUG
bool "GuruPlug Board"
+ select KW88F6281
+ select SHEEVA_88SV131
config TARGET_SHEEVAPLUG
bool "SheevaPlug Board"
+ select FEROCEON_88FR131
+ select KW88F6281
config TARGET_LSXL
bool "lsxl Board"
+ select FEROCEON_88FR131
+ select KW88F6281
config TARGET_POGO_E02
bool "pogo_e02 Board"
+ select FEROCEON_88FR131
+ select KW88F6281
config TARGET_DNS325
bool "dns325 Board"
+ select FEROCEON_88FR131
+ select KW88F6281
config TARGET_ICONNECT
bool "iconnect Board"
+ select FEROCEON_88FR131
+ select KW88F6281
config TARGET_KM_KIRKWOOD
bool "KM Kirkwood Board"
+ select FEROCEON_88FR131
+ select KW88F6281
select VENDOR_KM
config TARGET_NET2BIG_V2
bool "LaCie 2Big Network v2 NAS Board"
+ select FEROCEON_88FR131
+ select KW88F6281
config TARGET_NETSPACE_V2
bool "LaCie netspace_v2 Board"
+ select FEROCEON_88FR131
config TARGET_IB62X0
bool "ib62x0 Board"
+ select FEROCEON_88FR131
+ select KW88F6281
config TARGET_DOCKSTAR
bool "Dockstar Board"
+ select FEROCEON_88FR131
+ select KW88F6281
config TARGET_GOFLEXHOME
bool "GoFlex Home Board"
+ select FEROCEON_88FR131
+ select KW88F6281
config TARGET_NAS220
bool "BlackArmor NAS220"
+ select FEROCEON_88FR131
+ select KW88F6192
config TARGET_NSA310S
bool "Zyxel NSA310S"
+ select FEROCEON_88FR131
+ select KW88F6192
config TARGET_SBx81LIFKW
bool "Allied Telesis SBx81GS24/SBx81GT40/SBx81XS6/SBx81XS16"
+ select FEROCEON_88FR131
+ select KW88F6281
config TARGET_SBx81LIFXCAT
bool "Allied Telesis SBx81GP24/SBx81GT24"
+ select FEROCEON_88FR131
+ select KW88F6281
endchoice
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
-/*
- * By default kwbimage.cfg from board specific folder is used
- * If for some board, different configuration file need to be used,
- * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
- */
-#ifndef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
-#endif /* CONFIG_SYS_KWD_CONFIG */
-
/* Kirkwood has 2k of Security SRAM, use it for SP */
#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
#define CONFIG_SYS_L2_PL310
-/*
- * By default the generated mvebu kwbimage.cfg is used
- * If for some board, different configuration file need to be used,
- * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
- */
-#ifndef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG arch/arm/mach-mvebu/kwbimage.cfg
-#endif /* CONFIG_SYS_KWD_CONFIG */
-
/* end of 16M scrubbed by training in bootrom */
#define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000
endchoice
+config SYS_PLLFIN
+ int
+
+config TIMER_SYS_TICK_CH
+ int
+
config SYS_BOARD
default "nanopi2"
config SYS_CONFIG_NAME
default "s5p4418_nanopi2"
-endmenu
-
config SYS_PLLFIN
- int
+ default 24000000
config TIMER_SYS_TICK_CH
- int
+ default 0
+
+endmenu
source "board/friendlyarm/Kconfig"
string
default "octeontx"
-config SYS_PCI_64BIT
- bool
- default y
-
endif
string
default "octeontx2"
-config SYS_PCI_64BIT
- bool
- default y
-
endif
if ARCH_ORION5X
+config 88F5182
+ bool
+
+config FEROCEON
+ bool
+
choice
prompt "Marvell Orion board select"
optional
config TARGET_EDMINIV2
bool "LaCie Ethernet Disk mini V2"
+ select 88F5182
+ select FEROCEON
select SUPPORT_SPL
endchoice
select SPL
select TPL
select TPL_TINY_FRAMEWORK if TPL
- select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
select TPL_NEEDS_SEPARATE_STACK if TPL
imply SPL_SEPARATE_BSS
select SPL_SERIAL
select TPL
select TPL_DM
select TPL_OF_LIBFDT
- select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
select TPL_NEEDS_SEPARATE_STACK if TPL
select SPL_DRIVERS_MISC
imply ROCKCHIP_COMMON_BOARD
imply TPL_DRIVERS_MISC
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
- imply TPL_NEEDS_SEPARATE_TEXT_BASE
imply TPL_NEEDS_SEPARATE_STACK
imply TPL_OF_CONTROL
imply TPL_OF_PLATDATA
select SPL
select SUPPORT_TPL
select TPL
- select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
select TPL_NEEDS_SEPARATE_STACK if TPL
imply ROCKCHIP_COMMON_BOARD
imply ROCKCHIP_SDRAM_COMMON
select ARM64
select SUPPORT_SPL
select SUPPORT_TPL
- select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
select TPL_NEEDS_SEPARATE_STACK if TPL
imply ROCKCHIP_COMMON_BOARD
imply SPL_ROCKCHIP_COMMON_BOARD
select SPL_RAM if SPL
select SPL_REGMAP if SPL
select SPL_SYSCON if SPL
- select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
select TPL_NEEDS_SEPARATE_STACK if TPL
select SPL_SEPARATE_BSS
select SPL_SERIAL
#define CLK_D 1
#define CLK_P 2
-#ifndef CONFIG_SYS_CLK_FREQ_C100
-#define CONFIG_SYS_CLK_FREQ_C100 12000000
-#endif
-#ifndef CONFIG_SYS_CLK_FREQ_C110
-#define CONFIG_SYS_CLK_FREQ_C110 24000000
-#endif
+#define CFG_SYS_CLK_FREQ_C100 12000000
+#define CFG_SYS_CLK_FREQ_C110 24000000
/* s5pc110: return pll clock frequency */
static unsigned long s5pc100_get_pll_clk(int pllreg)
s = r & 0x7;
/* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
- freq = CONFIG_SYS_CLK_FREQ_C100;
+ freq = CFG_SYS_CLK_FREQ_C100;
fout = m * (freq / (p * (1 << s)));
return fout;
/* SDIV [2:0] */
s = r & 0x7;
- freq = CONFIG_SYS_CLK_FREQ_C110;
+ freq = CFG_SYS_CLK_FREQ_C110;
if (pllreg == APLL) {
if (s < 1)
s = 1;
Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
will be used for board configuration.
+config CPU_FREQ_HZ
+ int "CPU frequency"
+ default 800000000
+ help
+ The value, in Hz, that the CPU clock is running at.
+
config SYS_MALLOC_F_LEN
default 0x600
config TARGET_EB_CPU5282
bool "Support eb_cpu5282"
select M5282
+ select HW_WATCHDOG
config TARGET_M5208EVBE
bool "Support M5208EVBE"
*/
#ifndef CONFIG_TIMER
#include <common.h>
+#include <clock_legacy.h>
#include <init.h>
#include <irq_func.h>
#include <log.h>
lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
#else
lastdec = readl(&tmr->timer3_counter) /
- (CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ);
+ (get_board_sys_clk() / 2 / CONFIG_SYS_HZ);
#endif
timestamp = 0; /* start "advancing" time stamp from 0 */
ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
#else
ulong now = readl(&tmr->timer3_counter) /
- (CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ);
+ (get_board_sys_clk() / 2 / CONFIG_SYS_HZ);
#endif
debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
#ifdef CONFIG_FTTMR010_EXT_CLK
long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
#else
- long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000;
+ long tmo = usec * ((get_board_sys_clk() / 2) / 1000) / 1000;
#endif
unsigned long now, last = readl(&tmr->timer3_counter);
#ifdef CONFIG_FTTMR010_EXT_CLK
return CONFIG_SYS_HZ;
#else
- return CONFIG_SYS_CLK_FREQ;
+ return get_board_sys_clk();
#endif
}
#endif /* CONFIG_TIMER */
select SYS_CACHE_SHIFT_5
select FSL_ELBC
-config SYS_IMMR
- hex "Value for IMMR"
- default 0xE0000000
- help
- Address for the Internal Memory-Mapped Registers (IMMR) window used
- to configure the features of the SoC.
-
source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig"
source "arch/powerpc/cpu/mpc83xx/bats/Kconfig"
source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig"
source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig"
source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig"
+config 83XX_PCICLK
+ hex "PCI clock frequency"
+ default 0xDEADBEEF
+ help
+ If required, the PCI clock frequency to use when configuring
+ the host bridge.
+
config FSL_ELBC
bool
*/
#include <common.h>
+#include <clock_legacy.h>
#include <pci.h>
#include <mpc83xx.h>
#include <asm/global_data.h>
clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
sccr = im->clk.sccr;
- pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
+ pci_sync_in = get_board_sys_clk() / (1 + clkin_div);
spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
if (im->reset.rcwh & HRCWH_PCI_HOST) {
-#if defined(CONFIG_SYS_CLK_FREQ)
- pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
+#if CONFIG_SYS_CLK_FREQ != 0
+ pci_sync_in = get_board_sys_clk() / (1 + clkin_div);
#else
pci_sync_in = 0xDEADBEEF;
#endif
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
- return CONFIG_SYS_CLK_FREQ * spmf;
+ return get_board_sys_clk() * spmf;
}
#include <config.h>
#include <mpc83xx.h>
-#define CONFIG_83XX 1 /* needed for Linux kernel header files*/
-
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#ifndef CONFIG_DEFAULT_IMMR
#error CONFIG_DEFAULT_IMMR must be defined
#endif /* CONFIG_DEFAULT_IMMR */
-#ifndef CONFIG_SYS_IMMR
-#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR
-#endif /* CONFIG_SYS_IMMR */
/*
* After configuration, a system reset exception is executed using the
bool
select FSL_LAW
select SYS_CACHE_SHIFT_5
+ select SYS_HAS_SERDES
select SYS_FSL_ERRATUM_A004477
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
config SYS_FSL_ERRATUM_USB14
bool
+config SYS_HAS_SERDES
+ bool
+
config SYS_P4080_ERRATUM_CPU22
bool
config SYS_PPC_E500_USE_DEBUG_TLB
bool
-config FSL_IFC
- bool
-
config FSL_ELBC
bool
#ifdef CONFIG_FSL_CORENET
do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
- "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+ "clock-frequency", get_board_sys_clk(), 1);
do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0",
- "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+ "clock-frequency", get_board_sys_clk(), 1);
do_fixup_by_compat_u32(blob, "fsl,mpic",
"clock-frequency", get_bus_freq(0)/2, 1);
#else
uint rcw_tmp;
#endif
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
- unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+ unsigned long sysclk = get_board_sys_clk();
uint mem_pll_rat;
sys_info->freq_systembus = sysclk;
* are driven by differential sysclock.
*/
if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
- sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
+ sys_info->freq_ddrbus = get_board_sys_clk();
else
#endif
#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
plat_ratio = (gur->porpllsr) & 0x0000003e;
plat_ratio >>= 1;
- sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
+ sys_info->freq_systembus = plat_ratio * get_board_sys_clk();
/* Divide before multiply to avoid integer
* overflow for processor speeds above 2GHz */
#else
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
- sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
+ sys_info->freq_qe = qe_ratio * get_board_sys_clk();
#endif
#endif
help
Debug Event Register (37-47)
-config SYS_IMMR
- hex "Value for IMMR"
-
source "board/cssi/MCR3000/Kconfig"
endmenu
menu "Sandbox architecture"
depends on SANDBOX
-config ARCH_MAP_SYSMEM
- def_bool y
-
config SYS_ARCH
default "sandbox"
config CPU_SH4
bool
+config CPU_SH7751
+ bool
+ select CPU_SH4
+
choice
prompt "Target select"
optional
config TARGET_R2DPLUS
bool "Renesas R2D-PLUS"
- select CPU_SH4
+ select CPU_SH7751
endchoice
/* Timer */
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
-#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4)
+#define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 4)
#endif
*/
#include <common.h>
+#include <clock_legacy.h>
#include <time.h>
#include <asm/global_data.h>
#include <linux/delay.h>
void __udelay(unsigned long usec)
{
ulong lo, hi, i;
- ulong mhz = CONFIG_SYS_CLK_FREQ / 1000000;
+ ulong mhz = get_board_sys_clk() / 1000000;
/* Scale to support full 32-bit usec range */
#if XCHAL_HAVE_CCOUNT
register ulong ccount;
__asm__ volatile ("rsr %0, CCOUNT" : "=a"(ccount));
- return ccount / (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - base;
+ return ccount / (get_board_sys_clk() / CONFIG_SYS_HZ) - base;
#else
/*
* Add at least the overhead of this call (in cycles).
*/
fake_ccount += 20;
- return fake_ccount / (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - base;
+ return fake_ccount / (get_board_sys_clk() / CONFIG_SYS_HZ) - base;
#endif
}
unsigned long ccount;
__asm__ volatile ("rsr %0, CCOUNT" : "=a"(ccount));
- return ccount / (CONFIG_SYS_CLK_FREQ / 1000000);
+ return ccount / (get_board_sys_clk() / 1000000);
}
#endif
if TARGET_NET2BIG_V2
+choice
+ prompt "Board variant"
+
+config D2NET_V2
+ bool "D2NET v2"
+
+config NET2BIG_V2
+ bool "NET2BIG v2"
+
+endchoice
+
config SYS_BOARD
default "net2big_v2"
if TARGET_NETSPACE_V2
+choice
+ prompt "Board variant"
+
+config INETSPACE_V2
+ bool "INETSPACE v2"
+ select KW88F6281
+
+config NETSPACE_LITE_V2
+ bool "NETSPACE LITE v2"
+ select KW88F6192
+
+config NETSPACE_MAX_V2
+ bool "NETSPACE MAX v2"
+ select KW88F6281
+
+config NETSPACE_MINI_V2
+ bool "NETSPACE MINI v2"
+ select KW88F6192
+
+config NETSPACE_V2
+ bool "NETSPACE v2"
+ select KW88F6281
+
+endchoice
+
config SYS_BOARD
default "netspace_v2"
if TARGET_OPENRD
+choice
+ prompt "Board variant"
+
+config BOARD_IS_OPENRD_BASE
+ bool "Base"
+
+config BOARD_IS_OPENRD_CLIENT
+ bool "Client"
+
+config BOARD_IS_OPENRD_ULTIMATE
+ bool "Ultimate"
+
+endchoice
+
config SYS_BOARD
default "openrd"
*/
#include <common.h>
+#include <clock_legacy.h>
#include <command.h>
#include <dm.h>
#include <init.h>
return 0;
}
-int board_postclk_init(void)
+unsigned long get_board_sys_clk(void)
{
/*
* Obtain CPU clock frequency from board and cache in global
*/
#ifdef CONFIG_SYS_FPGAREG_FREQ
- gd->cpu_clk = (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
+ return (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
#else
/* early Tensilica bitstreams lack this reg, but most run at 50 MHz */
- gd->cpu_clk = 50000000UL;
+ return 50000000;
#endif
+}
+
+int board_postclk_init(void)
+{
+ gd->cpu_clk = get_board_sys_clk();
+
return 0;
}
int
default 0
-config SYS_MMC_IMG_LOAD_PART
- int
- default 1
-
config SYS_USB_IMG_LOAD_PART
int
default 1
This option enables the PCA9547 I2C mux on Freescale boards.
config VID
- depends on DM_I2C
bool "Enable Freescale VID"
+ depends on I2C || DM_I2C
help
This option enables setting core voltage based on individual
values saved in SoC fuses.
+config SPL_VID
+ bool "Enable Freescale VID in SPL"
+ depends on I2C || DM_I2C
+ help
+ This option enables setting core voltage based on individual
+ values saved in SoC fuses, in SPL.
+
+if VID || SPL_VID
+
+config VID_FLS_ENV
+ string "Environment variable for overriding VDD"
+ help
+ This option allows for specifying the environment variable
+ to check to override VDD information.
+
+config VOL_MONITOR_INA220
+ bool "Enable the INA220 voltage monitor read"
+ help
+ This option enables INA220 voltage monitor read
+ functionality. It is used by the common VID driver.
+
+config VOL_MONITOR_IR36021_READ
+ bool "Enable the IR36021 voltage monitor read"
+ help
+ This option enables IR36021 voltage monitor read
+ functionality. It is used by the common VID driver.
+
+config VOL_MONITOR_IR36021_SET
+ bool "Enable the IR36021 voltage monitor set"
+ help
+ This option enables IR36021 voltage monitor set
+ functionality. It is used by the common VID driver.
+
config VOL_MONITOR_LTC3882_READ
- depends on VID
bool "Enable the LTC3882 voltage monitor read"
help
This option enables LTC3882 voltage monitor read
functionality. It is used by the common VID driver.
config VOL_MONITOR_LTC3882_SET
- depends on VID
bool "Enable the LTC3882 voltage monitor set"
help
This option enables LTC3882 voltage monitor set
functionality. It is used by the common VID driver.
config VOL_MONITOR_ISL68233_READ
- depends on VID
bool "Enable the ISL68233 voltage monitor read"
help
This option enables ISL68233 voltage monitor read
functionality. It is used by the common VID driver.
config VOL_MONITOR_ISL68233_SET
- depends on VID
bool "Enable the ISL68233 voltage monitor set"
help
This option enables ISL68233 voltage monitor set
functionality. It is used by the common VID driver.
+
+endif
endif
obj-$(I2C_COMMON) += i2c_common.o
obj-$(CONFIG_FSL_USE_PCA9547_MUX) += i2c_mux.o
-obj-$(CONFIG_VID) += vid.o
+obj-$(CONFIG_$(SPL_)VID) += vid.o
obj-$(CONFIG_FSL_QIXIS) += qixis.o
obj-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o
ifndef CONFIG_SPL_BUILD
#include <common.h>
-
+#include <clock_legacy.h>
/*
* CADMUS Board System Registers
unsigned long
-get_clock_freq(void)
+get_board_sys_clk(void)
{
volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
/*
* Returns either 33000000 or 66000000 as the SYS_CLK_FREQ.
*/
-extern unsigned long get_clock_freq(void);
+extern unsigned long get_board_sys_clk(void);
/*
*/
#include <common.h>
+#include <clock_legacy.h>
#include <log.h>
#include <asm/io.h>
in_8(&fpga_reg->sclk[2]));
}
+#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
unsigned long get_board_ddr_clk(void)
{
return ics307_clk_freq(
in_8(&fpga_reg->dclk[1]),
in_8(&fpga_reg->dclk[2]));
}
+#endif
return 0;
}
+#ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
}
return 66666666;
}
+#endif
#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
unsigned long get_board_ddr_clk(void)
*/
#include <common.h>
+#include <clock_legacy.h>
#include <i2c.h>
#include <fdt_support.h>
#include <fsl_ddr_sdram.h>
*/
#include <common.h>
+#include <clock_legacy.h>
#include <i2c.h>
#include <fdt_support.h>
#include <fsl_ddr_sdram.h>
* Copyright 2017-2018 NXP
*/
#include <common.h>
+#include <clock_legacy.h>
#include <env.h>
#include <i2c.h>
#include <init.h>
#endif
}
+#ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
return 66666666;
}
+#endif
+#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
unsigned long get_board_ddr_clk(void)
{
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
return 66666666;
}
+#endif
#if !defined(CONFIG_SPL_BUILD)
void board_retimer_init(void)
* Copyright 2015 Freescale Semiconductor
*/
#include <common.h>
+#include <clock_legacy.h>
#include <env.h>
#include <init.h>
#include <malloc.h>
* Copyright 2017 NXP
*/
#include <common.h>
+#include <clock_legacy.h>
#include <env.h>
#include <init.h>
#include <malloc.h>
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+ gd->bus_clk = get_board_sys_clk() * plat_ratio;
ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
gd->bus_clk / 16 / CONFIG_BAUDRATE);
* Copyright 2011 Freescale Semiconductor, Inc.
*/
#include <common.h>
+#include <clock_legacy.h>
#include <init.h>
#include <mpc85xx.h>
#include <asm/io.h>
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+ gd->bus_clk = get_board_sys_clk() * plat_ratio;
ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
gd->bus_clk / 16 / CONFIG_BAUDRATE);
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
- bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+ bus_clk = get_board_sys_clk() * plat_ratio;
gd->bus_clk = bus_clk;
ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
*/
#include <common.h>
+#include <clock_legacy.h>
#include <init.h>
#include <ns16550.h>
#include <asm/io.h>
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+ gd->bus_clk = get_board_sys_clk() * plat_ratio;
ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
gd->bus_clk / 16 / CONFIG_BAUDRATE);
*/
#include <common.h>
+#include <clock_legacy.h>
#include <command.h>
#include <env.h>
#include <fdt_support.h>
return 0;
}
-unsigned long get_board_sys_clk(unsigned long dummy)
+unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = CPLD_READ(sysclk_sw1);
return CONFIG_SYS_L3_SIZE;
}
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
#if defined(CONFIG_SPL_MMC_BOOT)
#define GPIO1_SD_SEL 0x00020000
int board_mmc_getcd(struct mmc *mmc)
return 0;
}
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
#ifdef CONFIG_TARGET_T1024RDB
void board_reset(void)
{
return CONFIG_SYS_L3_SIZE;
}
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
void board_init_f(ulong bootflag)
{
*/
#include <common.h>
+#include <clock_legacy.h>
#include <command.h>
#include <env.h>
#include <fdt_support.h>
return CONFIG_SYS_L3_SIZE;
}
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
return 0;
}
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
int misc_init_r(void)
{
u8 reg;
return CONFIG_SYS_L3_SIZE;
}
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
return (gd->bus_clk / 2);
}
-unsigned long get_board_sys_clk(unsigned long dummy)
-{
- return 66666666;
-}
-
int misc_init_f(void)
{
/* configure QRIO pis for i2c deblocking */
displ5_set_iomux_misc_spl();
/* Initialize and reset WDT in SPL */
+#ifdef CONFIG_SPL_WATCHDOG
hw_watchdog_init();
WATCHDOG_RESET();
+#endif
/* load/boot image from boot device */
board_init_r(NULL, 0);
*/
#include <common.h>
+#include <clock_legacy.h>
#include <cpu_func.h>
#include <hang.h>
#include <init.h>
writel(0xA5A5A500, &swdt->swtcsra);
/* CPU frequency setting. Set to 0.8GHz */
- stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_OFFSET;
+ stc = ((800 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_OFFSET;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
}
*/
#include <common.h>
+#include <clock_legacy.h>
#include <cpu_func.h>
#include <env.h>
#include <hang.h>
writel(0xA5A5A500, &swdt->swtcsra);
/* CPU frequency setting. Set to 1.5GHz */
- stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
+ stc = ((1500 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
/* QoS */
*/
#include <common.h>
+#include <clock_legacy.h>
#include <cpu_func.h>
#include <env.h>
#include <hang.h>
writel(0xA5A5A500, &swdt->swtcsra);
/* CPU frequency setting. Set to 1.5GHz */
- stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
+ stc = ((1500 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
/* QoS */
*/
#include <common.h>
+#include <clock_legacy.h>
#include <cpu_func.h>
#include <env.h>
#include <env_internal.h>
/* CPU frequency setting. Set to 1.4GHz */
if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
u32 stat = 0;
- u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
+ u32 stc = ((1400 / CLK2MHZ(get_board_sys_clk())) - 1)
<< PLL0_STC_BIT;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
*/
#include <common.h>
+#include <clock_legacy.h>
#include <cpu_func.h>
#include <env.h>
#include <hang.h>
writel(0xA5A5A500, &swdt->swtcsra);
/* CPU frequency setting. Set to 1.5GHz */
- stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
+ stc = ((1500 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
/* QoS */
*/
#include <common.h>
+#include <clock_legacy.h>
#include <env.h>
#include <init.h>
#include <malloc.h>
/* CPU frequency setting. Set to 1.4GHz */
if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
u32 stat = 0;
- u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
+ u32 stc = ((1400 / CLK2MHZ(get_board_sys_clk())) - 1)
<< PLL0_STC_BIT;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
F: include/configs/capricorn-common.h
F: include/configs/deneb.h
F: include/configs/giedi.h
-F: include/configs/siemens-ccp-common.h
F: include/configs/siemens-env-common.h
F: configs/deneb_defconfig
F: configs/giedi_defconfig
/* Check the PCI_clk sel bit */
if (in_be32(&gur->porpllsr) & (1<<15)) {
src = "SYSCLK";
- f = CONFIG_SYS_CLK_FREQ;
+ f = get_board_sys_clk();
} else {
src = "PCI_CLK";
f = CONFIG_PCI_CLK_FREQ;
*/
#include <common.h>
+#include <clock_legacy.h>
#include <dm.h>
#include <env.h>
#include <hang.h>
* assured it's being powered with suitable core voltage
*/
if (!power_failed)
- clock_set_pll1(CONFIG_SYS_CLK_FREQ);
+ clock_set_pll1(get_board_sys_clk());
else
printf("Failed to set core voltage! Can't set CPU frequency\n");
}
partition that is typically specified with root=/dev/sdaX or
which gets converted into a root=PARTUUID=some_uuid.
-config SYS_FDT_ADDR
- hex "FDT load address"
- default 0x83000000
- help
- The address the FDT file should be loaded to.
-
config IMX_CONFIG
default "board/warp7/imximage.cfg"
config SYS_CONFIG_NAME
default "xenguest_arm64"
+config LNX_KRNL_IMG_TEXT_OFFSET_BASE
+ default SYS_LOAD_ADDR
+
endif
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-obj-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o
obj-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o
obj-$(CONFIG_ARCH_P2020) += fsl_8xxx_clk.o
obj-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o
*/
#include <common.h>
+#include <clock_legacy.h>
#include <asm/io.h>
/*
* Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
*/
-unsigned long get_board_sys_clk(ulong dummy)
+unsigned long get_board_sys_clk(void)
{
#if defined(CONFIG_MPC85xx)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
* Return DDR input clock - synchronous with SYSCLK or 66 MHz
* Note: 86xx doesn't support asynchronous DDR clk
*/
-unsigned long get_board_ddr_clk(ulong dummy)
+unsigned long get_board_ddr_clk(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9;
if (ddr_ratio == 0x7)
- return get_board_sys_clk(dummy);
+ return get_board_sys_clk();
#ifdef CONFIG_ARCH_P2020
if (in_be32(&gur->gpporcr) & 0x20000)
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2007-2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <linux/compiler.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_pci_setup(void *blob, struct bd_info *bd)
-{
- FT_FSL_PCI_SETUP;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
help
The address in memory that U-Boot will be running from, initially.
+config DYNAMIC_SYS_CLK_FREQ
+ bool "Determine CPU clock frequency at run-time"
+ help
+ Implement a get_board_sys_clk function that will determine the CPU
+ clock frequency at run time, rather than define it statically.
+
config SYS_CLK_FREQ
- depends on ARC || ARCH_SUNXI || MPC83xx
+ depends on !DYNAMIC_SYS_CLK_FREQ
int "CPU clock frequency"
+ default 125000000 if ARCH_LS1012A
+ default 100000000 if ARCH_P2020 || ARCH_T1024 || ARCH_T1042 || \
+ ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
+ default 66666666 if ARCH_P1010 || ARCH_P1020 || ARCH_T4240
+ default 66660000 if ARCH_T2080
+ default 33333333 if RCAR_GEN3
+ default 24000000 if ARCH_EXYNOS
+ default 20000000 if RCAR_GEN2
+ default 0
help
- TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture
+ A static value for the CPU frequency. Note that if not required
+ for a given SoC, this can be left at 0.
config ARCH_FIXUP_FDT_MEMORY
bool "Enable arch_fixup_memory_banks() call"
booted via SD/EMMC. This is not a must, some SoCs need this,
some not.
+config SD_BOOT_QSPI
+ bool "Support for booting from SD/EMMC and enable QSPI"
+ help
+ Enabling this will make a U-Boot binary that is capable of being
+ booted via SD/EMMC while enabling QSPI on the platform as well. This
+ is not a must, some SoCs need this, some not.
+
config SPI_BOOT
bool "Support for booting from SPI flash"
help
config SYS_MEMTEST_START
hex "default start address for mtest"
- default 0
+ default 0x0
help
This is the default start address for mtest for simple read/write
test. If no arguments are given to mtest, default address is used
provide the ability to load files, list directories and obtain
filesystem information.
+config JFFS2_DEV
+ string "Default device for JFFS2"
+ depends on CMD_JFFS2
+ default "nor0"
+ help
+ The default device to use with the jffs2 command.
+
+config JFFS2_PART_OFFSET
+ hex "Default offset within flash to locate the JFFS2 image"
+ depends on CMD_JFFS2
+ default 0x0
+ help
+ The default offset within flash to locate the JFFS2 image.
+
+config JFFS2_PART_SIZE
+ hex "Default size of JFFS2 partition"
+ depends on CMD_JFFS2
+ default 0xFFFFFFFF
+ help
+ The default size of the JFFS2 partition
+
config CMD_MTDPARTS
bool "MTD partition support"
depends on MTD
/* id */
id->mtd_id = "single part";
-#if defined(CONFIG_JFFS2_DEV)
dev_name = CONFIG_JFFS2_DEV;
-#else
- dev_name = "nor0";
-#endif
if ((mtd_id_parse(dev_name, NULL, &id->type, &id->num) != 0) ||
(mtd_device_validate(id->type, id->num, &size) != 0)) {
part->name = "static";
part->auto_name = 0;
-#if defined(CONFIG_JFFS2_PART_SIZE)
part->size = CONFIG_JFFS2_PART_SIZE;
-#else
- part->size = SIZE_REMAINING;
-#endif
-#if defined(CONFIG_JFFS2_PART_OFFSET)
part->offset = CONFIG_JFFS2_PART_OFFSET;
-#else
- part->offset = 0x00000000;
-#endif
part->dev = current_mtd_dev;
INIT_LIST_HEAD(&part->link);
u32 erase_bytes;
/* Probe the SPI bus to get the flash device */
- flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
- CONFIG_ENV_SPI_CS,
+ flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
+ CONFIG_SF_DEFAULT_CS,
CONFIG_SF_DEFAULT_SPEED,
CONFIG_SF_DEFAULT_MODE);
if (!flash) {
So this config enable the late init code with the help of board_late_init
function which should defined on respective boards.
+config SYS_FSL_CLK
+ bool
+ depends on ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 || \
+ (FSL_ESDHC_IMX && (ARCH_MX5 || ARCH_MX6 || ARCH_MX7))
+ default y
+ help
+ Enable to call get_clocks() in board_init_f() for platforms other
+ than PowerPC or M68k. This is a legacy option. If not TARGET_BRPPT2
+
config LAST_STAGE_INIT
bool "Call board-specific as last setup step"
help
May be left empty to trigger the Makefile infrastructure to
fall back to the linker-script used for the SPL stage.
-config TPL_NEEDS_SEPARATE_TEXT_BASE
- bool "TPL needs a separate text-base"
- depends on TPL
- help
- Enable, if the TPL stage should not inherit its text-base
- from the SPL stage. When enabled, a base address for the
- .text sections of the TPL stage has to be set below.
-
config TPL_NEEDS_SEPARATE_STACK
bool "TPL needs a separate initial stack-pointer"
depends on TPL
config TPL_TEXT_BASE
hex "Base address for the .text section of the TPL stage"
- depends on TPL_NEEDS_SEPARATE_TEXT_BASE
help
The base address for the .text section of the TPL stage.
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="mcr3000"
CONFIG_MPC8xx=y
-CONFIG_SYS_IMMR=0xFF000000
CONFIG_TARGET_MCR3000=y
CONFIG_8xx_GCLK_FREQ=132000000
CONFIG_CMD_IMMAP=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="mpc8379erdb"
CONFIG_SYS_CLK_FREQ=66666667
+# CONFIG_SYS_PCI_64BIT is not set
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC837XERDB=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_PHYS_64BIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_SERIAL=y
+CONFIG_TPL_TEXT_BASE=0xD0001000
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_ADDR_MAP=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_SERIAL=y
+CONFIG_TPL_TEXT_BASE=0xD0001000
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_SERIAL=y
+CONFIG_TPL_TEXT_BASE=0xD0001000
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_ADDR_MAP=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_SERIAL=y
+CONFIG_TPL_TEXT_BASE=0xD0001000
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_SERIAL=y
+CONFIG_TPL_TEXT_BASE=0xF8F81000
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_ELBC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_SERIAL=y
+CONFIG_TPL_TEXT_BASE=0xF8F81000
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_ELBC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_SERIAL=y
+CONFIG_TPL_TEXT_BASE=0xF8F81000
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_ELBC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_SERIAL=y
+CONFIG_TPL_TEXT_BASE=0xF8F81000
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_ELBC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_SERIAL=y
+CONFIG_TPL_TEXT_BASE=0xF8F81000
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_ELBC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg"
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg"
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg"
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg"
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg"
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg"
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p4080ds.cfg"
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p4080ds.cfg"
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg"
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg"
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg"
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/alliedtelesis/SBx81LIFKW/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x00600000
CONFIG_TARGET_SBx81LIFKW=y
CONFIG_ENV_SIZE=0x2000
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=20000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_KIRKWOOD_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
CONFIG_MV88E61XX_SWITCH=y
CONFIG_MV88E61XX_CPU_PORT=10
CONFIG_MV88E61XX_PHY_PORTS=0x003
CONFIG_MV88E61XX_FIXED_PORTS=0x300
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
+CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_DM_RTC=y
CONFIG_RTC_MV=y
+CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/alliedtelesis/SBx81LIFXCAT/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x00600000
CONFIG_TARGET_SBx81LIFXCAT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=20000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_KIRKWOOD_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
CONFIG_MV88E61XX_SWITCH=y
CONFIG_MV88E61XX_CPU_PORT=10
CONFIG_MV88E61XX_PHY_PORTS=0x003
CONFIG_MV88E61XX_FIXED_PORTS=0x300
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
+CONFIG_MVGBE=y
CONFIG_MII=y
+CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_FMAN_FW_ADDR=0x280000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
+CONFIG_U_QE=y
CONFIG_SYS_QE_FW_ADDR=0x380000
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_DM_RTC=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_SYS_FMAN_FW_ADDR=0x10400
CONFIG_MII=y
CONFIG_PCIE_FSL=y
+CONFIG_U_QE=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_SYS_FMAN_FW_ADDR=0x110000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
+CONFIG_U_QE=y
CONFIG_SYS_QE_FW_ADDR=0x130000
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_RTC=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
CONFIG_MII=y
CONFIG_PCIE_FSL=y
+CONFIG_U_QE=y
CONFIG_SYS_QE_FW_ADDR=0xEFF10000
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_RTC=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_nand_rcw.cfg"
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_EON=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_sd_rcw.cfg"
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_NXP_ESBC=y
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_spi_rcw.cfg"
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_ENV_OFFSET=0x100000
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_ENV_OFFSET=0x100000
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_ENV_OFFSET=0x100000
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_ENV_OFFSET=0x100000
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_ENV_OFFSET=0x100000
CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte"
CONFIG_SYS_LOAD_ADDR=0x40001000
CONFIG_FIT=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="echo Read pressed buttons status;KEY_VOLUMEUP=gpa20;KEY_HOME=gpa17;KEY_VOLUMEDOWN=gpa21;KEY_POWER=gpa00;PRESSED=0;RELEASED=1;if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; else setenv VOLUME_UP $RELEASED; fi;if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; else setenv VOLUME_DOWN $RELEASED; fi;if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte"
CONFIG_SYS_LOAD_ADDR=0x40001000
CONFIG_FIT=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="echo Read pressed buttons status;KEY_VOLUMEUP=gpa20;KEY_HOME=gpa17;KEY_VOLUMEDOWN=gpa21;KEY_POWER=gpa00;PRESSED=0;RELEASED=1;if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; else setenv VOLUME_UP $RELEASED; fi;if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; else setenv VOLUME_DOWN $RELEASED; fi;if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="exynos78x0-axy17lte"
CONFIG_SYS_LOAD_ADDR=0x40001000
CONFIG_FIT=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="echo Read pressed buttons status;KEY_VOLUMEUP=gpa20;KEY_HOME=gpa17;KEY_VOLUMEDOWN=gpa21;KEY_POWER=gpa00;PRESSED=0;RELEASED=1;if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; else setenv VOLUME_UP $RELEASED; fi;if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; else setenv VOLUME_DOWN $RELEASED; fi;if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPIO=y
CONFIG_ENV_OFFSET=0x140000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae3xx"
+CONFIG_SYS_CLK_FREQ=39062500
CONFIG_TARGET_ADP_AE3XX=y
CONFIG_SYS_LOAD_ADDR=0x300000
CONFIG_FIT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="ag101p"
+CONFIG_SYS_CLK_FREQ=39062500
CONFIG_TARGET_ADP_AG101P=y
CONFIG_SYS_LOAD_ADDR=0x300000
CONFIG_FIT=y
CONFIG_CFI_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_FTMAC100=y
CONFIG_BAUDRATE=38400
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_FTMAC100=y
CONFIG_BAUDRATE=38400
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_FTMAC100=y
CONFIG_BAUDRATE=38400
CONFIG_CFI_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_FTMAC100=y
CONFIG_BAUDRATE=38400
CONFIG_CFI_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_FTMAC100=y
CONFIG_BAUDRATE=38400
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_FTMAC100=y
CONFIG_BAUDRATE=38400
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_FTMAC100=y
CONFIG_BAUDRATE=38400
CONFIG_CFI_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_FTMAC100=y
CONFIG_BAUDRATE=38400
CONFIG_TARGET_AM642_A53_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
+CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am642-evm"
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
-CONFIG_SPL_DM_GPIO=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
-CONFIG_CLK_TI_SCI=y
-CONFIG_CLK_CCF=y
CONFIG_SPL_CLK_CCF=y
+CONFIG_CLK_CCF=y
+CONFIG_CLK_TI_SCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_OMAP24XX=y
-CONFIG_DM_GPIO=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_PHY=y
CONFIG_SPL_PHY=y
CONFIG_PHY_CADENCE_TORRENT=y
-CONFIG_SPL_PHY_CADENCE_TORRENT=y
CONFIG_PHY_J721E_WIZ=y
-CONFIG_SPL_PHY_J721E_WIZ=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
CONFIG_DM_GPIO=y
-CONFIG_SPL_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-evm"
CONFIG_SPL_TEXT_BASE=0x70000000
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
-CONFIG_CLK_TI_SCI=y
-CONFIG_CLK_CCF=y
CONFIG_SPL_CLK_CCF=y
+CONFIG_CLK_CCF=y
+CONFIG_CLK_TI_SCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_PHY=y
CONFIG_SPL_PHY=y
CONFIG_PHY_CADENCE_SIERRA=y
-CONFIG_SPL_PHY_CADENCE_SIERRA=y
CONFIG_PHY_CADENCE_TORRENT=y
-CONFIG_SPL_PHY_CADENCE_TORRENT=y
CONFIG_PHY_J721E_WIZ=y
-CONFIG_SPL_PHY_J721E_WIZ=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-flash.0:256k(u-boot),64k(u-boot-env),6144k(rootfs),1600k(uImage),64k(NVRAM),64k(ART)"
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=25000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-flash.0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1472k(uImage),64k(ART)"
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=25000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-flash.0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1472k(uImage),64k(ART)"
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SPI_MAX_HZ=25000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
CONFIG_MTD=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ARCH_RMOBILE_BOARD_STRING="Armadillo-800EVA Board"
CONFIG_R8A7740=y
CONFIG_TARGET_ARMADILLO_800EVA=y
+CONFIG_SYS_CLK_FREQ=50000000
CONFIG_SYS_LOAD_ADDR=0x44000000
CONFIG_BOOTDELAY=3
# CONFIG_CMDLINE_EDITING is not set
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MCFUART=y
+CONFIG_WATCHDOG=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=15000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=15000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=15000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=15000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=15000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=15000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=15000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=15000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=15000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=15000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=15000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=15000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=15000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SPL_SPI=y
CONFIG_ZYNQ_MAC_IN_EEPROM=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xfa
+CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCMSTB=y
CONFIG_MTD=y
+CONFIG_SYS_NS16550=y
# CONFIG_EFI_LOADER is not set
CONFIG_MMC_SDHCI_BCMSTB=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_BCMSTB_SPI=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_SYS_BOARD="antminer_s9"
CONFIG_SYS_CONFIG_NAME="bitmain_antminer_s9"
CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=0
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_WATCHDOG=y
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_ARCH_TIMER=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="chromebook_coral"
CONFIG_SPL_TEXT_BASE=0xfef10000
+CONFIG_TPL_TEXT_BASE=0xffff8000
CONFIG_SPL_SYS_MALLOC_F_LEN=0xf000
CONFIG_BOOTSTAGE_STASH_ADDR=0xfef00000
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_ARCH_TIMER=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_ARCH_TIMER=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus"
CONFIG_SPL_TEXT_BASE=0xffe70000
+CONFIG_TPL_TEXT_BASE=0xfffd8000
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_ARCH_TIMER=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
# CONFIG_SPL_BANNER_PRINT is not set
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1c
CONFIG_SPL_MMC_TINY=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_DM=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_VERSION_VARIABLE=y
# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_JZ4780_EFUSE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x00110000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_NFS is not set
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_TEGRA_NAND=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_DM_PMIC=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_CMD_EXT4=y
CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
CONFIG_IDENT_STRING="Presidio-SoC"
CONFIG_SYS_LOAD_ADDR=0x10000000
+CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
CONFIG_IDENT_STRING="Presidio-SoC"
CONFIG_SYS_LOAD_ADDR=0x10000000
+CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
CONFIG_IDENT_STRING="Presidio-SoC"
CONFIG_SYS_LOAD_ADDR=0x10000000
+CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_KWD_CONFIG="board/mikrotik/crs3xx-98dx3236/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_CRS3XX_98DX3236=y
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_KWD_CONFIG="board/mikrotik/crs3xx-98dx3236/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_CRS3XX_98DX3236=y
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_KWD_CONFIG="board/mikrotik/crs3xx-98dx3236/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_CRS3XX_98DX3236=y
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_KWD_CONFIG="board/mikrotik/crs3xx-98dx3236/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_CRS3XX_98DX3236=y
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_KWD_CONFIG="board/mikrotik/crs3xx-98dx3236/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_CRS3XX_98DX3236=y
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_KWD_CONFIG="board/mikrotik/crs3xx-98dx3236/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_CRS3XX_98DX3236=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/LaCie/net2big_v2/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_NET2BIG_V2=y
CONFIG_IDENT_STRING=" D2 v2"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
-CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=20000000
CONFIG_ENV_ADDR=0x70000
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_KIRKWOOD_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x0
CONFIG_LTO=y
CONFIG_SYS_LOAD_ADDR=0xc0700000
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run envboot; run mmcboot; "
CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
CONFIG_LTO=y
CONFIG_SYS_LOAD_ADDR=0xc0700000
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
CONFIG_LTO=y
CONFIG_SYS_LOAD_ADDR=0xc0700000
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run envboot; run mmcboot; "
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_CMD_FS_GENERIC=y
# CONFIG_DOS_PARTITION is not set
CONFIG_ENV_OVERWRITE=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_EFI_PARTITION=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_ENV_OVERWRITE=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_EFI_PARTITION=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_ENV_OVERWRITE=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_EFI_PARTITION=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_ENV_OVERWRITE=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_KWD_CONFIG="board/Marvell/db-xc3-24g4xg/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_MEMTEST_START=0x00800000
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x2000
+CONFIG_IDENT_STRING=" ##v01.06"
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
CONFIG_DMA_LPC32XX=y
+CONFIG_LPC32XX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_LPC32XX=y
CONFIG_BOOTP_DNS2=y
CONFIG_BOOTP_NTPSERVER=y
CONFIG_CMD_JFFS2=y
+CONFIG_JFFS2_DEV="nand0"
+CONFIG_JFFS2_PART_OFFSET=0x680000
+CONFIG_JFFS2_PART_SIZE=0xF980000
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs)"
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_CONS_INDEX=3
+CONFIG_JFFS2_NAND=y
CONFIG_OF_LIBFDT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
-CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_UNZIP=y
CONFIG_CMD_DFU=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
-CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="display5 > "
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_USB_HOST=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_SDP_SUPPORT=y
-CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="display5 factory > "
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/d-link/dns325/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=1
CONFIG_TARGET_DNS325=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_KIRKWOOD_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/Seagate/dockstar/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_DOCKSTAR=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/Marvell/dreamplug/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_DREAMPLUG=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_ENV_ADDR=0x100000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_INITRD_TAG=y
CONFIG_STATIC_MACH_TYPE=y
CONFIG_MACH_TYPE=527
+CONFIG_SYS_KWD_CONFIG="board/Synology/ds109/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_DS109=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_ENV_ADDR=0x3D0000
CONFIG_NETCONSOLE=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_OVERWRITE=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_ENV_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="phytium-durian"
# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_PCI_64BIT=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x90000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rv1108-elgin-r1"
CONFIG_ROCKCHIP_RV1108=y
-# CONFIG_DEBUG_UART_BOARD_INIT is not set
CONFIG_ROCKCHIP_BOOT_MODE_REG=0
CONFIG_TARGET_ELGIN_RV1108=y
+# CONFIG_DEBUG_UART_BOARD_INIT is not set
CONFIG_DEBUG_UART_BASE=0x10210000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=15000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_SOFT=y
CONFIG_SYS_I2C_SOFT_SLAVE=0
+CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
+CONFIG_JFFS2_NAND=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_SPL_SYS_THUMB_BUILD=y
CONFIG_ARCH_ASPEED=y
+CONFIG_SYS_TEXT_BASE=0x80000000
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x800
-CONFIG_SYS_TEXT_BASE=0x80000000
CONFIG_ASPEED_AST2600=y
CONFIG_TARGET_EVB_AST2600=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_WDT=y
-CONFIG_SHA512_ALGO=y
-CONFIG_SHA512=y
CONFIG_SHA384=y
CONFIG_HEXDUMP=y
# CONFIG_EFI_LOADER is not set
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_ROCKCHIP_OTP=y
+CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PHY_REALTEK=y
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_ARCH_TIMER=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x60000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_TPL_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x61000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_NR_DRAM_BANKS=2
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_DM_ETH=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_ROCKCHIP_OTP=y
+CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PHY_REALTEK=y
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_MEMTEST_START=0x0
CONFIG_ENV_SIZE=0x10000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g25-gardena-smart-gateway"
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_MEMTEST_START=0x0
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0xA0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x2000
+CONFIG_IDENT_STRING=" ##v01.07"
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/Seagate/goflexhome/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_GOFLEXHOME=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r7s72100-gr-peach-u-boot"
CONFIG_RZA1=y
+CONFIG_SYS_CLK_FREQ=66666666
CONFIG_SYS_LOAD_ADDR=0x20400000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
-CONFIG_ENV_SPI_BUS=0
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=0
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=50000000
-CONFIG_USE_ENV_SPI_MODE=y
-CONFIG_ENV_SPI_MODE=0x0
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_RZA1_GPIO=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_TFTP_TSIZE=y
CONFIG_AT91_GPIO=y
+CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/Marvell/guruplug/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_GURUPLUG=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x00110000
CONFIG_NR_DRAM_BANKS=2
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_TEGRA_NAND=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_PCI=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/raidsonic/ib62x0/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_IB62X0=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/iomega/iconnect/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_ICONNECT=y
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_IDS8313=y
-CONFIG_SYS_IMMR=0xF0000000
CONFIG_CORE_PLL_RATIO_2_1=y
CONFIG_PCI_HOST_MODE_ENABLE=y
CONFIG_BOOT_ROM_INTERFACE_GPCM_8BIT=y
# CONFIG_PCI is not set
CONFIG_RTC_PCF8563=y
CONFIG_SYS_NS16550=y
+CONFIG_WATCHDOG=y
+CONFIG_JFFS2_NAND=y
CONFIG_OF_LIBFDT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x0
CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y
CONFIG_SPL_DMA=y
CONFIG_SPL_MMC_TINY=y
# CONFIG_SPL_OF_PLATDATA_PARENT is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
-CONFIG_ENV_SPI_BUS=3
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=0
-CONFIG_USE_ENV_SPI_MAX_HZ=y
-CONFIG_ENV_SPI_MAX_HZ=40000000
-CONFIG_USE_ENV_SPI_MODE=y
-CONFIG_ENV_SPI_MODE=0x0
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=3
-CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x0
-CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-ctouch2.dtb"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_POWER=y
CONFIG_SYS_PROMPT="u-boot=> "
# CONFIG_CMD_EXPORTENV is not set
CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-edimm2.2.dtb"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_POWER=y
CONFIG_SYS_PROMPT="u-boot=> "
# CONFIG_CMD_EXPORTENV is not set
CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_PREBOOT="gsc wd-disable"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_HUSH_PARSER=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_HUSH_PARSER=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_CMD_FUSE=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SD_BOOT=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
CONFIG_SYS_LOAD_ADDR=0x80280000
+CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
CONFIG_SYS_LOAD_ADDR=0x80280000
+CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_FUSE=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/LaCie/netspace_v2/kwbimage-is2.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_IDENT_STRING=" IS v2"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
-CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=20000000
CONFIG_ENV_ADDR=0x70000
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_KIRKWOOD_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x0
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage_128M16_1.cfg"
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_ENV_SIZE=0x2000
CONFIG_NETCONSOLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_RAM=y
+CONFIG_KIRKWOOD_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_SOFT=y
CONFIG_SYS_I2C_SOFT_SLAVE=0x0
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_ENV_SIZE=0x2000
CONFIG_NETCONSOLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_RAM=y
+CONFIG_KIRKWOOD_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_SOFT=y
CONFIG_SYS_I2C_SOFT_SLAVE=0x0
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_KM_FPGA_CONFIG=y
CONFIG_NETCONSOLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_RAM=y
+CONFIG_KIRKWOOD_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_SOFT=y
CONFIG_SYS_I2C_SOFT_SLAVE=0x0
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="kmcent2"
CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020
+CONFIG_SYS_CLK_FREQ=66666666
CONFIG_MPC85xx=y
CONFIG_TARGET_KMCENT2=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_EADC_2=y
CONFIG_LCRR_CLKDIV_4=y
+CONFIG_83XX_PCICLK=0x3ef1480
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage_256M8_1.cfg"
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3
CONFIG_NETCONSOLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_RAM=y
+CONFIG_KIRKWOOD_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_SOFT=y
CONFIG_SYS_I2C_SOFT_SLAVE=0x0
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage_128M16_1.cfg"
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_KM_FPGA_CONFIG=y
CONFIG_NETCONSOLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_RAM=y
+CONFIG_KIRKWOOD_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_SOFT=y
CONFIG_SYS_I2C_SOFT_SLAVE=0x0
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
+CONFIG_83XX_PCICLK=0x3ef1480
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
+CONFIG_83XX_PCICLK=0x3ef1480
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage_128M16_1.cfg"
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_KM_FPGA_CONFIG=y
CONFIG_NETCONSOLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_RAM=y
+CONFIG_KIRKWOOD_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_SOFT=y
CONFIG_SYS_I2C_SOFT_SLAVE=0x0
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
+CONFIG_83XX_PCICLK=0x3ef1480
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
+CONFIG_83XX_PCICLK=0x3ef1480
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8A
CONFIG_SPL_USB_HOST=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_WATCHDOG=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=2
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="imx8mm-kontron-n801x-s imx8mm-kontron-n801x-s-lvds"
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
-CONFIG_ENV_SPI_BUS=0
-CONFIG_USE_ENV_SPI_MAX_HZ=y
-CONFIG_ENV_SPI_MAX_HZ=80000000
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_ARCH_TIMER=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="da850-lego-ev3"
CONFIG_SYS_LOAD_ADDR=0xc0700000
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=0
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds - press 'l' to stop...\n"
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_MESON_GXL=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
# CONFIG_MMC is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
# CONFIG_MMC is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=0
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=1000000
-CONFIG_USE_ENV_SPI_MODE=y
CONFIG_ENV_SPI_MODE=0x03
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SF_DEFAULT_SPEED=10000000
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SF_DEFAULT_SPEED=10000000
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=0
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=1000000
-CONFIG_USE_ENV_SPI_MODE=y
CONFIG_ENV_SPI_MODE=0x03
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SF_DEFAULT_SPEED=10000000
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_ESDHC=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
CONFIG_AHCI=y
CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_QSPI_BOOT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_GIGE=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_SYS_LOAD_ADDR=0x82000000
-CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT,SD_BOOT_QSPI"
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aiot/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg"
+CONFIG_SD_BOOT=y
+CONFIG_SD_BOOT_QSPI=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_GIGE=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_U_QE=y
CONFIG_SYS_QE_FW_ADDR=0xf40000
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND_BOOT"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg"
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg"
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT,SD_BOOT_QSPI"
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg"
CONFIG_SD_BOOT=y
+CONFIG_SD_BOOT_QSPI=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_FIXED=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_DSA=y
-CONFIG_SJA1105=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
+CONFIG_SJA1105=y
CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_SYS_EXTRA_OPTIONS="SPL_FSL_PBL"
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atsn/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg"
CONFIG_SD_BOOT=y
+CONFIG_SD_BOOT_QSPI=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_MISC_INIT_R=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_FIXED=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_DSA=y
-CONFIG_SJA1105=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
+CONFIG_SJA1105=y
CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT"
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atwr/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg"
+CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=0
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_DM=y
CONFIG_SPL_DM=y
# CONFIG_SPL_BLK is not set
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
# CONFIG_SPL_DM_I2C is not set
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_U_QE=y
CONFIG_SYS_QE_FW_ADDR=0x940000
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT"
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atwr/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg"
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT,SD_BOOT_QSPI"
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atwr/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg"
CONFIG_SD_BOOT=y
+CONFIG_SD_BOOT_QSPI=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_CMD_USB=y
CONFIG_CMD_WDT=y
CONFIG_CMD_CACHE=y
+CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
# CONFIG_DDR_SPD is not set
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_CMD_WDT=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
+CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_CMD_WDT=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
+CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_CMD_USB=y
CONFIG_CMD_WDT=y
CONFIG_CMD_CACHE=y
+CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
# CONFIG_DDR_SPD is not set
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_CMD_WDT=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
+CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
+CONFIG_VOL_MONITOR_INA220=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
+CONFIG_VOL_MONITOR_INA220=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
+CONFIG_VOL_MONITOR_INA220=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="NAND_BOOT"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg"
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
+CONFIG_VOL_MONITOR_INA220=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
+CONFIG_VOL_MONITOR_INA220=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
+CONFIG_VOL_MONITOR_INA220=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg"
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
+CONFIG_VOL_MONITOR_INA220=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT,SD_BOOT_QSPI"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg"
CONFIG_SD_BOOT=y
+CONFIG_SD_BOOT_QSPI=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
+CONFIG_VOL_MONITOR_INA220=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
+CONFIG_VOL_MONITOR_INA220=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=0
CONFIG_ENV_ADDR=0x60500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_DM=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_REALTEK=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_REALTEK=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_REALTEK=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT"
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043ardb/ls1043ardb_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg"
CONFIG_DM=y
CONFIG_SPL_DM=y
# CONFIG_SPL_BLK is not set
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT"
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043ardb/ls1043ardb_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_REALTEK=y
CONFIG_DM=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_REALTEK=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
# CONFIG_DDR_SPD is not set
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x52
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
+CONFIG_VOL_MONITOR_INA220=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
+CONFIG_VOL_MONITOR_INA220=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-lpuart"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
+CONFIG_VOL_MONITOR_INA220=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
+CONFIG_VOL_MONITOR_INA220=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046aqds/ls1046aqds_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg"
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
+CONFIG_VOL_MONITOR_INA220=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
+CONFIG_VOL_MONITOR_INA220=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046aqds/ls1046aqds_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg"
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
+CONFIG_VOL_MONITOR_INA220=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046aqds/ls1046aqds_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg"
CONFIG_SD_BOOT=y
+CONFIG_SD_BOOT_QSPI=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:2m(uboot),14m(free)"
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
+CONFIG_VOL_MONITOR_INA220=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
+CONFIG_VOL_MONITOR_INA220=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=0
CONFIG_ENV_ADDR=0x60500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
# CONFIG_SPL_BLK is not set
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
# CONFIG_SPL_DM_I2C is not set
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_SPL_VID=y
+CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
+CONFIG_VOL_MONITOR_LTC3882_READ=y
+CONFIG_VOL_MONITOR_LTC3882_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_SPL_VID=y
+CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
+CONFIG_VOL_MONITOR_LTC3882_READ=y
+CONFIG_VOL_MONITOR_LTC3882_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_SPL_VID=y
+CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
+CONFIG_VOL_MONITOR_LTC3882_READ=y
+CONFIG_VOL_MONITOR_LTC3882_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_SPL_VID=y
+CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
+CONFIG_VOL_MONITOR_LTC3882_READ=y
+CONFIG_VOL_MONITOR_LTC3882_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_SD_BOOT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_SPL_VID=y
+CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
+CONFIG_VOL_MONITOR_LTC3882_READ=y
+CONFIG_VOL_MONITOR_LTC3882_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI"
CONFIG_SD_BOOT=y
+CONFIG_SD_BOOT_QSPI=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_BOOTCOMMAND="mmcinfo;mmc read 0x80001000 0x6800 0x800; fsl_mc lazyapply dpl 0x80001000 && mmc read $kernel_load $kernel_start $kernel_size && bootm $kernel_load"
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_SPL_VID=y
+CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
+CONFIG_VOL_MONITOR_LTC3882_READ=y
+CONFIG_VOL_MONITOR_LTC3882_SET=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_SPL_VID=y
+CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
+CONFIG_VOL_MONITOR_LTC3882_READ=y
+CONFIG_VOL_MONITOR_LTC3882_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_MXC_I2C1_SPEED=40000000
CONFIG_SYS_MXC_I2C2_SPEED=40000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_SPL_VID=y
+CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
+CONFIG_VOL_MONITOR_LTC3882_READ=y
+CONFIG_VOL_MONITOR_LTC3882_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_MXC_I2C1_SPEED=40000000
CONFIG_SYS_MXC_I2C2_SPEED=40000000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_SPL_VID=y
+CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
+CONFIG_VOL_MONITOR_LTC3882_READ=y
+CONFIG_VOL_MONITOR_LTC3882_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI"
CONFIG_SD_BOOT=y
+CONFIG_SD_BOOT_QSPI=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_SPL_BLK is not set
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_MXC_I2C1_SPEED=40000000
CONFIG_SYS_MXC_I2C2_SPEED=40000000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_SPL_VID=y
+CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
+CONFIG_VOL_MONITOR_LTC3882_READ=y
+CONFIG_VOL_MONITOR_LTC3882_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI"
CONFIG_SD_BOOT=y
+CONFIG_SD_BOOT_QSPI=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_MXC_I2C1_SPEED=40000000
CONFIG_SYS_MXC_I2C2_SPEED=40000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_SPL_VID=y
+CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
+CONFIG_VOL_MONITOR_LTC3882_READ=y
+CONFIG_VOL_MONITOR_LTC3882_SET=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_SPL_VID=y
+CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
+CONFIG_VOL_MONITOR_LTC3882_READ=y
+CONFIG_VOL_MONITOR_LTC3882_SET=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_NXP_ESBC=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2081a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_AHCI=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PCI=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
+CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_AHCI=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x806c0000 0x6c0000 0x40000; env exists mcinitcmd && env exists secureboot && esbc_validate 0x806C0000; sf read 0x80d00000 0xd00000 0x100000; env exists mcinitcmd && fsl_mc lazyapply dpl 0x80d00000; run distro_bootcmd;run qspi_bootcmd; env exists secureboot && esbc_halt;"
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_AHCI=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/buffalo/lsxl/kwbimage-lschl.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_LSXL=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_KIRKWOOD_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/buffalo/lsxl/kwbimage-lsxhl.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_LSXL=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_KIRKWOOD_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_SPL_VID=y
+CONFIG_VID_FLS_ENV="lx2160aqds_vdd_mv"
+CONFIG_VOL_MONITOR_LTC3882_READ=y
+CONFIG_VOL_MONITOR_LTC3882_SET=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_SPL_VID=y
+CONFIG_VID_FLS_ENV="lx2160aqds_vdd_mv"
+CONFIG_VOL_MONITOR_LTC3882_READ=y
+CONFIG_VOL_MONITOR_LTC3882_SET=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_MUX=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_SPL_VID=y
+CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv"
+CONFIG_VOL_MONITOR_LTC3882_READ=y
+CONFIG_VOL_MONITOR_LTC3882_SET=y
CONFIG_EMC2305=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_MISC_INIT_R=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_SPL_VID=y
+CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv"
+CONFIG_VOL_MONITOR_LTC3882_READ=y
+CONFIG_VOL_MONITOR_LTC3882_SET=y
CONFIG_EMC2305=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_SPL_VID=y
+CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv"
+CONFIG_VOL_MONITOR_LTC3882_READ=y
+CONFIG_VOL_MONITOR_LTC3882_SET=y
CONFIG_EMC2305=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_SPL_VID=y
+CONFIG_VID_FLS_ENV="lx2162aqds_vdd_mv"
+CONFIG_VOL_MONITOR_LTC3882_READ=y
+CONFIG_VOL_MONITOR_LTC3882_SET=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_SPL_VID=y
+CONFIG_VID_FLS_ENV="lx2162aqds_vdd_mv"
+CONFIG_VOL_MONITOR_LTC3882_READ=y
+CONFIG_VOL_MONITOR_LTC3882_SET=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds"
CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_SPL_VID=y
+CONFIG_VID_FLS_ENV="lx2162aqds_vdd_mv"
+CONFIG_VOL_MONITOR_LTC3882_READ=y
+CONFIG_VOL_MONITOR_LTC3882_SET=y
CONFIG_FSPI_AHB_EN_4BYTE=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_ENV_OVERWRITE=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x00110000
CONFIG_NR_DRAM_BANKS=2
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPL_DM=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_TEGRA_NAND=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_CMD_PING=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=15000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
CONFIG_IMX_THERMAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
CONFIG_IMX_THERMAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
CONFIG_IMX_THERMAL=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/Seagate/nas220/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_NAS220=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
+CONFIG_KIRKWOOD_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_NAND=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/LaCie/net2big_v2/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_NET2BIG_V2=y
+CONFIG_NET2BIG_V2=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x70000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_IDENT_STRING=" 2Big v2"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
-CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=20000000
CONFIG_ENV_ADDR=0x70000
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_KIRKWOOD_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x0
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/LaCie/netspace_v2/kwbimage-ns2l.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_NETSPACE_V2=y
+CONFIG_NETSPACE_LITE_V2=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x70000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_IDENT_STRING=" NS v2 Lite"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
-CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=20000000
CONFIG_ENV_ADDR=0x70000
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_KIRKWOOD_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x0
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/LaCie/netspace_v2/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_NETSPACE_V2=y
+CONFIG_NETSPACE_MAX_V2=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x70000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_IDENT_STRING=" NS Max v2"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
-CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=20000000
CONFIG_ENV_ADDR=0x70000
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_KIRKWOOD_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x0
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/LaCie/netspace_v2/kwbimage-ns2l.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_NETSPACE_V2=y
+CONFIG_NETSPACE_MINI_V2=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x70000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_IDENT_STRING=" NS v2 Mini"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
-CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=20000000
CONFIG_ENV_ADDR=0x70000
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
CONFIG_BLK=y
+CONFIG_KIRKWOOD_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x0
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/LaCie/netspace_v2/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_NETSPACE_V2=y
+CONFIG_NETSPACE_V2=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x70000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_IDENT_STRING=" NS v2"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
-CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=20000000
CONFIG_ENV_ADDR=0x70000
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
+CONFIG_KIRKWOOD_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x0
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
# CONFIG_SYS_THUMB_BUILD is not set
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SUPPORT_PASSING_ATAGS=y
CONFIG_CMDLINE_TAG=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/zyxel/nsa310s/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_NSA310S=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x81000100
CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_SYS_LOAD_ADDR=0x4000000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
-CONFIG_ENV_SPI_BUS=0
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=0
-CONFIG_USE_ENV_SPI_MAX_HZ=y
-CONFIG_ENV_SPI_MAX_HZ=125000000
-CONFIG_USE_ENV_SPI_MODE=y
-CONFIG_ENV_SPI_MODE=0x0
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TFTP_TSIZE=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_OCTEONTX=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SF_DEFAULT_SPEED=125000000
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_LOAD_ADDR=0x4000000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
-CONFIG_ENV_SPI_BUS=0
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=0
-CONFIG_USE_ENV_SPI_MAX_HZ=y
-CONFIG_ENV_SPI_MAX_HZ=125000000
-CONFIG_USE_ENV_SPI_MODE=y
-CONFIG_ENV_SPI_MODE=0x0
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TFTP_TSIZE=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_OCTEONTX=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SF_DEFAULT_SPEED=125000000
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
-CONFIG_ENV_SPI_BUS=0
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=0
-CONFIG_USE_ENV_SPI_MAX_HZ=y
-CONFIG_ENV_SPI_MAX_HZ=16000000
-CONFIG_USE_ENV_SPI_MODE=y
-CONFIG_ENV_SPI_MODE=0x0
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TFTP_TSIZE=y
CONFIG_AHCI_PCI=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OCTEONTX=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SF_DEFAULT_SPEED=16000000
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
-CONFIG_ENV_SPI_BUS=0
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=0
-CONFIG_USE_ENV_SPI_MAX_HZ=y
-CONFIG_ENV_SPI_MAX_HZ=16000000
-CONFIG_USE_ENV_SPI_MODE=y
-CONFIG_ENV_SPI_MODE=0x0
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TFTP_TSIZE=y
CONFIG_AHCI_PCI=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OCTEONTX=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SF_DEFAULT_SPEED=16000000
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43e00000
CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0xc0700000
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run envboot; run mmcboot; "
CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/Marvell/openrd/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_OPENRD=y
CONFIG_IDENT_STRING="\nOpenRD-Base"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
-CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; ${x_bootcmd_usb}; bootm 0x6400000;"
CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/Marvell/openrd/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_OPENRD=y
+CONFIG_BOARD_IS_OPENRD_CLIENT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x80000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-client"
CONFIG_IDENT_STRING="\nOpenRD-Client"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
-CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; ${x_bootcmd_usb}; bootm 0x6400000;"
CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/Marvell/openrd/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_OPENRD=y
+CONFIG_BOARD_IS_OPENRD_ULTIMATE=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x80000
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-ultimate"
CONFIG_IDENT_STRING="\nOpenRD-Ultimate"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_LOAD_ADDR=0x800000
-CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; ${x_bootcmd_usb}; bootm 0x6400000;"
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80080000
CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80080000
CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80080000
CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80080000
CONFIG_NR_DRAM_BANKS=1026
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80080000
CONFIG_NR_DRAM_BANKS=1026
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80080000
CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_ENV_OVERWRITE=y
# CONFIG_ENV_IS_IN_MMC is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SPI_MAX_HZ=48000000
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x00110000
CONFIG_NR_DRAM_BANKS=2
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=1
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=1
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-expu1"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
+CONFIG_SYS_CLK_FREQ=66666666
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-seli8"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
+CONFIG_SYS_CLK_FREQ=66666666
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x51
-CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=3
-CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SF_DEFAULT_SPEED=80000000
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x51
-CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x00110000
CONFIG_NR_DRAM_BANKS=2
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPL_DM=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_TEGRA_NAND=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_JFFS2=y
+CONFIG_JFFS2_DEV="nand0"
+CONFIG_JFFS2_PART_SIZE=0x10000000
CONFIG_MTDIDS_DEFAULT="nor0=physmap-flash.0,nand0=nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=physmap-flash.0:256k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),-(rootfs);nand:-(nand)"
CONFIG_OF_CONTROL=y
CONFIG_DM_VIDEO=y
# CONFIG_VIDEO_BPP32 is not set
CONFIG_LCD=y
+CONFIG_JFFS2_NAND=y
CONFIG_AT91_GPIO=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
+CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_ETH=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/cloudengines/pogo_e02/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_POGO_E02=y
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_TEXT_BASE=0xf01000
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="qemu-ppce500"
+CONFIG_SYS_CLK_FREQ=33000000
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_QEMU_PPCE500=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DEFAULT_DEVICE_TREE="sh7751-r2dplus"
+CONFIG_SYS_CLK_FREQ=60000000
CONFIG_TARGET_R2DPLUS=y
CONFIG_SYS_LOAD_ADDR=0x8e000000
CONFIG_BOOTDELAY=-1
CONFIG_CFI_FLASH=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
+CONFIG_SYS_FLASH_CFI=y
CONFIG_RENESAS_RPC_HF=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_FALCON=y
+CONFIG_SYS_CLK_FREQ=16666666
# CONFIG_PSCI_RESET is not set
CONFIG_ARMV8_PSCI=y
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_CFI_FLASH=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
+CONFIG_SYS_FLASH_CFI=y
CONFIG_RENESAS_RPC_HF=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CFI_FLASH=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
+CONFIG_SYS_FLASH_CFI=y
CONFIG_RENESAS_RPC_HF=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_DM_ETH=y
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SYS_ARCH_TIMER=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_RAM=y
CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_ROCKCHIP_SERIAL=y
CONFIG_SYSRESET=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x44800000
CONFIG_SYS_MALLOC_LEN=0x5001000
CONFIG_MTD=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_MAX8998=y
+CONFIG_SOFT_SPI=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Samsung"
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
-CONFIG_ENV_SPI_BUS=0
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=0
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=50000000
-CONFIG_USE_ENV_SPI_MODE=y
-CONFIG_ENV_SPI_MODE=0x0
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
-CONFIG_ENV_SPI_BUS=0
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=0
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=50000000
-CONFIG_USE_ENV_SPI_MODE=y
-CONFIG_ENV_SPI_MODE=0x0
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
-CONFIG_ENV_SPI_BUS=2
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=0
-CONFIG_USE_ENV_SPI_MAX_HZ=y
-CONFIG_ENV_SPI_MAX_HZ=50000000
-CONFIG_USE_ENV_SPI_MODE=y
-CONFIG_ENV_SPI_MODE=0x0
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_AT91_MCK_BYPASS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
-# CONFIG_CMD_IMI is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
-CONFIG_ENV_SPI_BUS=2
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=0
-CONFIG_USE_ENV_SPI_MAX_HZ=y
-CONFIG_ENV_SPI_MAX_HZ=66000000
-CONFIG_USE_ENV_SPI_MODE=y
-CONFIG_ENV_SPI_MODE=0x0
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
-CONFIG_CMD_GPIO=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x00110000
CONFIG_NR_DRAM_BANKS=2
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_TEGRA_KEYBOARD=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_TEGRA_NAND=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_KIRKWOOD=y
+CONFIG_SYS_KWD_CONFIG="board/Marvell/sheevaplug/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_SHEEVAPLUG=y
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unleashed-a00.dtb"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
+CONFIG_SYS_PCI_64BIT=y
CONFIG_AHCI=y
CONFIG_TARGET_SIFIVE_UNMATCHED=y
CONFIG_ARCH_RV64I=y
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unmatched-a00.dtb"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_CMD_GPT_RENAME=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
-CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=1
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_SPL_CLK=y
-CONFIG_SPI_FLASH_ISSI=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x54
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=1
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_I2C_S3C24X0=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=1
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_I2C_S3C24X0=y
CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100"
CONFIG_TARGET_SMDKC100=y
CONFIG_IDENT_STRING=" for SMDKC100"
+CONFIG_SYS_CLK_FREQ=12000000
CONFIG_SYS_LOAD_ADDR=0x30000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x12c30000
CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_DEBUG_UART_S5P=y
CONFIG_IDENT_STRING=" for snow"
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=1
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_I2C_CROS_EC_LDO=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION is not set
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_SPI=y
CONFIG_SPI_MEM=y
CONFIG_DESIGNWARE_SPI=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
CONFIG_DESIGNWARE_WATCHDOG=y
CONFIG_WDT=y
# CONFIG_GZIP is not set
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MMC_DW=y
CONFIG_MTD=y
-CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="socrates"
+# CONFIG_SYS_PCI_64BIT is not set
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_SOCRATES=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=1
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_I2C_CROS_EC_LDO=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y
CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y
-# CONFIG_SCMI_AGENT_MAILBOX is not set
CONFIG_GPIO_HOG=y
CONFIG_DM_HWSPINLOCK=y
CONFIG_HWSPINLOCK_STM32=y
CONFIG_OF_LIST="stm32mp15xx-dhcom-pdk2 stm32mp15xx-dhcom-drc02 stm32mp15xx-dhcom-picoitx"
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
-CONFIG_ENV_SPI_BUS=0
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=0
-CONFIG_USE_ENV_SPI_MAX_HZ=y
-CONFIG_ENV_SPI_MAX_HZ=50000000
-CONFIG_USE_ENV_SPI_MODE=y
-CONFIG_ENV_SPI_MODE=0x0
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
-CONFIG_ENV_SPI_BUS=0
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=0
-CONFIG_USE_ENV_SPI_MAX_HZ=y
-CONFIG_ENV_SPI_MAX_HZ=50000000
-CONFIG_USE_ENV_SPI_MODE=y
-CONFIG_ENV_SPI_MODE=0x0
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y
CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y
-# CONFIG_SCMI_AGENT_MAILBOX is not set
CONFIG_GPIO_HOG=y
CONFIG_DM_HWSPINLOCK=y
CONFIG_HWSPINLOCK_STM32=y
CONFIG_MTDIDS_DEFAULT="nor0=spi-flash.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-flash.0:1m(u-boot),7m(kernel),-(rootfs)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_CS=y
CONFIG_ENV_SPI_CS=1
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_BUS=y
-CONFIG_ENV_SPI_BUS=0
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=0
CONFIG_PROT_UDP=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_SYS_VENDOR="opalkelly"
CONFIG_SYS_CONFIG_NAME="syzygy_hub"
CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_DM_GPIO=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x00110000
CONFIG_NR_DRAM_BANKS=2
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPL_DM=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_TEGRA_NAND=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_EFI_PARTITION=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_ENV_OVERWRITE=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x1E0000
+CONFIG_SYS_CLK_FREQ=27000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_SPL_GPIO=y
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SYS_ARCH_TIMER=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43e00000
CONFIG_SYS_MALLOC_LEN=0x5001000
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x63300000
CONFIG_SYS_MALLOC_LEN=0x5001000
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x00110000
CONFIG_NR_DRAM_BANKS=2
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=48000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM=y
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
+CONFIG_83XX_PCICLK=0x3ef1480
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_CMD_FS_UUID=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_ENV_OVERWRITE=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
-CONFIG_ENV_SPI_MAX_HZ=40000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_AHCI_PCI=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
-CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
+CONFIG_83XX_PCICLK=0x3ef1480
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=atmel_nand:16m(kernel)ro,120m(root1),-(root2)"
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=15000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
CONFIG_SYS_MALLOC_LEN=0x2500000
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x00110000
CONFIG_NR_DRAM_BANKS=2
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_ARM=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_TARGET_VEXPRESS_CA9X4=y
CONFIG_SYS_TEXT_BASE=0x60800000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_AT91_GPIO=y
CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_SMSC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MACB=y
CONFIG_ARM=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SYS_ARCH_TIMER=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_LPC32XX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_LPC32XX=y
CONFIG_TARGET_XENGUEST_ARM64=y
CONFIG_SYS_TEXT_BASE=0x40080000
CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="xenguest-arm64"
CONFIG_IDENT_STRING=" xenguest"
CONFIG_SYS_LOAD_ADDR=0x40000000
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_PROMPT="xenguest# "
# CONFIG_CMD_BDI is not set
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_ARM=y
CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_MTD=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc0"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x600
CONFIG_SPL=y
+CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
# CONFIG_CMD_ZYNQMP is not set
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_FIT=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc1"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x600
CONFIG_SPL=y
+CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
# CONFIG_CMD_ZYNQMP is not set
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_FIT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x80
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
+CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
# CONFIG_CMD_ZYNQMP is not set
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_FIT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x80
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
+CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
# CONFIG_CMD_ZYNQMP is not set
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_FIT=y
CONFIG_SPL=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
CONFIG_ZYNQMP_NO_DDR=y
+CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
# CONFIG_CMD_ZYNQMP is not set
# CONFIG_PSCI_RESET is not set
# CONFIG_EXPERT is not set
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-r5"
CONFIG_DEBUG_UART_BASE=0xff010000
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_CPU_FREQ_HZ=500000000
CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_BOOTSTAGE=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
CONFIG_CMD_FRU=y
CONFIG_ZYNQMP_USB=y
+CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_XTFPGA_KC705=y
CONFIG_SYS_LOAD_ADDR=0x02000000
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=10
CONFIG_AUTOBOOT_KEYED=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_ICACHE_OFF=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x100000
CONFIG_SYS_MALLOC_LEN=0x8000
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_ICACHE_OFF=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_SYS_MALLOC_LEN=0x1000
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_ICACHE_OFF=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_SYS_MALLOC_LEN=0x1000
+++ /dev/null
-Freescale system clock options
-
- - CONFIG_SYS_FSL_CLK
- Enable to call get_clocks() in board_init_f() for
- non-PPC platforms.
u8 clkin_div;
clkin_div = (get_spmr(im) & SPMR_CKID) >> SPMR_CKID_SHIFT;
- return CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
+ return get_board_sys_clk() / (1 + clkin_div);
}
/**
u8 spmf;
spmf = (get_spmr(im) & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
- return CONFIG_SYS_CLK_FREQ * spmf;
+ return get_board_sys_clk() * spmf;
}
/**
help
This driver supports CREG GPIOs on Synopsys HSDK SOC.
+config KIRKWOOD_GPIO
+ bool "Kirkwood GPIO driver"
+ help
+ This drdiver supports GPIOs on Kirkwood platforms
+
config LPC32XX_GPIO
bool "LPC32XX GPIO driver"
depends on DM
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_M68K
+#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
+#endif
+
#if !CONFIG_IS_ENABLED(DM_I2C)
static const struct fsl_i2c_base *i2c_base[4] = {
(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
config SYS_I2C_EEPROM_ADDR_OVERFLOW
hex "EEPROM Address Overflow"
- default 0
+ default 0x0
help
EEPROM chips that implement "address overflow" are ones
like Catalyst 24WC04/08/16 which has 9/10/11 bits of
Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
typically to reboot the board in error condition.
+config FSL_IFC
+ bool
+
endmenu
This option, if enabled, provides more flexible and linux-like
NAND initialization process.
-config SYS_NAND_DRIVER_ECC_LAYOUT
+config SPL_SYS_NAND_SELF_INIT
+ bool
+ depends on !SPL_NAND_SIMPLE
+ help
+ This option, if enabled, provides more flexible and linux-like
+ NAND initialization process, in SPL.
+
+config TPL_SYS_NAND_SELF_INIT
bool
+ depends on TPL_NAND_SUPPORT
+ help
+ This option, if enabled, provides more flexible and linux-like
+ NAND initialization process, in SPL.
+
+config SYS_NAND_DRIVER_ECC_LAYOUT
+ bool "Omit standard ECC layouts to save space"
help
- Omit standard ECC layouts to safe space. Select this if your driver
+ Omit standard ECC layouts to save space. Select this if your driver
is known to provide its own ECC layout.
config SYS_NAND_USE_FLASH_BBT
config NAND_ATMEL
bool "Support Atmel NAND controller"
+ select SYS_NAND_SELF_INIT
imply SYS_NAND_USE_FLASH_BBT
help
Enable this driver for NAND flash platforms using an Atmel NAND
config NAND_BRCMNAND
bool "Support Broadcom NAND controller"
depends on OF_CONTROL && DM && DM_MTD
+ select SYS_NAND_SELF_INIT
help
Enable the driver for NAND flash on platforms using a Broadcom NAND
controller.
config NAND_DAVINCI
bool "Support TI Davinci NAND controller"
+ select SYS_NAND_SELF_INIT if TARGET_DA850EVM
help
Enable this driver for NAND flash controllers available in TI Davinci
and Keystone2 platforms
config NAND_FSL_ELBC
bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver"
+ select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
+ select SPL_SYS_NAND_SELF_INIT
+ select SYS_NAND_SELF_INIT
depends on FSL_ELBC
help
Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.
config NAND_FSL_IFC
bool "Support Freescale Integrated Flash Controller NAND driver"
+ select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
+ select SPL_SYS_NAND_SELF_INIT
+ select SYS_NAND_SELF_INIT
+ select FSL_IFC
help
Enable the Freescale Integrated Flash Controller NAND driver.
config NAND_LPC32XX_MLC
bool "Support LPC32XX_MLC controller"
+ select SYS_NAND_SELF_INIT
help
Enable the LPC32XX MLC NAND controller.
select SYS_NAND_SELF_INIT
select SYS_NAND_U_BOOT_LOCATIONS
select SPL_NAND_SUPPORT
+ select SPL_SYS_NAND_SELF_INIT
imply CMD_NAND
---help---
Enable support for NAND. This option enables the standard and
config NAND_MXS
bool "MXS NAND support"
depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
+ select SPL_SYS_NAND_SELF_INIT
select SYS_NAND_SELF_INIT
imply CMD_NAND
select APBH_DMA
config NAND_ZYNQ
bool "Support for Zynq Nand controller"
+ select SPL_SYS_NAND_SELF_INIT
select SYS_NAND_SELF_INIT
select DM_MTD
imply CMD_NAND
NFC v800: RK3308, RV1108
NFC v900: PX30, RK3326
+config TEGRA_NAND
+ bool "Support for NAND controller on Tegra SoCs"
+ depends on ARCH_TEGRA
+ select SYS_NAND_SELF_INIT
+ imply CMD_NAND
+ help
+ Enables support for NAND Flash chips on Tegra SoCs platforms.
+
comment "Generic NAND options"
config SYS_NAND_BLOCK_SIZE
nand->dev_ready = nand_davinci_dev_ready;
}
-#ifdef CONFIG_SYS_NAND_SELF_INIT
+#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
static int davinci_nand_probe(struct udevice *dev)
{
struct nand_chip *nand = dev_get_priv(dev);
return 0;
}
-#ifndef CONFIG_SYS_NAND_SELF_INIT
+#if !CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
static void nand_init_chip(int i)
{
struct nand_chip *nand = &nand_chip[i];
return;
initialized = 1;
-#ifdef CONFIG_SYS_NAND_SELF_INIT
+#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
board_nand_init();
#else
int i;
config SF_DEFAULT_MODE
hex "SPI Flash default mode (see include/spi.h)"
depends on SPI_FLASH || DM_SPI_FLASH
- default 0
+ default 0x0
help
The default mode may be provided by the platform
to handle the common case when only a single serial
struct udevice *new;
/* speed and mode will be read from DT */
- ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS,
- CONFIG_ENV_SPI_CS, 0, 0, &new);
+ ret = spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS,
+ CONFIG_SF_DEFAULT_CS, 0, 0, &new);
ucode_flash = dev_get_uclass_priv(new);
#else
struct udevice *new;
/* speed and mode will be read from DT */
- ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+ ret = spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS,
0, 0, &new);
ucode_flash = dev_get_uclass_priv(new);
hex "PFE base address"
default 0x04000000
+config SYS_FSL_PFE_SPI_BUS
+ int "Value of SPI flash bus for PFE firmware"
+ default SF_DEFAULT_BUS
+
+config SYS_FSL_PFE_SPI_CS
+ int "Value of SPI flash chip select for PFE firmware"
+ default SF_DEFAULT_CS
+
+config SYS_FSL_PFE_SPI_MAX_HZ
+ int "Value of SPI flash max frequency for PFE firmware"
+ default SF_DEFAULT_SPEED
+
+config SYS_FSL_PFE_SPI_MODE
+ hex "Value of SPI flash work mode for PFE firmware"
+ default SF_DEFAULT_MODE
+
endif
if (!addr)
return -ENOMEM;
- ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS,
- CONFIG_ENV_SPI_CS,
- CONFIG_ENV_SPI_MAX_HZ,
- CONFIG_ENV_SPI_MODE,
+ ret = spi_flash_probe_bus_cs(CONFIG_SYS_FSL_PFE_SPI_BUS,
+ CONFIG_SYS_FSL_PFE_SPI_CS,
+ CONFIG_SYS_FSL_PFE_SPI_MAX_HZ,
+ CONFIG_SYS_FSL_PFE_SPI_MODE,
&new);
if (ret) {
printf("SF: failed to probe spi\n");
struct spi_flash *ucode_flash;
addr = malloc(CONFIG_CORTINA_FW_LENGTH);
- ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
- CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+ ucode_flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS,
+ CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);
if (!ucode_flash) {
puts("SF: probe for Cortina ucode failed\n");
} else {
struct spi_flash *ucode_flash;
addr = malloc(CONFIG_CORTINA_FW_LENGTH);
- ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
- CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+ ucode_flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS,
+ CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);
if (!ucode_flash) {
puts("SF: probe for Cortina ucode failed\n");
} else {
measure when porting a board to use driver model for PCI. Once the
board is fully supported, this option should be disabled.
+config SYS_PCI_64BIT
+ bool "Enable 64-bit PCI resources"
+ default y if PPC
+ help
+ Enable 64-bit PCI resource access.
+
config PCI_AARDVARK
bool "Enable Aardvark PCIe driver"
depends on DM_GPIO
obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o
obj-$(CONFIG_PCIE_ECAM_SYNQUACER) += pcie_ecam_synquacer.o
-obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
obj-$(CONFIG_PCI_MPC85XX) += pci_mpc85xx.o
obj-$(CONFIG_PCI_MSC01) += pci_msc01.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <env.h>
-#include <init.h>
-#include <log.h>
-#include <malloc.h>
-#include <asm/fsl_serdes.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
- *
- * Initialize controller and call the common driver/pci pci_hose_scan to
- * scan for bridges and devices.
- *
- * Hose fields which need to be pre-initialized by board specific code:
- * regions[]
- * first_busno
- *
- * Fields updated:
- * last_busno
- */
-
-#include <pci.h>
-#include <asm/io.h>
-#include <asm/fsl_pci.h>
-
-#define MAX_PCI_REGIONS 7
-
-#ifndef CONFIG_SYS_PCI_MEMORY_BUS
-#define CONFIG_SYS_PCI_MEMORY_BUS 0
-#endif
-
-#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0
-#endif
-
-#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
-#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
-#endif
-
-/* Setup one inbound ATMU window.
- *
- * We let the caller decide what the window size should be
- */
-static void set_inbound_window(volatile pit_t *pi,
- struct pci_region *r,
- u64 size)
-{
- u32 sz = (__ilog2_u64(size) - 1);
-#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
- u32 flag = 0;
-#else
- u32 flag = PIWAR_LOCAL;
-#endif
-
- flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
-
- out_be32(&pi->pitar, r->phys_start >> 12);
- out_be32(&pi->piwbar, r->bus_start >> 12);
-#ifdef CONFIG_SYS_PCI_64BIT
- out_be32(&pi->piwbear, r->bus_start >> 44);
-#else
- out_be32(&pi->piwbear, 0);
-#endif
- if (r->flags & PCI_REGION_PREFETCH)
- flag |= PIWAR_PF;
- out_be32(&pi->piwar, flag | sz);
-}
-
-int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;
-
- /* Reset hose to make sure its in a clean state */
- memset(hose, 0, sizeof(struct pci_controller));
-
- hose->regions = (struct pci_region *)
- calloc(1, MAX_PCI_REGIONS * sizeof(struct pci_region));
-
- pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- return fsl_is_pci_agent(hose);
-}
-
-static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
- u64 out_lo, u8 pcie_cap,
- volatile pit_t *pi)
-{
- struct pci_region *r = hose->regions + hose->region_count;
- u64 sz = min((u64)gd->ram_size, (1ull << 32));
-
- phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
- pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
- pci_size_t pci_sz;
-
- /* we have no space available for inbound memory mapping */
- if (bus_start > out_lo) {
- printf ("no space for inbound mapping of memory\n");
- return 0;
- }
-
- /* limit size */
- if ((bus_start + sz) > out_lo) {
- sz = out_lo - bus_start;
- debug ("limiting size to %llx\n", sz);
- }
-
- pci_sz = 1ull << __ilog2_u64(sz);
- /*
- * we can overlap inbound/outbound windows on PCI-E since RX & TX
- * links a separate
- */
- if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) {
- debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
- (u64)bus_start, (u64)phys_start, (u64)sz);
- pci_set_region(r, bus_start, phys_start, sz,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
- PCI_REGION_PREFETCH);
-
- /* if we aren't an exact power of two match, pci_sz is smaller
- * round it up to the next power of two. We report the actual
- * size to pci region tracking.
- */
- if (pci_sz != sz)
- sz = 2ull << __ilog2_u64(sz);
-
- set_inbound_window(pi--, r++, sz);
- sz = 0; /* make sure we dont set the R2 window */
- } else {
- debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
- (u64)bus_start, (u64)phys_start, (u64)pci_sz);
- pci_set_region(r, bus_start, phys_start, pci_sz,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
- PCI_REGION_PREFETCH);
- set_inbound_window(pi--, r++, pci_sz);
-
- sz -= pci_sz;
- bus_start += pci_sz;
- phys_start += pci_sz;
-
- pci_sz = 1ull << __ilog2_u64(sz);
- if (sz) {
- debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
- (u64)bus_start, (u64)phys_start, (u64)pci_sz);
- pci_set_region(r, bus_start, phys_start, pci_sz,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
- PCI_REGION_PREFETCH);
- set_inbound_window(pi--, r++, pci_sz);
- sz -= pci_sz;
- bus_start += pci_sz;
- phys_start += pci_sz;
- }
- }
-
-#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
- /*
- * On 64-bit capable systems, set up a mapping for all of DRAM
- * in high pci address space.
- */
- pci_sz = 1ull << __ilog2_u64(gd->ram_size);
- /* round up to the next largest power of two */
- if (gd->ram_size > pci_sz)
- pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
- debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
- (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
- (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
- (u64)pci_sz);
- pci_set_region(r,
- CONFIG_SYS_PCI64_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- pci_sz,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
- PCI_REGION_PREFETCH);
- set_inbound_window(pi--, r++, pci_sz);
-#else
- pci_sz = 1ull << __ilog2_u64(sz);
- if (sz) {
- debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
- (u64)bus_start, (u64)phys_start, (u64)pci_sz);
- pci_set_region(r, bus_start, phys_start, pci_sz,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
- PCI_REGION_PREFETCH);
- sz -= pci_sz;
- bus_start += pci_sz;
- phys_start += pci_sz;
- set_inbound_window(pi--, r++, pci_sz);
- }
-#endif
-
-#ifdef CONFIG_PHYS_64BIT
- if (sz && (((u64)gd->ram_size) < (1ull << 32)))
- printf("Was not able to map all of memory via "
- "inbound windows -- %lld remaining\n", sz);
-#endif
-
- hose->region_count = r - hose->regions;
-
- return 1;
-}
-
-#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
-static void fsl_pcie_boot_master(pit_t *pi)
-{
- /* configure inbound window for slave's u-boot image */
- debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
- "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
- (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
- (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
- CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
- struct pci_region r_inbound;
- u32 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)
- - 1;
- pci_set_region(&r_inbound,
- CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
- CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
- sz_inbound,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- set_inbound_window(pi--, &r_inbound,
- CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
-
- /* configure inbound window for slave's u-boot image */
- debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
- "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
- (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
- (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
- CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
- pci_set_region(&r_inbound,
- CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
- CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
- sz_inbound,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- set_inbound_window(pi--, &r_inbound,
- CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
-
- /* configure inbound window for slave's ucode and ENV */
- debug("PCIEBOOT - MASTER: Inbound window for slave's "
- "ucode and ENV; "
- "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
- (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
- (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
- CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
- sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)
- - 1;
- pci_set_region(&r_inbound,
- CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
- CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
- sz_inbound,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- set_inbound_window(pi--, &r_inbound,
- CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
-}
-
-static void fsl_pcie_boot_master_release_slave(int port)
-{
- unsigned long release_addr;
-
- /* now release slave's core 0 */
- switch (port) {
- case 1:
- release_addr = CONFIG_SYS_PCIE1_MEM_VIRT
- + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
- break;
-#ifdef CONFIG_SYS_PCIE2_MEM_VIRT
- case 2:
- release_addr = CONFIG_SYS_PCIE2_MEM_VIRT
- + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
- break;
-#endif
-#ifdef CONFIG_SYS_PCIE3_MEM_VIRT
- case 3:
- release_addr = CONFIG_SYS_PCIE3_MEM_VIRT
- + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
- break;
-#endif
- default:
- release_addr = 0;
- break;
- }
- if (release_addr != 0) {
- out_be32((void *)release_addr,
- CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
- debug("PCIEBOOT - MASTER: "
- "Release slave successfully! Now the slave should start up!\n");
- } else {
- debug("PCIEBOOT - MASTER: "
- "Release slave failed!\n");
- }
-}
-#endif
-
-void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
-{
- u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
- u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data;
- u16 temp16;
- u32 temp32;
- u32 block_rev;
- int enabled, r, inbound = 0;
- u16 ltssm;
- u8 temp8, pcie_cap;
- int pcie_cap_pos;
- int pci_dcr;
- int pci_dsr;
- int pci_lsr;
-
-#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
- int pci_lcr;
-#endif
-
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
- struct pci_region *reg = hose->regions + hose->region_count;
- pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
-
- /* Initialize ATMU registers based on hose regions and flags */
- volatile pot_t *po = &pci->pot[1]; /* skip 0 */
- volatile pit_t *pi;
-
- u64 out_hi = 0, out_lo = -1ULL;
- u32 pcicsrbar, pcicsrbar_sz;
-
- pci_setup_indirect(hose, cfg_addr, cfg_data);
-
-#ifdef PEX_CCB_DIV
- /* Configure the PCIE controller core clock ratio */
- pci_hose_write_config_dword(hose, dev, 0x440,
- ((gd->bus_clk / 1000000) *
- (16 / PEX_CCB_DIV)) / 333);
-#endif
- block_rev = in_be32(&pci->block_rev1);
- if (PEX_IP_BLK_REV_2_2 <= block_rev) {
- pi = &pci->pit[2]; /* 0xDC0 */
- } else {
- pi = &pci->pit[3]; /* 0xDE0 */
- }
-
- /* Handle setup of outbound windows first */
- for (r = 0; r < hose->region_count; r++) {
- unsigned long flags = hose->regions[r].flags;
- u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
-
- flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE;
- if (flags != PCI_REGION_SYS_MEMORY) {
- u64 start = hose->regions[r].bus_start;
- u64 end = start + hose->regions[r].size;
-
- out_be32(&po->powbar, hose->regions[r].phys_start >> 12);
- out_be32(&po->potar, start >> 12);
-#ifdef CONFIG_SYS_PCI_64BIT
- out_be32(&po->potear, start >> 44);
-#else
- out_be32(&po->potear, 0);
-#endif
- if (hose->regions[r].flags & PCI_REGION_IO) {
- out_be32(&po->powar, POWAR_EN | sz |
- POWAR_IO_READ | POWAR_IO_WRITE);
- } else {
- out_be32(&po->powar, POWAR_EN | sz |
- POWAR_MEM_READ | POWAR_MEM_WRITE);
- out_lo = min(start, out_lo);
- out_hi = max(end, out_hi);
- }
- po++;
- }
- }
- debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi);
-
- /* setup PCSRBAR/PEXCSRBAR */
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
- pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
- pcicsrbar_sz = ~pcicsrbar_sz + 1;
-
- if (out_hi < (0x100000000ull - pcicsrbar_sz) ||
- (out_lo > 0x100000000ull))
- pcicsrbar = 0x100000000ull - pcicsrbar_sz;
- else
- pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz;
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar);
-
- out_lo = min(out_lo, (u64)pcicsrbar);
-
- debug("PCICSRBAR @ 0x%x\n", pcicsrbar);
-
- pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS,
- pcicsrbar_sz, PCI_REGION_SYS_MEMORY);
- hose->region_count++;
-
- /* see if we are a PCIe or PCI controller */
- pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
- pci_dcr = pcie_cap_pos + 0x08;
- pci_dsr = pcie_cap_pos + 0x0a;
- pci_lsr = pcie_cap_pos + 0x12;
-
- pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
-
-#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
- /* boot from PCIE --master */
- char *s = env_get("bootmaster");
- char pcie[6];
- sprintf(pcie, "PCIE%d", pci_info->pci_num);
-
- if (s && (strcmp(s, pcie) == 0)) {
- debug("PCIEBOOT - MASTER: Master port [ %d ] for pcie boot.\n",
- pci_info->pci_num);
- fsl_pcie_boot_master((pit_t *)pi);
- } else {
- /* inbound */
- inbound = fsl_pci_setup_inbound_windows(hose,
- out_lo, pcie_cap, pi);
- }
-#else
- /* inbound */
- inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
-#endif
-
- for (r = 0; r < hose->region_count; r++)
- debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r,
- (u64)hose->regions[r].phys_start,
- (u64)hose->regions[r].bus_start,
- (u64)hose->regions[r].size,
- hose->regions[r].flags);
-
- pci_register_hose(hose);
- pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */
- hose->current_busno = hose->first_busno;
-
- out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */
- out_be32(&pci->peer, ~0x20140); /* Enable All Error Interrupts except
- * - Master abort (pci)
- * - Master PERR (pci)
- * - ICCA (PCIe)
- */
- pci_hose_read_config_dword(hose, dev, pci_dcr, &temp32);
- temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
- pci_hose_write_config_dword(hose, dev, pci_dcr, temp32);
-
-#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
- pci_lcr = pcie_cap_pos + 0x10;
- temp32 = 0;
- pci_hose_read_config_dword(hose, dev, pci_lcr, &temp32);
- temp32 &= ~0x03; /* Disable ASPM */
- pci_hose_write_config_dword(hose, dev, pci_lcr, temp32);
- udelay(1);
-#endif
- if (pcie_cap == PCI_CAP_ID_EXP) {
- if (block_rev >= PEX_IP_BLK_REV_3_0) {
-#define PEX_CSR0_LTSSM_MASK 0xFC
-#define PEX_CSR0_LTSSM_SHIFT 2
- ltssm = (in_be32(&pci->pex_csr0)
- & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
- enabled = (ltssm == 0x11) ? 1 : 0;
-#ifdef CONFIG_FSL_PCIE_RESET
- int i;
- /* assert PCIe reset */
- setbits_be32(&pci->pdb_stat, 0x08000000);
- (void) in_be32(&pci->pdb_stat);
- udelay(1000);
- /* clear PCIe reset */
- clrbits_be32(&pci->pdb_stat, 0x08000000);
- asm("sync;isync");
- for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
- pci_hose_read_config_word(hose, dev, PCI_LTSSM,
- <ssm);
- udelay(1000);
- }
-#endif
- } else {
- /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); */
- /* enabled = ltssm >= PCI_LTSSM_L0; */
- pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
- enabled = ltssm >= PCI_LTSSM_L0;
-
-#ifdef CONFIG_FSL_PCIE_RESET
- if (ltssm == 1) {
- int i;
- debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm);
- /* assert PCIe reset */
- setbits_be32(&pci->pdb_stat, 0x08000000);
- (void) in_be32(&pci->pdb_stat);
- udelay(100);
- debug(" Asserting PCIe reset @%p = %x\n",
- &pci->pdb_stat, in_be32(&pci->pdb_stat));
- /* clear PCIe reset */
- clrbits_be32(&pci->pdb_stat, 0x08000000);
- asm("sync;isync");
- for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
- pci_hose_read_config_word(hose, dev, PCI_LTSSM,
- <ssm);
- udelay(1000);
- debug("....PCIe link error. "
- "LTSSM=0x%02x.\n", ltssm);
- }
- enabled = ltssm >= PCI_LTSSM_L0;
-
- /* we need to re-write the bar0 since a reset will
- * clear it
- */
- pci_hose_write_config_dword(hose, dev,
- PCI_BASE_ADDRESS_0, pcicsrbar);
- }
-#endif
- }
-
-#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
- if (enabled == 0) {
- serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
- temp32 = in_be32(&srds_regs->srdspccr0);
-
- if ((temp32 >> 28) == 3) {
- int i;
-
- out_be32(&srds_regs->srdspccr0, 2 << 28);
- setbits_be32(&pci->pdb_stat, 0x08000000);
- in_be32(&pci->pdb_stat);
- udelay(100);
- clrbits_be32(&pci->pdb_stat, 0x08000000);
- asm("sync;isync");
- for (i=0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
- pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
- udelay(1000);
- }
- enabled = ltssm >= PCI_LTSSM_L0;
- }
- }
-#endif
- if (!enabled) {
- /* Let the user know there's no PCIe link for root
- * complex. for endpoint, the link may not setup, so
- * print undetermined.
- */
- if (fsl_is_pci_agent(hose))
- printf("undetermined, regs @ 0x%lx\n", pci_info->regs);
- else
- printf("no link, regs @ 0x%lx\n", pci_info->regs);
- hose->last_busno = hose->first_busno;
- return;
- }
-
- out_be32(&pci->pme_msg_det, 0xffffffff);
- out_be32(&pci->pme_msg_int_en, 0xffffffff);
-
- /* Print the negotiated PCIe link width */
- pci_hose_read_config_word(hose, dev, pci_lsr, &temp16);
- printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
- (temp16 & 0xf), pci_info->regs);
-
- hose->current_busno++; /* Start scan with secondary */
- pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
- }
-
-#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
- /* The Read-Only Write Enable bit defaults to 1 instead of 0.
- * Set to 0 to protect the read-only registers.
- */
- clrbits_be32(&pci->dbi_ro_wr_en, 0x01);
-#endif
-
- /* Use generic setup_device to initialize standard pci regs,
- * but do not allocate any windows since any BAR found (such
- * as PCSRBAR) is not in this cpu's memory space.
- */
- pciauto_setup_device(hose, dev, 0, hose->pci_mem,
- hose->pci_prefetch, hose->pci_io);
-
- if (inbound) {
- pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
- pci_hose_write_config_word(hose, dev, PCI_COMMAND,
- temp16 | PCI_COMMAND_MEMORY);
- }
-
-#ifndef CONFIG_PCI_NOSCAN
- if (!fsl_is_pci_agent(hose)) {
- debug(" Scanning PCI bus %02x\n",
- hose->current_busno);
- hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
- } else {
- debug(" Not scanning PCI bus %02x. PI=%x\n",
- hose->current_busno, temp8);
- hose->last_busno = hose->current_busno;
- }
-
- /* if we are PCIe - update limit regs and subordinate busno
- * for the virtual P2P bridge
- */
- if (pcie_cap == PCI_CAP_ID_EXP) {
- pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
- }
-#else
- hose->last_busno = hose->current_busno;
-#endif
-
- /* Clear all error indications */
- if (pcie_cap == PCI_CAP_ID_EXP)
- out_be32(&pci->pme_msg_det, 0xffffffff);
- out_be32(&pci->pedr, 0xffffffff);
-
- pci_hose_read_config_word(hose, dev, pci_dsr, &temp16);
- if (temp16) {
- pci_hose_write_config_word(hose, dev, pci_dsr, 0xffff);
- }
-
- pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
- if (temp16) {
- pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
- }
-}
-
-int fsl_is_pci_agent(struct pci_controller *hose)
-{
- int pcie_cap_pos;
- u8 pcie_cap;
- pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
-
- pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
- pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
- if (pcie_cap == PCI_CAP_ID_EXP) {
- u8 header_type;
-
- pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE,
- &header_type);
- return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
- } else {
- u8 prog_if;
-
- pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
- /* Programming Interface (PCI_CLASS_PROG)
- * 0 == pci host or pcie root-complex,
- * 1 == pci agent or pcie end-point
- */
- return (prog_if == FSL_PROG_IF_AGENT);
- }
-}
-
-int fsl_pci_init_port(struct fsl_pci_info *pci_info,
- struct pci_controller *hose, int busno)
-{
- volatile ccsr_fsl_pci_t *pci;
- struct pci_region *r;
- pci_dev_t dev = PCI_BDF(busno,0,0);
- int pcie_cap_pos;
- u8 pcie_cap;
-
- pci = (ccsr_fsl_pci_t *) pci_info->regs;
-
- /* on non-PCIe controllers we don't have pme_msg_det so this code
- * should do nothing since the read will return 0
- */
- if (in_be32(&pci->pme_msg_det)) {
- out_be32(&pci->pme_msg_det, 0xffffffff);
- debug (" with errors. Clearing. Now 0x%08x",
- pci->pme_msg_det);
- }
-
- r = hose->regions + hose->region_count;
-
- /* outbound memory */
- pci_set_region(r++,
- pci_info->mem_bus,
- pci_info->mem_phys,
- pci_info->mem_size,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- pci_info->io_bus,
- pci_info->io_phys,
- pci_info->io_size,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
- hose->first_busno = busno;
-
- fsl_pci_init(hose, pci_info);
-
- if (fsl_is_pci_agent(hose)) {
- fsl_pci_config_unlock(hose);
- hose->last_busno = hose->first_busno;
-#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
- } else {
- /* boot from PCIE --master releases slave's core 0 */
- char *s = env_get("bootmaster");
- char pcie[6];
- sprintf(pcie, "PCIE%d", pci_info->pci_num);
-
- if (s && (strcmp(s, pcie) == 0))
- fsl_pcie_boot_master_release_slave(pci_info->pci_num);
-#endif
- }
-
- pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
- pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
- printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
- "e" : "", pci_info->pci_num,
- hose->first_busno, hose->last_busno);
- return(hose->last_busno + 1);
-}
-
-/* Enable inbound PCI config cycles for agent/endpoint interface */
-void fsl_pci_config_unlock(struct pci_controller *hose)
-{
- pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
- int pcie_cap_pos;
- u8 pcie_cap;
- u16 pbfr;
-
- if (!fsl_is_pci_agent(hose))
- return;
-
- pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
- pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
- if (pcie_cap != 0x0) {
- ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr;
- u32 block_rev = in_be32(&pci->block_rev1);
- /* PCIe - set CFG_READY bit of Configuration Ready Register */
- if (block_rev >= PEX_IP_BLK_REV_3_0)
- setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY);
- else
- pci_hose_write_config_byte(hose, dev,
- FSL_PCIE_CFG_RDY, 0x1);
- } else {
- /* PCI - clear ACL bit of PBFR */
- pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
- pbfr &= ~0x20;
- pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
- }
-}
-
-#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \
- defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4)
-int fsl_configure_pcie(struct fsl_pci_info *info,
- struct pci_controller *hose,
- const char *connected, int busno)
-{
- int is_endpoint;
-
- set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
- set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
-
- is_endpoint = fsl_setup_hose(hose, info->regs);
- printf("PCIe%u: %s", info->pci_num,
- is_endpoint ? "Endpoint" : "Root Complex");
- if (connected)
- printf(" of %s", connected);
- puts(", ");
-
- return fsl_pci_init_port(info, hose, busno);
-}
-
-#if defined(CONFIG_FSL_CORENET)
-#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
- #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR3_PCIE1
- #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR3_PCIE2
- #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR3_PCIE3
- #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR3_PCIE4
-#else
- #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1
- #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2
- #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3
- #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4
-#endif
- #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
-#elif defined(CONFIG_MPC85xx)
- #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE
- #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2
- #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3
- #define _DEVDISR_PCIE4 0
- #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
-#elif defined(CONFIG_MPC86xx)
- #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1
- #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2
- #define _DEVDISR_PCIE3 0
- #define _DEVDISR_PCIE4 0
- #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
- (&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
-#else
-#error "No defines for DEVDISR_PCIE"
-#endif
-
-/* Implement a dummy function for those platforms w/o SERDES */
-static const char *__board_serdes_name(enum srds_prtcl device)
-{
- switch (device) {
-#ifdef CONFIG_SYS_PCIE1_NAME
- case PCIE1:
- return CONFIG_SYS_PCIE1_NAME;
-#endif
-#ifdef CONFIG_SYS_PCIE2_NAME
- case PCIE2:
- return CONFIG_SYS_PCIE2_NAME;
-#endif
-#ifdef CONFIG_SYS_PCIE3_NAME
- case PCIE3:
- return CONFIG_SYS_PCIE3_NAME;
-#endif
-#ifdef CONFIG_SYS_PCIE4_NAME
- case PCIE4:
- return CONFIG_SYS_PCIE4_NAME;
-#endif
- default:
- return NULL;
- }
-
- return NULL;
-}
-
-__attribute__((weak, alias("__board_serdes_name"))) const char *
-board_serdes_name(enum srds_prtcl device);
-
-static u32 devdisr_mask[] = {
- _DEVDISR_PCIE1,
- _DEVDISR_PCIE2,
- _DEVDISR_PCIE3,
- _DEVDISR_PCIE4,
-};
-
-int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
- struct fsl_pci_info *pci_info)
-{
- struct pci_controller *hose;
- int num = dev - PCIE1;
-
- hose = calloc(1, sizeof(struct pci_controller));
- if (!hose)
- return busno;
-
- if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) {
- busno = fsl_configure_pcie(pci_info, hose,
- board_serdes_name(dev), busno);
- } else {
- printf("PCIe%d: disabled\n", num + 1);
- }
-
- return busno;
-}
-
-int fsl_pcie_init_board(int busno)
-{
- struct fsl_pci_info pci_info;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
- u32 devdisr;
- u32 *addr;
-
-#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
- addr = &gur->devdisr3;
-#else
- addr = &gur->devdisr;
-#endif
- devdisr = in_be32(addr);
-
-#ifdef CONFIG_PCIE1
- SET_STD_PCIE_INFO(pci_info, 1);
- busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info);
-#else
- setbits_be32(addr, _DEVDISR_PCIE1); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE2
- SET_STD_PCIE_INFO(pci_info, 2);
- busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info);
-#else
- setbits_be32(addr, _DEVDISR_PCIE2); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE3
- SET_STD_PCIE_INFO(pci_info, 3);
- busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info);
-#else
- setbits_be32(addr, _DEVDISR_PCIE3); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE4
- SET_STD_PCIE_INFO(pci_info, 4);
- busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info);
-#else
- setbits_be32(addr, _DEVDISR_PCIE4); /* disable */
-#endif
-
- return busno;
-}
-#else
-int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
- struct fsl_pci_info *pci_info)
-{
- return busno;
-}
-
-int fsl_pcie_init_board(int busno)
-{
- return busno;
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-
-void ft_fsl_pci_setup(void *blob, const char *pci_compat,
- unsigned long ctrl_addr)
-{
- int off;
- u32 bus_range[2];
- phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr;
- struct pci_controller *hose;
-
- hose = find_hose_by_cfg_addr((void *)(ctrl_addr));
-
- /* convert ctrl_addr to true physical address */
- p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR;
- p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS;
-
- off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr);
-
- if (off < 0)
- return;
-
- /* We assume a cfg_addr not being set means we didn't setup the controller */
- if ((hose == NULL) || (hose->cfg_addr == NULL)) {
- fdt_del_node(blob, off);
- } else {
- bus_range[0] = 0;
- bus_range[1] = hose->last_busno - hose->first_busno;
- fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
- fdt_pci_dma_ranges(blob, off, hose);
- }
-}
-#endif
#define status_dcc(x) \
__asm__ volatile ("mrc p14, 0, %0, c14, c0, 0\n" : "=r" (x))
-#elif defined(CONFIG_CPU_ARMV8)
+#elif defined(CONFIG_ARM64)
/*
* ARMV8
*/
*/
#include <common.h>
+#include <clock_legacy.h>
#include <clk.h>
#include <dm.h>
#include <fsl_lpuart.h>
}
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 0
-#endif
-
u32 __weak get_lpuart_clk(void)
{
- return CONFIG_SYS_CLK_FREQ;
+ return get_board_sys_clk();
}
#if CONFIG_IS_ENABLED(CLK)
*/
#include <common.h>
+#include <clock_legacy.h>
#include <malloc.h>
#include <asm/global_data.h>
#include <asm/io.h>
clk_free(&clk);
#else
- uc_priv->clock_rate = CONFIG_SYS_CLK_FREQ / 2;
+ uc_priv->clock_rate = get_board_sys_clk() / 2;
#endif
readb(priv->regs + OSTM_CTL);
different sector sizes, and CONFIG_ENV_SECT_SIZE should be
set to that value.
-config USE_ENV_SPI_BUS
- bool "SPI flash bus for environment"
- depends on ENV_IS_IN_SPI_FLASH
- help
- Force the SPI bus for environment.
- If not defined, use CONFIG_SF_DEFAULT_BUS.
-
config ENV_SPI_BUS
int "Value of SPI flash bus for environment"
- depends on USE_ENV_SPI_BUS
- help
- Value the SPI bus and chip select for environment.
-
-config USE_ENV_SPI_CS
- bool "SPI flash chip select for environment"
depends on ENV_IS_IN_SPI_FLASH
+ default SF_DEFAULT_BUS
help
- Force the SPI chip select for environment.
- If not defined, use CONFIG_SF_DEFAULT_CS.
+ Value the SPI bus and chip select for environment.
config ENV_SPI_CS
int "Value of SPI flash chip select for environment"
- depends on USE_ENV_SPI_CS
- help
- Value of the SPI chip select for environment.
-
-config USE_ENV_SPI_MAX_HZ
- bool "SPI flash max frequency for environment"
depends on ENV_IS_IN_SPI_FLASH
+ default SF_DEFAULT_CS
help
- Force the SPI max work clock for environment.
- If not defined, use CONFIG_SF_DEFAULT_SPEED.
+ Value of the SPI chip select for environment.
config ENV_SPI_MAX_HZ
int "Value of SPI flash max frequency for environment"
- depends on USE_ENV_SPI_MAX_HZ
- help
- Value of the SPI max work clock for environment.
-
-config USE_ENV_SPI_MODE
- bool "SPI flash mode for environment"
depends on ENV_IS_IN_SPI_FLASH
+ default SF_DEFAULT_SPEED
help
- Force the SPI work mode for environment.
+ Value of the SPI max work clock for environment.
config ENV_SPI_MODE
hex "Value of SPI flash work mode for environment"
- depends on USE_ENV_SPI_MODE
+ depends on ENV_IS_IN_SPI_FLASH
+ default SF_DEFAULT_MODE
help
Value of the SPI work mode for environment.
See include/spi.h for value.
Flash File System version 2). JFFS2 is a log-structured file system
for use with flash memory devices. It supports raw NAND devices,
hard links and compression.
+
+config JFFS2_LZO
+ bool "Enable LZO compression in JFFS2"
+ depends on FS_JFFS2
+ help
+ Enable LZO compression in the JFFS2 filesystem
+
+config JFFS2_NAND
+ bool "Enable JFFS2 support for NAND flash"
+ depends on FS_JFFS2
+ help
+ Enable support for NAND flash as the backing store for JFFS2.
#define get_board_ddr_clk() CONFIG_DDR_CLK_FREQ
#endif
+/*
+ * If we have CONFIG_DYNAMIC_SYS_CLK_FREQ then there will be an
+ * implentation of get_board_sys_clk() somewhere. Otherwise we have
+ * a static value to use now.
+ */
+#ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ
+unsigned long get_board_sys_clk(void);
+#else
+#define get_board_sys_clk() CONFIG_SYS_CLK_FREQ
+#endif
+
#endif
*/
#define CONFIG_SYS_UART_PORT (0)
-#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000
#ifdef CONFIG_MCFFEC
#define CONFIG_MCFTMR
/* I2C */
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_UDP_CHECKSUM
#define CONFIG_SYS_UART_PORT (0)
-#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/*
#define CONFIG_MCFTMR
/* I2C */
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
#define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
#define CONFIG_SYS_UART_PORT (0)
-#undef CONFIG_WATCHDOG
-
#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
/*
#define CONFIG_SYS_UART_PORT (0)
-#undef CONFIG_WATCHDOG /* disable watchdog */
-
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
#define CONFIG_HOSTNAME "M5253DEMO"
/* I2C */
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
#define CONFIG_SYS_I2C_PINMUX_SET (0)
#define CONFIG_SYS_UART_PORT (0)
-#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
#endif
/* I2C */
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
#define CONFIG_SYS_I2C_PINMUX_SET (0x000F)
#define CONFIG_SYS_UART_PORT (0)
-#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000
#define CONFIG_SYS_UNIFY_CACHE
#define CONFIG_MCFTMR
/* I2C */
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_UDP_CHECKSUM
#define CONFIG_SYS_UART_PORT (0)
-#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
#define CONFIG_SYS_UNIFY_CACHE
#define CONFIG_MCFTMR
/* I2C */
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_UDP_CHECKSUM
# define CONFIG_SYS_NAND_SIZE 1
# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
# define NAND_ALLOW_ERASE_ALL 1
-# define CONFIG_JFFS2_NAND 1
-# define CONFIG_JFFS2_DEV "nand0"
-# define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1)
-# define CONFIG_JFFS2_PART_OFFSET 0x00000000
#endif
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#define CONFIG_SYS_UART_PORT (0)
-#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
#define CONFIG_SYS_UNIFY_CACHE
#define CONFIG_MCFTMR
/* I2C */
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_UDP_CHECKSUM
# define CONFIG_SYS_NAND_SIZE 1
# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
# define NAND_ALLOW_ERASE_ALL 1
-# define CONFIG_JFFS2_NAND 1
-# define CONFIG_JFFS2_DEV "nand0"
-# define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1)
-# define CONFIG_JFFS2_PART_OFFSET 0x00000000
#endif
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC_PIN_MUX
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
*/
#define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_NETDEV "eth1"
#define CONFIG_HAS_FEC 1 /* 8540 has FEC */
#endif
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-
/*
* sysclk for MPC85xx
*
* Note that PCI-X won't work at 33MHz.
*/
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 33000000
-#endif
-
/*
* These can be toggled for performance analysis, otherwise use default.
*/
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
/*
* Miscellaneous configurable options
*/
#define CONFIG_PCI1 /* PCI controller 1 */
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#undef CONFIG_PCI2
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#ifndef __ASSEMBLY__
#include <linux/stringify.h>
-extern unsigned long get_clock_freq(void);
#endif
-#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
/*
* Miscellaneous configurable options
*/
* assume U-Boot is less than 0.5MB
*/
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
/*
* in the README.mpc85xxads.
*/
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 33000000
-#endif
-
/*
* These can be toggled for performance analysis, otherwise use default.
*/
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
#else
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_NAND_INIT
#define CONFIG_SPL_COMMON_INIT_DDR
#define CONFIG_SPL_MAX_SIZE (128 << 10)
-#define CONFIG_TPL_TEXT_BASE 0xD0001000
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
#elif defined(CONFIG_SPL_BUILD)
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_NAND_MINIMAL
#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
#endif
#define CONFIG_SPL_PAD_TO 0x20000
#define CONFIG_TPL_PAD_TO 0x20000
#endif
#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE 0xD0001000
#elif defined(CONFIG_SPL_BUILD)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#endif
/* High Level Configuration Options */
-#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
#if defined(CONFIG_PCI)
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/*
* PCI Windows
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif
-#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */
-
#define CONFIG_HWCONFIG
/*
* These can be toggled for performance analysis, otherwise use default.
#if defined(CONFIG_HAS_FSL_DR_USB)
#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
#endif
#endif
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
|| defined(CONFIG_FSL_SATA)
#endif
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#endif
#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(unsigned long dummy);
#include <linux/stringify.h>
#endif
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
/*
* These can be toggled for performance analysis, otherwise use default.
#define CONFIG_HAS_FSL_MPH_USB
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
#ifndef _CONFIG_SBX81LIFKW_H
#define _CONFIG_SBX81LIFKW_H
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
-
/* additions for new ARM relocation support */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
-#define CONFIG_KIRKWOOD_GPIO 1
/*
* NS16550 Configuration
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */
#define CONFIG_PHY_BASE_ADR 0x01
#endif /* CONFIG_CMD_NET */
#ifndef _CONFIG_SBX81LIFXCAT_H
#define _CONFIG_SBX81LIFXCAT_H
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
-
/* additions for new ARM relocation support */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
-#define CONFIG_KIRKWOOD_GPIO 1
/*
* NS16550 Configuration
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */
#define CONFIG_PHY_BASE_ADR 0x01
#endif /* CONFIG_CMD_NET */
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ 100000000
-
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#ifdef CONFIG_PCI
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
#endif
#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_PCIE4 /* PCIE controller 4 */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
#if defined(CONFIG_SPIFLASH)
#elif defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_NXP_ESBC
#endif
#endif
-#define CONFIG_SYS_CLK_FREQ 100000000
-
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#ifdef CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
#endif
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
-#define CONFIG_U_QE
-
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-
/*
* Config the L3 Cache as L3 SRAM
*/
#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
-#define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv"
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_VID
-#endif
-#define CONFIG_VOL_MONITOR_IR36021_SET
-#define CONFIG_VOL_MONITOR_IR36021_READ
/* The lowest and highest voltage allowed for T208xQDS */
#define VDD_MV_MIN 819
#define VDD_MV_MAX 1212
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_PCIE4 /* PCIE controller 4 */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
* USB
*/
#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_HAS_FSL_DR_USB
#endif
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ 66660000
-
/*
* Config the L3 Cache as L3 SRAM
*/
#define I2C_MUX_CH_VOL_MONITOR 0xa
-#define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv"
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_VID
-#endif
-#define CONFIG_VOL_MONITOR_IR36021_SET
-#define CONFIG_VOL_MONITOR_IR36021_READ
/* The lowest and highest voltage allowed for T208xRDB */
#define VDD_MV_MIN 819
#define VDD_MV_MAX 1212
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_PCIE4 /* PCIE controller 4 */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
* USB
*/
#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_HAS_FSL_DR_USB
#endif
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/*
* These can be toggled for performance analysis, otherwise use default.
"setenv bootargs config-addr=0x60000000; " \
"bootm 0x01000000 - 0x00f00000"
-#define CONFIG_SYS_CLK_FREQ 66666666
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
/*
* DDR Setup
*/
#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
-#define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv"
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_VID
-#endif
-#define CONFIG_VOL_MONITOR_IR36021_SET
-#define CONFIG_VOL_MONITOR_IR36021_READ
/* The lowest and highest voltage allowed for T4240RDB */
#define VDD_MV_MIN 819
#define VDD_MV_MAX 1212
/*
* USB
*/
-#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_SKIP_TRUNOFF_WATCHDOG
-#define CONFIG_ARCH_MAP_SYSMEM
-
#define CONFIG_BOOTP_SERVERIP
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
/*
* Timer
*/
-#define CONFIG_SYS_CLK_FREQ 39062500
-#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
+#define VERSION_CLOCK get_board_sys_clk()
/*
* Use Externel CLOCK or PCLK
*/
#define CONFIG_USE_INTERRUPT
-#define CONFIG_ARCH_MAP_SYSMEM
-
#define CONFIG_BOOTP_SERVERIP
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*
* Timer
*/
-#define CONFIG_SYS_CLK_FREQ 39062500
-#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
+#define VERSION_CLOCK get_board_sys_clk()
/*
* Use Externel CLOCK or PCLK
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define RMOBILE_XTAL_CLK 20000000u
-#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
*/
#define CONFIG_SYS_NS16550_CLK 25000000
-#define CONFIG_ENV_SPI_MAX_HZ 25000000
-
/* Miscellaneous configurable options */
/*
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=PARTUUID=${uuid} rootwait " \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \
"\0" \
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
/* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */
#define CONFIG_SYS_FSL_USDHC_NUM 3
"mmcargs=setenv bootargs ${consoleargs} " \
"root=PARTUUID=${uuid} rootwait " \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"netargs=setenv bootargs ${consoleargs} " \
"root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \
"${vidargs}\0" \
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
/* On Apalis iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_USBD_HS
/* Framebuffer and LCD */
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IMX_HDMI
#define CONFIG_SYS_SDRAM_BASE 0x880000000
-#define CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE CONFIG_SYS_TEXT_BASE
-
/* Environment */
#define ENV_DEVICE_SETTINGS \
"stdin=serial,usbkbd\0" \
#define CONFIG_TMU_TIMER
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
-#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4)
+#define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 4)
/* STACK */
#define CONFIG_SYS_INIT_SP_ADDR 0xE8083000
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 50000000
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ get_board_sys_clk()
#endif /* __ARMADILLO_800EVA_H */
#define CONFIG_MCFTMR
/* I2C */
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
/*
* Defines processor clock - important for correct timings concerning serial
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 3355 /* timeout in milliseconds */
#endif
/* Access eMMC Boot_1 and Boot_2 partitions */
/* enable 64-bit PCI resources */
-#define CONFIG_SYS_PCI_64BIT 1
#define CONSOLE_ARGS "console_args=console=ttyS0,115200n8\0"
#define MAX_CPUS "max_cpus=maxcpus=8\0"
/*
* CONFIG_SYS_LOAD_ADDR - 1 MiB.
*/
-#define CONFIG_SYS_FDT_SAVE_ADDRESS 0x1f00000
#define CONFIG_SYS_CBSIZE 512
#define CONFIG_SYS_MAXARGS 32
*/
#define V_NS16550_CLK 81000000
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/*
* Flash configuration.
*/
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_MACRONIX
/*
* Filesystem configuration.
#endif
/* Board Clock */
-#define RMOBILE_XTAL_CLK 20000000u
-#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
/* ENV setting */
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_SELF_INIT
#endif /* CONFIG_MTD_RAW_NAND */
/*
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_SELF_INIT
#endif /* CONFIG_MTD_RAW_NAND */
/*
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_SELF_INIT
#endif /* CONFIG_MTD_RAW_NAND */
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_SELF_INIT
#endif /* CONFIG_MTD_RAW_NAND */
/*
#include <asm/arch/imx-regs.h>
#include "siemens-env-common.h"
-#include "siemens-ccp-common.h"
/* SPL config */
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
#define CONFIG_SPL_STACK 0x013E000
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define CONFIG_FACTORYSET
-#undef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "07")
-
#define CONFIG_REMAKE_ELF
/* ENET Config */
/* On CCP board, USDHC1 is for eMMC */
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* eMMC */
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
#define CONFIG_SPL_STACK 0x013E000
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define CONFIG_REMAKE_ELF
/* Flat Device Tree Definitions */
-#define CONFIG_OF_BOARD_SETUP
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
"boot_fdt=try\0" \
"fdt_file=imx8qm-cgt-qmx8.dtb\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_FSL_USDHC_NUM 3
"stdout=vidconsole,serial\0" \
"stderr=vidconsole,serial\0"
-#define CONFIG_TPL_TEXT_BASE 0xffff8000
-
#define CONFIG_SYS_NS16550_MEM32
#undef CONFIG_SYS_NS16550_PORT_MAPPED
"stdout=vidconsole,serial\0" \
"stderr=vidconsole,serial\0"
-#define CONFIG_TPL_TEXT_BASE 0xfffd8000
-
#endif /* __CONFIG_H */
#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */
-#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
/* Miscellaneous configuration options */
#define CONFIG_SYS_BOOTM_LEN (64 << 20)
#define CONFIG_SPL_START_S_PATH "arch/mips/mach-jz47xx"
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1c /* 14 KiB offset */
-
#endif /* __CONFIG_CI20_H__ */
"fdtaddr=0x83000000\0" \
"mmcdev_def="__stringify(CONFIG_SYS_MMC_DEV)"\0" \
"usbdev_def="__stringify(CONFIG_SYS_USB_DEV)"\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"usbpart=" __stringify(CONFIG_SYS_USB_IMG_LOAD_PART) "\0" \
"doboot=bootz ${loadaddr} - ${fdtaddr}\0" \
"mmc_config=mmc dev ${mmcdev}; mmc rescan\0" \
#include "mx6_common.h"
/* Machine config */
-#define CONFIG_SYS_LITTLE_ENDIAN
/* MMC */
#define CONFIG_SYS_FSL_USDHC_NUM 3
*/
#if 0
-#define CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
#endif
"mmcargs=setenv bootargs ${consoleargs} " \
"root=PARTUUID=${uuid} rootwait " \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"netargs=setenv bootargs ${consoleargs} " \
"root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \
"${vidargs}\0" \
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
/* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_USBD_HS
/* Framebuffer and LCD */
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IMX_HDMI
/*
* High Level Board Configuration Options
*/
-#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
/* Avoid overwriting factory configuration block */
#define CONFIG_BOARD_SIZE_LIMIT 0x40000
#define CONFIG_LCD_LOGO
/* NAND support */
-#define CONFIG_TEGRA_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define UBOOT_UPDATE \
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_FSL_CLK
-
#ifdef CONFIG_VIDEO_FSL_DCU_FB
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_SELF_INIT
#endif /* CONFIG_MTD_RAW_NAND */
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
-#define CONFIG_SYS_CLK_FREQ 33333333u
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#if defined(CONFIG_SPIFLASH)
#elif defined(CONFIG_SDCARD)
#define CONFIG_FSL_FIXED_MMC_LOCATION
#endif
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
-
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_HAS_FSL_MPH_USB
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
-#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
#endif
/* Ethernet */
*/
#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) /* 64 MB */
-#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
/* Environment in SPI NOR flash */
* SoC Configuration
*/
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
59, 60, 61, 62, 63 }
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 10
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_NAND_SELF_INIT
-#endif
#endif
/*
#ifndef _CONFIG_DB_XC3_24G4G_H
#define _CONFIG_DB_XC3_24G4G_H
-/*
- * High Level Configuration Options (easy to change)
- */
-
-#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
-
/* Environment in SPI NOR flash */
/* NAND */
#include "capricorn-common.h"
-#undef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "06")
-
/* DDR3 board total DDR is 2 GB */
#undef PHYS_SDRAM_1_SIZE
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
/*
* GPIO
*/
-#define CONFIG_LPC32XX_GPIO
/*
* Ethernet
/* TWL4030 */
-/* Board NAND Info */
-#define CONFIG_JFFS2_NAND
-/* nand device jffs2 lives on */
-#define CONFIG_JFFS2_DEV "nand0"
-/* start of jffs2 partition */
-#define CONFIG_JFFS2_PART_OFFSET 0x680000
-#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
- /* partition */
-
/* BOOTP/DHCP options */
#define CONFIG_BOOTP_NISDOMAIN
#define CONFIG_BOOTP_BOOTFILESIZE
#endif
#endif
-/* Watchdog */
-#if defined(CONFIG_SPL_BUILD)
-#undef CONFIG_WDT
-#undef CONFIG_WATCHDOG
-#define CONFIG_HW_WATCHDOG
-#endif
-
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=ttymxc0,115200\0" \
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* Watchdog */
-#if defined(CONFIG_SPL_BUILD)
-#undef CONFIG_WDT
-#undef CONFIG_WATCHDOG
-#define CONFIG_HW_WATCHDOG
-#endif
-
/* ENV config */
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
/* The 0x120000 value corresponds to above SPI-NOR memory MAP */
#ifndef _CONFIG_DNS325_H
#define _CONFIG_DNS325_H
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
-#define CONFIG_KW88F6281 /* SOC Name */
-
#include "mv-common.h"
/* Remove or override few declarations from mv-common.h */
/*
* Enable GPI0 support
*/
-#define CONFIG_KIRKWOOD_GPIO
/*
* Environment variables configurations
#ifndef _CONFIG_DOCKSTAR_H
#define _CONFIG_DOCKSTAR_H
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-#define CONFIG_KW88F6281 1 /* SOC Name */
-
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
#ifndef _CONFIG_DREAMPLUG_H
#define _CONFIG_DREAMPLUG_H
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
-
-#include "mv-plug-common.h"
+#include "mv-common.h"
/*
* Environment variables configurations
#ifndef _CONFIG_DS109_H
#define _CONFIG_DS109_H
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
-
-#include "mv-plug-common.h"
+#include "mv-common.h"
/*
* Environment variables configurations
#define CONFIG_SYS_INIT_SP_ADDR (0x88000000 - 0x100000)
/* PCI CONFIG */
-#define CONFIG_SYS_PCI_64BIT 1
#define CONFIG_PCI_SCAN_SHOW
/* SCSI */
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
-#define CONFIG_SYS_CLK_FREQ 33333333u
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
#define CONFIG_BOOT_RETRY_TIME -1
#define CONFIG_RESET_TO_RETRY
-#define CONFIG_HW_WATCHDOG
-
#define STATUS_LED_ACTIVE 0
/*----------------------------------------------------------------------*
* I2C
*/
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
-
#ifdef CONFIG_CMD_DATE
#define CONFIG_RTC_DS1338
#define CONFIG_I2C_RTC_ADDR 0x68
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 }
-#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_FEROCEON 1 /* CPU Core subversion */
-#define CONFIG_88F5182 1 /* SOC Name */
-
#include <asm/arch/orion5x.h>
/*
* CLKs configurations
*/
/* nedded by compliance test in read mode */
-#if defined(CONFIG_SPL_CMT)
-#define CONFIG_SYS_DCACHE_OFF
-#endif
/* Define own nand partitions */
#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE)
#endif
/* JFFS2 */
-#ifdef CONFIG_CMD_JFFS2
-#define CONFIG_JFFS2_NAND
-#endif
/* Ethernet */
#define CONFIG_NET_RETRY_COUNT 20
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_ATMEL_MCI
#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
#endif
#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
-/* Memory Info */
-#define CONFIG_SYS_LOAD_ADDR 0x83000000
-
/* Misc */
#define CONFIG_EXTRA_ENV_SETTINGS \
""
#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
-/* Memory Info */
-#define CONFIG_SYS_LOAD_ADDR 0x83000000
-
/* Misc */
#define STR_HELPER(s) #s
#define STR(s) STR_HELPER(s)
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
-#define CONFIG_SUPPORT_EMMC_RPMB
-
#endif
#include <configs/rk3308_common.h>
-#define CONFIG_SUPPORT_EMMC_RPMB
-
#define ROCKCHIP_DEVICE_SETTINGS \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#include <configs/rk3568_common.h>
-#define CONFIG_SUPPORT_EMMC_RPMB
-
#define ROCKCHIP_DEVICE_SETTINGS \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
/* Keep L2 Cache Disabled */
/* input clock of PLL: 24MHz input clock */
-#define CONFIG_SYS_CLK_FREQ 24000000
-#define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ
+#define COUNTER_FREQUENCY 24000000
/* select serial console configuration */
#define PHYS_SDRAM_12 (CONFIG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_12_SIZE SDRAM_BANK_SIZE
-#define CONFIG_DEBUG_UART_CLOCK 132710400
-
-#define CONFIG_PREBOOT \
-"echo Read pressed buttons status;" \
-"KEY_VOLUMEUP=gpa20;" \
-"KEY_HOME=gpa17;" \
-"KEY_VOLUMEDOWN=gpa21;" \
-"KEY_POWER=gpa00;" \
-"PRESSED=0;" \
-"RELEASED=1;" \
-"if gpio input $KEY_VOLUMEUP; then setenv VOLUME_UP $PRESSED; " \
-"else setenv VOLUME_UP $RELEASED; fi;" \
-"if gpio input $KEY_VOLUMEDOWN; then setenv VOLUME_DOWN $PRESSED; " \
-"else setenv VOLUME_DOWN $RELEASED; fi;" \
-"if gpio input $KEY_HOME; then setenv HOME $PRESSED; else setenv HOME $RELEASED; fi;" \
-"if gpio input $KEY_POWER; then setenv POWER $PRESSED; else setenv POWER $RELEASED; fi;"
-
#ifndef MEM_LAYOUT_ENV_SETTINGS
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
/* Board Clock */
/* XTAL_CLK : 16.66MHz */
-#define CONFIG_SYS_CLK_FREQ 16666666u
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
#include <configs/rk3308_common.h>
-#define CONFIG_SUPPORT_EMMC_RPMB
-
#define ROCKCHIP_DEVICE_SETTINGS \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#include "capricorn-common.h"
-#undef CONFIG_IDENT_STRING
-#define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "07")
-
/* DDR3 board total DDR is 1 GB */
#undef PHYS_SDRAM_1_SIZE
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */
#ifndef _CONFIG_GOFLEXHOME_H
#define _CONFIG_GOFLEXHOME_H
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-#define CONFIG_KW88F6281 1 /* SOC Name */
-
/*
* Default GPIO configuration and LED status
*/
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define RMOBILE_XTAL_CLK 20000000u
-#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
#define __GRPEACH_H
/* Board Clock , P1 clock frequency (XTAL=13.33MHz) */
-#define CONFIG_SYS_CLK_FREQ 66666666
/* Miscellaneous */
#define CONFIG_SYS_PBSIZE 256
#ifndef _CONFIG_GURUPLUG_H
#define _CONFIG_GURUPLUG_H
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
-
-/*
- * Standard filesystems
- */
-
-/*
- * mv-plug-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-plug-common.h"
+#include "mv-common.h"
/*
* Environment variables configurations
#endif
/* NAND support */
-#define CONFIG_TEGRA_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Environment in NAND (which is 512M), aligned to start of last sector */
#ifndef _CONFIG_IB62x0_H
#define _CONFIG_IB62x0_H
-/*
- * High level configuration options
- */
-#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
-#define CONFIG_KW88F6281 /* SOC Name */
-
#include "mv-common.h"
/*
#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
#endif /* CONFIG_IDE */
-/*
- * RTC driver configuration
- */
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_MV
-#endif /* CONFIG_CMD_DATE */
-
#endif /* _CONFIG_IB62x0_H */
#ifndef _CONFIG_ICONNECT_H
#define _CONFIG_ICONNECT_H
-/*
- * High level configuration options
- */
-#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
-#define CONFIG_KW88F6281 /* SOC Name */
-
#include "mv-common.h"
/*
/*
* HW-Watchdog
*/
-#define CONFIG_WATCHDOG 1
#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
/*
#define CONFIG_TIMESTAMP
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
-#define CONFIG_JFFS2_NAND
-#define CONFIG_JFFS2_DEV "0"
-
/* mtdparts command line support */
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0xd8000000
-#define CONFIG_JFFS2_NAND
#define CONFIG_MXC_NAND_HWECC
/*
"fdt_file=imx7-cm.dtb\0" \
"fdt_addr=0x83000000\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
/* USB Configs */
#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
"initrd_addr=0x43800000\0" \
"bootm_size=0x10000000\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"initrd_addr=0x43800000\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate}" \
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
-
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
/* Monitor Command Prompt */
/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
/* FEC*/
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M)
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
"fdtfile=imx8mm-evk.dtb\0" \
"initrd_addr=0x43800000\0" \
"bootm_size=0x10000000\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
/* Link Definitions */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
# define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif /* CONFIG_SPL_BUILD */
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
-
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 2) \
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
#define CONFIG_SYS_BOOTM_LEN SZ_256M
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
-#define CONFIG_SYS_MEMTEST_END \
- (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
-
/* UART */
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#endif /* __IMX8MM_ICORE_MX8MM_H */
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
/* FEC */
#define CONFIG_ETHPRIME "eth0"
#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"initrd_addr=0x43800000\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console} " \
/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
/* ENET Config */
#if defined(CONFIG_FEC_MXC)
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
"initrd_addr=0x43800000\0" \
"bootm_size=0x10000000\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
/* Link Definitions */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
#endif
#define CONFIG_SPL_MAX_SIZE (152 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
"initrd_addr=0x43800000\0" \
"bootm_size=0x10000000\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
/* Link Definitions */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
#endif
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_STACK 0x187FF0
"fdt_file=imx8mq-cm.dtb\0" \
"initrd_addr=0x43800000\0" \
"bootm_size=0x10000000\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
/* Link Definitions */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
#endif
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
"fdt_file=imx8mq-evk.dtb\0" \
"initrd_addr=0x43800000\0" \
"bootm_size=0x10000000\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
/* Link Definitions */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
-#define CONFIG_MXC_GPIO
-
-#define CONFIG_OF_SYSTEM_SETUP
-
#endif
#define CONFIG_SPL_MAX_SIZE (172 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
"initrd_addr=0x43800000\0" \
"initrd_high=0xffffffffffffffff\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
- (PHYS_SDRAM_SIZE >> 1))
-
#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
/* Monitor Command Prompt */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
-#define CONFIG_MXC_GPIO
-
-#define CONFIG_OF_SYSTEM_SETUP
-
#endif
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
#define CONFIG_SPL_STACK 0x013E000
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define CONFIG_REMAKE_ELF
-/* Flat Device Tree Definitions */
-#define CONFIG_OF_BOARD_SETUP
-
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
"initrd_addr=0x83800000\0" \
"initrd_high=0xffffffffffffffff\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
/* Default environment is in SD */
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_FSL_USDHC_NUM 2
"fdt_file=imx8qm-rom7720-a1.dtb\0" \
"initrd_addr=0x83800000\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
-/* Default environment is in SD */
-
-#ifdef CONFIG_QSPI_BOOT
-#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
-#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
-#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
-#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
-#endif
-
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board,
* USDHC3 is for SD on base board On DDR4 board, USDHC1 is mux for NAND,
* USDHC2 is for SD, USDHC3 is for SD on base board
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
#define CONFIG_SPL_STACK 0x013E000
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define CONFIG_REMAKE_ELF
-/* Flat Device Tree Definitions */
-#define CONFIG_OF_BOARD_SETUP
-
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
"initrd_addr=0x83800000\0" \
"initrd_high=0xffffffffffffffff\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot}\0 " \
/* Default environment is in SD */
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_BOOTM_LEN (SZ_64M)
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
"fdtfile=imx8ulp-evk.dtb\0" \
"initrd_addr=0x83800000\0" \
"bootm_size=0x10000000\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR 0x20240000
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
#define PHYS_SDRAM 0x80000000
#define CONFIG_SYS_INIT_SP_ADDR 0x20280000
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
#define PHYS_SDRAM 0x80000000
#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
-/*
- * System Clock Setup
- */
-#define CONFIG_SYS_CLK_FREQ 66000000
-#define CONFIG_83XX_PCICLK 66000000
-
/* QE microcode/firmware address */
/* between the u-boot partition and env */
-/*
- * High Level Configuration Options
- */
-#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */
-
-/*
- * System Clock Setup
- */
-#define CONFIG_SYS_CLK_FREQ 66000000
-#define CONFIG_83XX_PCICLK 66000000
-
/*
* System IO Config
*/
#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
-
-/* EEprom support */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#ifndef _CONFIG_KM_ARM_H
#define _CONFIG_KM_ARM_H
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
-#define CONFIG_KW88F6281 /* SOC Name */
-
#define CONFIG_NAND_ECC_BCH
/* include common defines/options for all Keymile boards */
#undef CONFIG_I2C_MVTWSI
#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */
#define CONFIG_SYS_NUM_I2C_BUSES 6
#define CONFIG_SYS_I2C_MAX_HOPS 1
#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
#ifndef __CONFIG_PG_WCOM_LS102XA_H
#define __CONFIG_PG_WCOM_LS102XA_H
-#define CONFIG_SYS_FSL_CLK
-
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
CONFIG_KM_PHRAM + \
CONFIG_KM_RESERVED_PRAM) >> 10)
-#define CONFIG_SYS_CLK_FREQ 66666666
-
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
* IFC Definitions
*/
/* NOR Flash Definitions */
-#define CONFIG_FSL_IFC
#define CONFIG_SYS_FLASH_BASE 0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
/* KM_KIRKWOOD_128M16 */
#elif defined(CONFIG_KM_KIRKWOOD_128M16)
#define CONFIG_HOSTNAME "km_kirkwood_128m16"
-#undef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
#define CONFIG_KM_DISABLE_PCIE
/* KM_NUSA */
#define CONFIG_HOSTNAME "kmnusa"
-#undef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
-
/* KMCOGE5UN */
#elif defined(CONFIG_KM_COGE5UN)
-#undef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
#define CONFIG_HOSTNAME "kmcoge5un"
#define CONFIG_KM_DISABLE_PCIE
/* KM_SUSE2 */
#elif defined(CONFIG_KM_SUSE2)
#define CONFIG_HOSTNAME "kmsuse2"
-#undef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
#else
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/* Environment in parallel NOR-Flash */
#define CONFIG_ENV_TOTAL_SIZE 0x040000
#define ENV_DEL_ADDR 0xebf00000 /*direct for newenv*/
-#define CONFIG_SYS_CLK_FREQ 66666666
-
/*
* These can be toggled for performance analysis, otherwise use default.
*/
* Retain non-DM serial port for debug purposes.
*/
#if !defined(CONFIG_DM_SERIAL)
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
#include "km/km-mpc83xx.h"
#include "km/km-mpc8360.h"
-/*
- * System Clock Setup
- */
-#define CONFIG_SYS_CLK_FREQ 66000000
-#define CONFIG_83XX_PCICLK 66000000
-
/**
* KMCOGE5NE has 512 MB RAM
*/
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define RMOBILE_XTAL_CLK 20000000u
-#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
#ifdef CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
/* early stack pointer */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xeff0)
-/* memtest command */
-#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END 0x9fffffff
-
/* SMP */
#define CPU_RELEASE_ADDR secondary_boot_addr
/* serial port */
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
+#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
/* ethernet */
#define CONFIG_SYS_RX_ETH_BUFFER 8
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_FSL_CLK
-
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
/* Clock */
#define CONFIG_GLOBAL_TIMER
-#define CONFIG_SYS_CLK_FREQ (48000000)
#define CONFIG_SYS_CPU_CLK (1196000000)
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ get_board_sys_clk()
#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
#define CONFIG_NFS_TIMEOUT 10000UL
#ifndef _CONFIG_LACIE_KW_H
#define _CONFIG_LACIE_KW_H
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
-/* SoC name */
-#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
-#define CONFIG_KW88F6192
-#else
-#define CONFIG_KW88F6281
-#endif
-
-/*
- * SDRAM configuration
- */
-
-/*
- * Different SDRAM configuration and size for some of the boards derived
- * from the Network Space v2
- */
-#if defined(CONFIG_INETSPACE_V2)
-#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-is2.cfg
-#elif defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
-#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-ns2l.cfg
-#endif
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
#include "mv-common.h"
/* Remove or override few declarations from mv-common.h */
/*
* Enable GPI0 support
*/
-#define CONFIG_KIRKWOOD_GPIO
/*
* Enable I2C support
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define RMOBILE_XTAL_CLK 20000000u
-#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
* SoC Configuration
*/
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#endif
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
/* SATA */
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
#include <asm/arch/stream_id_lsch2.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_CLK_FREQ 125000000
-
#ifdef CONFIG_TFABOOT
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
#else
/* I2C */
/* GPIO */
-#ifdef CONFIG_DM_GPIO
-#ifndef CONFIG_MPC8XXX_GPIO
-#define CONFIG_MPC8XXX_GPIO
-#endif
-#endif
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#include "ls1012a_common.h"
-#undef CONFIG_SYS_BOARD
-#define CONFIG_SYS_BOARD "ls1012afrwy"
-
/* Board Rev*/
#define BOARD_REV_A_B 0x0
#define BOARD_REV_C 0x00080000
DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
DSPI_CTAR_DT(0))
-#define CONFIG_SPI_FLASH_SST /* cs1 */
#define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
DSPI_CTAR_DT(0))
-#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
#define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
DSPI_CTAR_DT(0))
-#define CONFIG_SPI_FLASH_EON /* cs3 */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
-#define CONFIG_SYS_FSL_CLK
-
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
-#define CONFIG_SYS_CLK_FREQ 100000000
-
/*
* DDR: 800 MHz ( 1600 MT/s data rate )
*/
#define SDRAM_CFG_BI 0x00000001
#ifdef CONFIG_SD_BOOT
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
-
#define CONFIG_SPL_MAX_SIZE 0x1a000
#define CONFIG_SPL_STACK 0x1001d000
#define CONFIG_SPL_PAD_TO 0x1c000
CONFIG_SYS_SCSI_MAX_LUN)
/* SPI */
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SPI_FLASH_SPANSION
-#endif
/*
* eTSEC
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#endif
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
#include <asm/fsl_secure_boot.h>
#endif
#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
-#define CONFIG_SYS_FSL_CLK
-
#define CONFIG_DEEP_SLEEP
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_QIXIS_I2C_ACCESS
-#else
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#endif
#ifdef CONFIG_SD_BOOT
* IFC Definitions
*/
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_FSL_IFC
#define CONFIG_SYS_FLASH_BASE 0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
*/
/* GPIO */
-#ifdef CONFIG_DM_GPIO
-#ifndef CONFIG_MPC8XXX_GPIO
-#define CONFIG_MPC8XXX_GPIO
-#endif
-#endif
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
-#define CONFIG_SYS_FSL_CLK
-
#define CONFIG_DEEP_SLEEP
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
/* XHCI Support - enabled by default */
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_CLK_FREQ 100000000
-
#define DDR_SDRAM_CFG 0x470c0008
#define DDR_CS0_BNDS 0x008000bf
#define DDR_CS0_CONFIG 0x80014302
#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
#endif
-#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
-#define CONFIG_SYS_FSL_CLK
-
#define CONFIG_DEEP_SLEEP
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
-#define CONFIG_SYS_CLK_FREQ 100000000
-
#define DDR_SDRAM_CFG 0x470c0008
#define DDR_CS0_BNDS 0x008000bf
#define DDR_CS0_CONFIG 0x80014302
* IFC Definitions
*/
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_FSL_IFC
#define CONFIG_SYS_FLASH_BASE 0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
*/
/* GPIO */
-#ifdef CONFIG_DM_GPIO
-#ifndef CONFIG_MPC8XXX_GPIO
-#define CONFIG_MPC8XXX_GPIO
-#endif
-#endif
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define __L1028A_COMMON_H
#define CONFIG_REMAKE_ELF
-#define CONFIG_MP
#include <asm/arch/stream_id_lsch3.h>
#include <asm/arch/config.h>
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
/* GPIO */
-#ifdef CONFIG_DM_GPIO
-#ifndef CONFIG_MPC8XXX_GPIO
-#define CONFIG_MPC8XXX_GPIO
-#endif
-#endif
/* I2C */
#include "ls1028a_common.h"
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
+#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#include "ls1028a_common.h"
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
+#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
#define CONFIG_SYS_RTC_BUS_NUM 0
#endif
/* GPIO */
-#ifdef CONFIG_DM_GPIO
-#ifndef CONFIG_MPC8XXX_GPIO
-#define CONFIG_MPC8XXX_GPIO
-#endif
-#endif
/* IFC */
#ifndef SPL_NO_IFC
#if defined(CONFIG_TFABOOT) || \
(!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI))
-#define CONFIG_FSL_IFC
/*
* CONFIG_SYS_FLASH_BASE has the final address (core view)
* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
#endif
/* DSPI */
-#ifndef SPL_NO_DSPI
-#ifdef CONFIG_FSL_DSPI
-#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
-#define CONFIG_SPI_FLASH_SST /* cs1 */
-#define CONFIG_SPI_FLASH_EON /* cs2 */
-#endif
-#endif
/* FMan ucode */
#ifndef SPL_NO_FMAN
#include "ls1043a_common.h"
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
-#define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv"
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_VID
-#endif
-#define CONFIG_VOL_MONITOR_IR36021_SET
-#define CONFIG_VOL_MONITOR_INA220
/* The lowest and highest voltage allowed for LS1043AQDS */
#define VDD_MV_MIN 819
#define VDD_MV_MAX 1212
#include "ls1043a_common.h"
-#define CONFIG_SYS_CLK_FREQ 100000000
-
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#endif
/* GPIO */
-#ifdef CONFIG_DM_GPIO
-#ifndef CONFIG_MPC8XXX_GPIO
-#define CONFIG_MPC8XXX_GPIO
-#endif
-#endif
/* I2C */
#include "ls1046a_common.h"
-#define CONFIG_SYS_CLK_FREQ 100000000
-
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_UBOOT_BASE 0x40100000
-/* IFC */
-#define CONFIG_FSL_IFC
/*
* NAND Flash Definitions
*/
#include "ls1046a_common.h"
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* IFC */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_FSL_IFC
/*
* CONFIG_SYS_FLASH_BASE has the final address (core view)
* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
-#define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv"
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_VID
-#endif
-#define CONFIG_VOL_MONITOR_IR36021_SET
-#define CONFIG_VOL_MONITOR_INA220
/* The lowest and highest voltage allowed for LS1046AQDS */
#define VDD_MV_MIN 819
#define VDD_MV_MAX 1212
#include "ls1046a_common.h"
-#define CONFIG_SYS_CLK_FREQ 100000000
-
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
#endif
-#ifndef SPL_NO_IFC
-/* IFC */
-#define CONFIG_FSL_IFC
-/*
- * NAND Flash Definitions
- */
-#endif
-
#define CONFIG_SYS_NAND_BASE 0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#define CPU_RELEASE_ADDR secondary_boot_addr
/* GPIO */
-#ifdef CONFIG_DM_GPIO
-#ifndef CONFIG_MPC8XXX_GPIO
-#define CONFIG_MPC8XXX_GPIO
-#endif
-#endif
/* I2C */
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
-#if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS)
-/* IFC */
-#define CONFIG_FSL_IFC
-#endif
-
/*
* During booting, IFC is mapped at the region of 0x30000000.
* But this region is limited to 256MB. To accommodate NOR, promjet
#include "ls1088a_common.h"
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_QIXIS_I2C_ACCESS
#define SYS_NO_FLASH
-
-#define CONFIG_SYS_CLK_FREQ 100000000
#else
#define CONFIG_QIXIS_I2C_ACCESS
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#endif
-#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
+#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
#define I2C_SVDD_MONITOR_ADDR 0x4F
-#define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv"
-#define CONFIG_VID
-
/* The lowest and highest voltage allowed for LS1088AQDS */
#define VDD_MV_MIN 819
#define VDD_MV_MAX 1212
-#define CONFIG_VOL_MONITOR_LTC3882_SET
-#define CONFIG_VOL_MONITOR_LTC3882_READ
-
#define PWM_CHANNEL0 0x0
/*
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#ifdef CONFIG_FSL_DSPI
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_EON
#if !defined(CONFIG_TFABOOT) && \
!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#endif
#define SYS_NO_FLASH
#endif
-#define CONFIG_SYS_CLK_FREQ 100000000
#define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
#define I2C_SVDD_MONITOR_ADDR 0x4F
-#define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv"
-#define CONFIG_VID
-
/* The lowest and highest voltage allowed for LS1088ARDB */
#define VDD_MV_MIN 819
#define VDD_MV_MAX 1212
-#define CONFIG_VOL_MONITOR_LTC3882_SET
-#define CONFIG_VOL_MONITOR_LTC3882_READ
-
#define PWM_CHANNEL0 0x0
/*
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
/* GPIO */
-#ifdef CONFIG_DM_GPIO
-#ifndef CONFIG_MPC8XXX_GPIO
-#define CONFIG_MPC8XXX_GPIO
-#endif
-#endif
/* I2C */
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
-/* IFC */
-#define CONFIG_FSL_IFC
-
/*
* During booting, IFC is mapped at the region of 0x30000000.
* But this region is limited to 256MB. To accommodate NOR, promjet
#include "ls2080a_common.h"
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
#ifdef CONFIG_FSL_QSPI
#define CONFIG_QIXIS_I2C_ACCESS
#define CONFIG_SYS_I2C_IFDR_DIV 0x7e
#endif
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
+#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS1 0x51
#define I2C_MUX_CH_DEFAULT 0x8
/* SPI */
-#ifdef CONFIG_FSL_DSPI
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_EON
-#endif
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
-#endif
/*
* Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
* If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
*/
#define RTC
#define CONFIG_RTC_DS3231 1
-#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define I2C_MUX_CH_VOL_MONITOR 0xa
#define I2C_VOL_MONITOR_ADDR 0x38
-#define CONFIG_VOL_MONITOR_IR36021_READ
-#define CONFIG_VOL_MONITOR_IR36021_SET
-#define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv"
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_VID
-#endif
/* step the IR regulator in 5mV increments */
#define IR_VDD_STEP_DOWN 5
#define IR_VDD_STEP_UP 5
#define VDD_MV_MIN 819
#define VDD_MV_MAX 1212
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
+#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS1 0x51
#define I2C_MUX_CH_DEFAULT 0x8
/* SPI */
-#if defined(CONFIG_FSL_DSPI)
-#define CONFIG_SPI_FLASH_STMICRO
-#endif
/*
* RTC configuration
#ifndef _CONFIG_LSXL_H
#define _CONFIG_LSXL_H
-/*
- * Version number information
- */
-#if defined(CONFIG_LSCHLV2)
-#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lschl.cfg
-#elif defined(CONFIG_LSXHL)
-#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg
-#else
-#error "unknown board"
-#endif
-
/*
* General configuration options
*/
-#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
-#define CONFIG_KW88F6281 /* SOC Name */
-
-#define CONFIG_KIRKWOOD_GPIO
#include "mv-common.h"
#include <asm/arch/soc.h>
#define CONFIG_REMAKE_ELF
-#define CONFIG_FSL_TZPC_BP147
#define CONFIG_FSL_MEMAC
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
/* PCI */
#ifdef CONFIG_PCI
-#define CONFIG_SYS_PCI_64BIT
#define CONFIG_PCI_SCAN_SHOW
#endif
#endif
#endif
-/* GPIO */
-#ifdef CONFIG_DM_GPIO
-#ifndef CONFIG_MPC8XXX_GPIO
-#define CONFIG_MPC8XXX_GPIO
-#endif
-#endif
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
+#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
#include "lx2160a_common.h"
-/* VID */
-#define CONFIG_VID_FLS_ENV "lx2160aqds_vdd_mv"
-#define CONFIG_VID
-#define CONFIG_VOL_MONITOR_LTC3882_SET
-#define CONFIG_VOL_MONITOR_LTC3882_READ
-
/* RTC */
#define CONFIG_SYS_RTC_BUS_NUM 0
#include "lx2160a_common.h"
-/* VID */
-#define CONFIG_VID_FLS_ENV "lx2160ardb_vdd_mv"
-#define CONFIG_VID
-#define CONFIG_VOL_MONITOR_LTC3882_SET
-#define CONFIG_VOL_MONITOR_LTC3882_READ
-
/* RTC */
#define CONFIG_SYS_RTC_BUS_NUM 4
#undef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-/* Voltage monitor on channel 2*/
-#define CONFIG_VID_FLS_ENV "lx2162aqds_vdd_mv"
-#define CONFIG_VID
-#define CONFIG_VOL_MONITOR_LTC3882_SET
-#define CONFIG_VOL_MONITOR_LTC3882_READ
-
/* RTC */
#define CONFIG_SYS_RTC_BUS_NUM 0
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_FSL_CLK
-
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
/*
"fi ; " \
"fi\0"
-#if defined(CONFIG_SPL_BUILD)
-#undef CONFIG_WATCHDOG
-#define CONFIG_HW_WATCHDOG
-#endif
-
#endif /* __M53MENLO_CONFIG_H__ */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* NAND support */
-#define CONFIG_TEGRA_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Environment in NAND, aligned to start of last sector */
#define STDIN_CFG "serial"
#endif
-#define CONFIG_CPU_ARMV8
#define CONFIG_REMAKE_ELF
#define CONFIG_SYS_MAXARGS 32
#define CONFIG_SYS_CBSIZE 1024
#include <linux/sizes.h>
-#define CONFIG_CPU_ARMV8
#define COUNTER_FREQUENCY 13000000
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
-#define CONFIG_CPU_ARMV8
-
#define COUNTER_FREQUENCY 13000000
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#include <linux/sizes.h>
-#define CONFIG_CPU_ARMV8
#define COUNTER_FREQUENCY 13000000
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
-#define CONFIG_CPU_ARMV8
-
#define COUNTER_FREQUENCY 13000000
/* DRAM definition */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009-2015
- * Marvell Semiconductor <www.marvell.com>
- */
-
-#ifndef _CONFIG_MARVELL_PLUG_H
-#define _CONFIG_MARVELL_PLUG_H
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_KW88F6281 1 /* SOC Name */
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-#endif /* _CONFIG_MARVELL_PLUG_H */
/* High Level Configuration Options */
-#define CONFIG_SYS_FSL_CLK
-
#include <asm/arch/imx-regs.h>
/*
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_FSL_CLK
-
#define CONFIG_MXC_UART_BASE UART2_BASE
#define CONFIG_FPGA_COUNT 1
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_FSL_CLK
-
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_FSL_CLK
-
/* USB Configs */
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#include <asm/arch/imx-regs.h>
#include <asm/mach-imx/gpio.h>
-#define CONFIG_SYS_FSL_CLK
-
/* Miscellaneous configurable options */
#define CONFIG_SYS_CBSIZE 512
#define CONFIG_SYS_MAXARGS 32
#endif
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
"splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
#endif
#endif
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
"ip_dyn=yes\0" \
"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
#define CONFIG_IOMUX_LPSR
-#define CONFIG_SOFT_SPI
-
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_ENET_DEV 1
#if (CONFIG_FEC_ENET_DEV == 0)
#define CONFIG_MXC_GPT_HCLK
#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
#define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK
-#define CONFIG_SYS_FSL_CLK
#define CONFIG_SYS_BOOTM_LEN 0x1000000
/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
#ifdef CONFIG_IMX_BOOTAUX
/* Set to QSPI1 A flash at default */
#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000
*/
#define CONFIG_BOARD_SIZE_LIMIT 785408
#define CONFIG_MMCROOT "/dev/mmcblk0p2"
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG1_RBASE
"fdt_file=imx7ulp-com.dtb\0" \
"fdt_addr=0x63000000\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
#define CONFIG_SYS_BOOTM_LEN 0x1000000
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG1_RBASE
"earlycon=lpuart32,0x402D0010\0" \
"ip_dyn=yes\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
#ifndef _CONFIG_NAS220_H
#define _CONFIG_NAS220_H
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 /* #define CPU Core subversion */
-#define CONFIG_KW88F6192 /* SOC Name */
-
/* power-on led, regulator, sata0, sata1 */
#define NAS220_GE_OE_VAL_LOW ((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28))
#define NAS220_GE_OE_VAL_HIGH (0)
#define CONFIG_PHY_BASE_ADR 8
#endif /* CONFIG_CMD_NET */
-/*
- * File system
- */
-#define CONFIG_JFFS2_NAND
-#define CONFIG_JFFS2_LZO
-
/*
* EFI partition
*/
-#define CONFIG_KIRKWOOD_GPIO
-
#endif /* _CONFIG_NAS220_H */
/*
* High Level Configuration Options
*/
-#define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
#ifndef _CONFIG_NSA310S_H
#define _CONFIG_NSA310S_H
-/* high level configuration options */
-#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-#define CONFIG_KW88F6192 1 /* SOC Name */
-#define CONFIG_KW88F6702 1 /* SOC Name */
-
#include "mv-common.h"
/* environment variables configuration */
#define CONFIG_LBA48
#endif /* CONFIG_SATA */
-/* RTC driver configuration */
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_MV
-#endif /* CONFIG_CMD_DATE */
-
#endif /* _CONFIG_NSA310S_H */
#ifndef __OCTEONTX2_COMMON_H__
#define __OCTEONTX2_COMMON_H__
-#define CONFIG_SUPPORT_RAW_INITRD
-
/** Maximum size of image supported for bootm (and bootable FIT images) */
#define CONFIG_SYS_BOOTM_LEN (256 << 20)
#if defined(CONFIG_MMC_OCTEONTX)
#define MMC_SUPPORTS_TUNING
/** EMMC specific defines */
-#define CONFIG_SUPPORT_EMMC_RPMB
#endif
#endif /* __OCTEONTX2_COMMON_H__ */
# define CONFIG_SYS_64BIT_LBA
#endif
-/***** SPI Defines *********/
-#ifdef CONFIG_DM_SPI_FLASH
-# define CONFIG_SF_DEFAULT_BUS 0
-# define CONFIG_SF_DEFAULT_CS 0
-#endif
-
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /** Console I/O Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 8192
/** EMMC specific defines */
-#if defined(CONFIG_MMC_OCTEONTX)
-#define CONFIG_SUPPORT_EMMC_RPMB
-#endif
#if defined(CONFIG_NAND_OCTEONTX)
/*#define CONFIG_MTD_CONCAT */
#include <configs/exynos4-common.h>
-#define CONFIG_SYS_L2CACHE_OFF
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x10502000
* Need to override existing one (smdk5420) with odroid so set_board_info will
* use proper prefix when creating full board_name (SYS_BOARD + type)
*/
-#undef CONFIG_SYS_BOARD
-#define CONFIG_SYS_BOARD "odroid"
/* Define new extra env settings, including DFU settings */
#undef CONFIG_EXTRA_ENV_SETTINGS
/*
* SoC Configuration
*/
-#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#ifndef _CONFIG_OPENRD_H
#define _CONFIG_OPENRD_H
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
-#define CONFIG_KW88F6281 1 /* SOC Name */
-
#include "mv-common.h"
/*
#define CONFIG_SPL_NAND_INIT
#define CONFIG_SPL_COMMON_INIT_DDR
#define CONFIG_SPL_MAX_SIZE (128 << 10)
-#define CONFIG_TPL_TEXT_BASE 0xf8f81000
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
#elif defined(CONFIG_SPL_BUILD)
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
#endif /* not CONFIG_TPL_BUILD */
#define CONFIG_SPL_PAD_TO 0x20000
#ifndef CONFIG_SYS_MONITOR_BASE
#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE 0xf8f81000
#elif defined(CONFIG_SPL_BUILD)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_LBA48
-#if defined(CONFIG_TARGET_P2020RDB)
-#define CONFIG_SYS_CLK_FREQ 100000000
-#else
-#define CONFIG_SYS_CLK_FREQ 66666666
-#endif
-
#define CONFIG_HWCONFIG
/*
* These can be toggled for performance analysis, otherwise use default.
#if defined(CONFIG_HAS_FSL_DR_USB)
#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
#endif
#endif
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
/*
* Miscellaneous configurable options
*/
func(DHCP, dhcp, na)
/* Environment at end of QSPI, in the VER partition */
-#define CONFIG_ENV_SPI_MAX_HZ 48000000
-#define CONFIG_ENV_SPI_MODE SPI_MODE_0
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-#define CONFIG_PREBOOT
-
#define BOARD_EXTRA_ENV_SETTINGS \
"preboot=if test -e mmc 1:1 /u-boot-preboot.scr; then " \
"load mmc 1:1 ${scriptaddr} /u-boot-preboot.scr; " \
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"ip_dyn=yes\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=2\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console} " \
/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#endif /* __PHYCORE_IMX8MM_H */
#define CONFIG_SPL_MAX_SIZE (152 * SZ_1K)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"ip_dyn=yes\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=2\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console} " \
/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#endif /* __PHYCORE_IMX8MP_H */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
-#define CONFIG_SYS_ENV_ADDR 0x88300000
-#define CONFIG_SYS_FDT_ADDR 0x89d00000
-
/* Memory Test */
/*----------------------------------------------------------------------
#define MEM_LAYOUT_ENV_SETTINGS \
"kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
- "fdt_addr_r="__stringify(CONFIG_SYS_FDT_ADDR)"\0" \
- "scriptaddr="__stringify(CONFIG_SYS_ENV_ADDR)"\0"
+ "fdt_addr_r=0x89d00000\0" \
+ "scriptaddr=0x88300000\0" \
#define CONFIG_LEGACY_BOOTCMD_ENV \
"legacy_bootcmd= " \
"bootmenu_2=Boot using PICO-Pi baseboard=" \
"setenv fdtfile imx6ul-pico-pi.dtb\0" \
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
BOOTENV
#endif
-
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"image=zImage\0" \
"splashpos=m,m\0" \
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
"initrd_addr=0x43800000\0" \
"initrd_high=0xffffffffffffffff\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
- (PHYS_SDRAM_SIZE >> 1))
-
#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
/* Monitor Command Prompt */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
-#define CONFIG_MXC_GPIO
-
-#define CONFIG_OF_SYSTEM_SETUP
-
#define CONFIG_SYS_BOOTM_LEN SZ_128M
#endif
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* NAND support */
-#define CONFIG_TEGRA_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Environment in NAND, aligned to start of last sector */
#endif
-#define CONFIG_JFFS2_NAND 1
-#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
-#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
-#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/
-
/* PSRAM */
#define PHYS_PSRAM 0x70000000
#define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */
#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD3
-#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
#endif
/* Ethernet */
#ifndef _CONFIG_POGO_E02_H
#define _CONFIG_POGO_E02_H
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
-#define CONFIG_KW88F6281 /* SOC Name */
-
#include "mv-common.h"
/*
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define RMOBILE_XTAL_CLK 20000000u
-#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
#define CONFIG_REMAKE_ELF
-#define CONFIG_SUPPORT_RAW_INITRD
-
#define CONFIG_SYS_INIT_SP_ADDR 0x00100000
#define CONFIG_SYS_BOOTM_LEN 0x00c00000
#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
#define CONFIG_ENABLE_36BIT_PHYS
/* Needed to fill the ccsrbar pointer */
#define CONFIG_CHIP_SELECTS_PER_CTRL 0
-#define CONFIG_SYS_CLK_FREQ 33000000
-
#define CONFIG_SYS_BOOT_BLOCK 0x00000000 /* boot TLB */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_CPU_SH7751 1
#define __LITTLE_ENDIAN__ 1
/* SCIF */
/*
* SuperH Clock setting
*/
-#define CONFIG_SYS_CLK_FREQ 60000000
#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
/*
#define CONFIG_TMU_TIMER
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
-#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 8)
+#define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 8)
#endif /* __RCAR_GEN2_COMMON_H */
#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0
#define COUNTER_FREQUENCY 24000000
-#define CONFIG_SYS_ARCH_TIMER
#define CONFIG_SYS_HZ_CLOCK 24000000
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0
#define COUNTER_FREQUENCY 24000000
-#define CONFIG_SYS_ARCH_TIMER
#define CONFIG_SYS_HZ_CLOCK 24000000
#define CONFIG_IRAM_BASE 0x10080000
/* spl size 32kb sram - 2kb bootrom */
#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800)
-#define CONFIG_ROCKCHIP_SERIAL 1
#define CONFIG_SPL_STACK 0x10087fff
#define CONFIG_ROCKCHIP_STIMER_BASE 0x110d0020
#define COUNTER_FREQUENCY 24000000
-#define CONFIG_SYS_ARCH_TIMER
#define CONFIG_SYS_HZ_CLOCK 24000000
#define CONFIG_SYS_INIT_SP_ADDR 0x61100000
#define CONFIG_ROCKCHIP_STIMER_BASE 0xff810020
#define COUNTER_FREQUENCY 24000000
-#define CONFIG_SYS_ARCH_TIMER
#define CONFIG_SYS_HZ_CLOCK 24000000
#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
#define CONFIG_SPL_MAX_SIZE 0x20000
#define CONFIG_SPL_BSS_START_ADDR 0x00400000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
#define CONFIG_SYS_NS16550_MEM32
(void *)PHY_BASEADDR_UART2, \
(void *)PHY_BASEADDR_UART3}
-/*-----------------------------------------------------------------------
- * PLL
- */
-#define CONFIG_SYS_PLLFIN 24000000UL
-
-/*-----------------------------------------------------------------------
- * Timer
- */
-#define CONFIG_TIMER_SYS_TICK_CH 0
-
/*-----------------------------------------------------------------------
* BACKLIGHT
*/
#include <linux/sizes.h>
#include <asm/arch/cpu.h> /* get chip and board defs */
-/* input clock of PLL: has 24MHz input clock at S5PC110 */
-#define CONFIG_SYS_CLK_FREQ_C110 24000000
-
/* DRAM Base */
#define CONFIG_SYS_SDRAM_BASE 0x30000000
#define CONFIG_TIZEN /* TIZEN lib */
/* Keep L2 Cache Disabled */
-#define CONFIG_SYS_L2CACHE_OFF 1
/* Universal has 2 banks of DRAM */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_USB_GADGET_DWC2_OTG_PHY
-/*
- * SPI Settings
- */
-#define CONFIG_SOFT_SPI
-
#ifndef __ASSEMBLY__
void universal_spi_scl(int bit);
void universal_spi_sda(int bit);
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 }
-#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif
-/* NAND flash */
-
-/* SPI flash */
-#define CONFIG_SF_DEFAULT_SPEED 66000000
-
#ifdef CONFIG_SD_BOOT
/* u-boot env in sd/mmc card */
#define FAT_ENV_INTERFACE "mmc"
#endif
-#ifdef CONFIG_QSPI_BOOT
-#undef CONFIG_ENV_SPI_BUS
-#define CONFIG_ENV_SPI_BUS 1
-
-#endif
-
/* SPL */
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
/* Environment in eMMC, at the end of 2nd "boot sector" */
/* NAND support */
-#define CONFIG_TEGRA_NAND
/* Max number of NAND devices */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#ifndef _CONFIG_SHEEVAPLUG_H
#define _CONFIG_SHEEVAPLUG_H
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-
-#include "mv-plug-common.h"
+#include "mv-common.h"
/*
* Environment variables configurations
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/* Be very careful updating CONFIG_IDENT_STRING
- * This string will control the update flow whether an U-Boot should be
- * updated or not. If the version of installed U-Boot (in flash) is smaller
- * than the version to be installed (from update file), an update will
- * be performed.
- *
- * General rules:
- * 1. First 4 characters ' ##v' or IDENT_MAGIC represent kind of a magic number
- * to identify the following strings after easily. Don't change them!
- *
- * 2. First 2 digits after 'v' or CCP_MAJOR are updated with U-Boot version
- * change, e.g. from 2015.04 to 2018.03
- *
- * 3. Second 2 digits after '.' or CCP_MINOR are updated if we want to upgrade
- * U-Boot within an U-Boot version.
- */
-#define CCP_IDENT_MAGIC " ##v"
-#define GENERATE_CCP_VERSION(MAJOR, MINOR) CCP_IDENT_MAGIC MAJOR "." MINOR
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
BOOTENV \
BOOTENV_SF
-
-#define CONFIG_PREBOOT \
- "setenv fdt_addr ${fdtcontroladdr};" \
- "fdt addr ${fdtcontroladdr};"
#endif
#endif /* __CONFIG_H */
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit resources */
-
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
/* Environment options */
"partitions=" PARTS_DEFAULT "\0" \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
BOOTENV
-
-#define CONFIG_PREBOOT \
- "setenv fdt_addr ${fdtcontroladdr};" \
- "fdt addr ${fdtcontroladdr};"
#endif /* CONFIG_SPL_BUILD */
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define RMOBILE_XTAL_CLK 20000000u
-#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
#include <asm/arch/cpu.h> /* get chip and board defs */
/* input clock of PLL: SMDKC100 has 12MHz input clock */
-#define CONFIG_SYS_CLK_FREQ 12000000
/* DRAM Base */
#define CONFIG_SYS_SDRAM_BASE 0x30000000
/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_EXTRA_ENV_SETTINGS \
"image=zImage\0" \
#define CONFIG_AT91_WANTS_COMMON_PHY
#define CONFIG_TFTP_PORT
-/* MMC */
-#define CONFIG_GENERIC_ATMEL_MCI
-
/* LCD */
#define CONFIG_ATMEL_LCD
#define CONFIG_GURNARD_SPLASH
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
-#undef CONFIG_WATCHDOG_TIMEOUT_MSECS
-#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000
-
#endif /* __CONFIG_SOCFPGA_SECU1_H__ */
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
-#else
-#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
-#endif
#endif
/* SPL QSPI boot support */
/* Flash device info */
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
#endif /* CONFIG_SPL_BUILD */
* L4 Watchdog
*/
#ifndef CONFIG_SPL_BUILD
-#undef CONFIG_HW_WATCHDOG
#undef CONFIG_DESIGNWARE_WATCHDOG
#endif
#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
* in the README.mpc85xxads.
*/
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 66666666
-#endif
-
/*
* These can be toggled for performance analysis, otherwise use default.
*/
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
/*
* Miscellaneous configurable options
*/
#define CONFIG_RTC_MCFRRTC
#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
-/* spi not partitions */
-#define CONFIG_JFFS2_DEV "nor0"
-
/* Timer */
#define CONFIG_MCFTMR
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define RMOBILE_XTAL_CLK 20000000u
-#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
#define CONFIG_SYS_FLASH_BASE (0x08000000)
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (512 * 1024))
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE)
-
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_MAXARGS 128
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
-/* #define CONFIG_SYS_PCI_64BIT 1 */
#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \
"mtd nor1=u-boot.bin raw 200000 100000;" \
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * Copyright (C) 2009 TechNexion Ltd.
- */
-
-#ifndef __TAM3517_H
-#define __TAM3517_H
-
-/*
- * High Level Configuration Options
- */
-
-#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap.h>
-
-/* Clock Defines */
-#define V_OSCK 26000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
-
-/*
- * DDR related
- */
-#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
-
-/*
- * Hardware drivers
- */
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
-
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-
-/*
- * Board NAND Info.
- */
-#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
- /* to access */
- /* nand at CS0 */
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
- /* NAND devices */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-
-#define CONFIG_SYS_MAXARGS 32 /* max number of command */
- /* args */
-
-/*
- * AM3517 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-
-/*
- * Physical Memory Map
- */
-#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
-
-/*
- * FLASH and environment organization
- */
-
-/* **** PISMO SUPPORT *** */
-
-/* Redundant Environment */
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-/*
- * ethernet support, EMAC
- *
- */
-#define CONFIG_NET_RETRY_COUNT 10
-
-/* Defines for SPL */
-#define CONFIG_SPL_CONSOLE
-#define CONFIG_SPL_NAND_SOFTECC
-#define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */
-
-#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
- CONFIG_SPL_TEXT_BASE)
-#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
-
-#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
-#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
-
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-
-/* FAT */
-#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
-#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
-
-/* RAW SD card / eMMC */
-#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
-
-/* NAND boot config */
-#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
- 48, 49, 50, 51, 52, 53, 54, 55,\
- 56, 57, 58, 59, 60, 61, 62, 63}
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
-
-/* Setup MTD for NAND on the SOM */
-
-#define CONFIG_TAM3517_SETTINGS \
- "netdev=eth0\0" \
- "nandargs=setenv bootargs root=${nandroot} " \
- "rootfstype=${nandrootfstype}\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip_sta=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
- "addip=if test -n ${ipdyn};then run addip_dyn;" \
- "else run addip_sta;fi\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addtty=setenv bootargs ${bootargs}" \
- " console=ttyO0,${baudrate}\0" \
- "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
- "loadaddr=82000000\0" \
- "kernel_addr_r=82000000\0" \
- "hostname=" CONFIG_HOSTNAME "\0" \
- "bootfile=" CONFIG_HOSTNAME "/uImage\0" \
- "flash_self=run ramargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr}\0" \
- "nandboot=run nandargs addip addtty addmtd addmisc;" \
- "nand read ${kernel_addr_r} kernel\0" \
- "bootm ${kernel_addr_r}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
- "run nfsargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr_r}\0" \
- "net_self=if run net_self_load;then " \
- "run ramargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
- "else echo Images not loades;fi\0" \
- "u-boot=" CONFIG_HOSTNAME "/u-boot.img\0" \
- "load=tftp ${loadaddr} ${u-boot}\0" \
- "loadmlo=tftp ${loadaddr} ${mlo}\0" \
- "mlo=" CONFIG_HOSTNAME "/MLO\0" \
- "uboot_addr=0x80000\0" \
- "update=nandecc sw;nand erase ${uboot_addr} 100000;" \
- "nand write ${loadaddr} ${uboot_addr} 80000\0" \
- "updatemlo=nandecc hw;nand erase 0 20000;" \
- "nand write ${loadaddr} 0 20000\0" \
- "upd=if run load;then echo Updating u-boot;if run update;" \
- "then echo U-Boot updated;" \
- "else echo Error updating u-boot !;" \
- "echo Board without bootloader !!;" \
- "fi;" \
- "else echo U-Boot not downloaded..exiting;fi\0" \
-
-/*
- * this is common code for all TAM3517 boards.
- * MAC address is stored from manufacturer in
- * I2C EEPROM
- */
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-/*
- * The I2C EEPROM on the TAM3517 contains
- * mac address and production data
- */
-struct tam3517_module_info {
- char customer[48];
- char product[48];
-
- /*
- * bit 0~47 : sequence number
- * bit 48~55 : week of year, from 0.
- * bit 56~63 : year
- */
- unsigned long long sequence_number;
-
- /*
- * bit 0~7 : revision fixed
- * bit 8~15 : revision major
- * bit 16~31 : TNxxx
- */
- unsigned int revision;
- unsigned char eth_addr[4][8];
- unsigned char _rev[100];
-};
-
-#define TAM3517_READ_EEPROM(info, ret) \
-do { \
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); \
- if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \
- (void *)info, sizeof(*info))) \
- ret = 1; \
- else \
- ret = 0; \
-} while (0)
-
-#define TAM3517_READ_MAC_FROM_EEPROM(info) \
-do { \
- char buf[80], ethname[20]; \
- int i; \
- memset(buf, 0, sizeof(buf)); \
- for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \
- sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \
- (info)->eth_addr[i][5], \
- (info)->eth_addr[i][4], \
- (info)->eth_addr[i][3], \
- (info)->eth_addr[i][2], \
- (info)->eth_addr[i][1], \
- (info)->eth_addr[i][0]); \
- \
- if (i) \
- sprintf(ethname, "eth%daddr", i); \
- else \
- strcpy(ethname, "ethaddr"); \
- printf("Setting %s from EEPROM with %s\n", ethname, buf);\
- env_set(ethname, buf); \
- } \
-} while (0)
-
-/* The following macros are taken from Technexion's documentation */
-#define TAM3517_sequence_number(info) \
- ((info)->sequence_number % 0x1000000000000LL)
-#define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
-#define TAM3517_year(info) ((info)->sequence_number >> 56)
-#define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
-#define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
-#define TAM3517_revision_tn(info) ((info)->revision >> 16)
-
-#define TAM3517_PRINT_SOM_INFO(info) \
-do { \
- printf("Vendor:%s\n", (info)->customer); \
- printf("SOM: %s\n", (info)->product); \
- printf("SeqNr: %02llu%02llu%012llu\n", \
- TAM3517_year(info), \
- TAM3517_week_of_year(info), \
- TAM3517_sequence_number(info)); \
- printf("Rev: TN%u %u.%u\n", \
- TAM3517_revision_tn(info), \
- TAM3517_revision_major(info), \
- TAM3517_revision_fixed(info)); \
-} while (0)
-
-#endif
-
-#endif /* __TAM3517_H */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* NAND support */
-#define CONFIG_TEGRA_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Environment in NAND, aligned to start of last sector */
/*
* High Level Configuration Options
*/
-#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
#include <asm/arch/tegra.h> /* get chip and board defs */
*/
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
-#define CONFIG_SYS_NAND_SELF_INIT
-
#endif /* _TEGRA20_COMMON_H_ */
/**
* Platform/Board specific defs
*/
-#define CONFIG_SYS_CLK_FREQ 27000000
#define CONFIG_SYS_TIMERBASE 0x4802E000
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_TIZEN /* TIZEN lib */
-#define CONFIG_SYS_L2CACHE_OFF
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x10502000
#define CONFIG_TIZEN /* TIZEN lib */
-#define CONFIG_SYS_L2CACHE_OFF
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x10502000
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 }
-#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SPL_PAD_TO 0x20000
-#define CONFIG_SYS_PCI_64BIT
-
#endif /* __CONFIG_UNIPHIER_H__ */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_FSL_CLK
-
#include <asm/arch/imx-regs.h>
/* U-Boot environment */
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
/* ENET */
#define CONFIG_ETHPRIME "FEC"
/* Board info register */
#define SYS_ID V2M_SYSREGS
-#define CONFIG_SYS_L2CACHE_OFF 1
-
#define SCTL_BASE V2M_SYSCTL
#define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0)
#include <asm/arch/imx-regs.h>
#include <linux/stringify.h>
-#define CONFIG_SYS_FSL_CLK
-
/* NAND support */
#ifdef CONFIG_CMD_NAND
#ifdef CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI0
-#define CONFIG_SPI_FLASH_STMICRO
#endif
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_ATMEL_MCI
#define ATMEL_BASE_MMCI 0xfc000000
#define CONFIG_SYS_MMC_CLK_OD 500000
#define CONFIG_SYS_NS16550_CLK 40000000
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM3 0xb0000e00
-#define CONFIG_CONS_INDEX 3
/* RAM */
/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_DFU_ENV_SETTINGS \
"dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"fdt_file=imx7s-warp.dtb\0" \
- "fdt_addr=" __stringify(CONFIG_SYS_FDT_ADDR)"\0" \
+ "fdt_addr=0x83000000\0" \
"fdtovaddr=0x83100000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"rootpart=" __stringify(CONFIG_WARP7_ROOT_PART) "\0" \
"finduuid=part uuid mmc 0:${rootpart} uuid\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
*/
/* driver configuration */
-#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_MAX_NAND_CHIPS 1
#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
* GPIO
*/
-#define CONFIG_LPC32XX_GPIO
-
/*
* Environment
*/
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (SZ_32K / 0x200)
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR (SZ_1M / 0x200)
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SPI_FLASH_MTD
-#endif
-
/* Memory configuration */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */
#define CONFIG_EXTRA_ENV_SETTINGS
-#undef CONFIG_NR_DRAM_BANKS
#undef CONFIG_SYS_SDRAM_BASE
-#define CONFIG_NR_DRAM_BANKS 1
-
-/*
- * This can be any arbitrary address as we are using PIE, but
- * please note, that CONFIG_SYS_TEXT_BASE must match the below.
- */
-#define CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE CONFIG_SYS_LOAD_ADDR
-
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_OF_SYSTEM_SETUP
-
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadimage=ext4load pvblock 0 0x90000000 /boot/Image;\0" \
#endif
/* Serial setup */
-#define CONFIG_CPU_ARMV8
-
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 4800, 9600, 19200, 38400, 57600, 115200 }
#endif
/* Serial setup */
-#define CONFIG_CPU_ARMV8
-
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 4800, 9600, 19200, 38400, 57600, 115200 }
# define CONFIG_SYS_MAX_NAND_DEVICE 1
#endif
-#if defined(CONFIG_SPL_BUILD)
-#define CONFIG_ZYNQMP_PSU_INIT_ENABLED
-#endif
-
/* Miscellaneous configurable options */
#if defined(CONFIG_ZYNQMP_USB)
#define CONFIG_EXTRA_ENV_SETTINGS
-/* CPU clock */
-#define CONFIG_CPU_FREQ_HZ 500000000
-
/* Serial drivers */
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
#define CONFIG_UBOOT_SECTOR_START 0x2
#define CONFIG_UBOOT_SECTOR_COUNT 0x3fe
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
#define CONFIG_XTFPGA
-/* FPGA CPU freq after init */
-#define CONFIG_SYS_CLK_FREQ (gd->cpu_clk)
-
/*===================*/
/* RAM Layout */
/*===================*/
#define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */
/* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_NS16550_CLK get_board_sys_clk()
/*======================*/
/* Ethernet Driver Info */
#ifndef __CONFIG_ZYNQ_COMMON_H
#define __CONFIG_ZYNQ_COMMON_H
-/* CPU clock */
-#ifndef CONFIG_CPU_FREQ_HZ
-# define CONFIG_CPU_FREQ_HZ 800000000
-#endif
-
#define CONFIG_REMAKE_ELF
/* Cache options */
-#define CONFIG_SYS_L2CACHE_OFF
#ifndef CONFIG_SYS_L2CACHE_OFF
# define CONFIG_SYS_L2_PL310
# define CONFIG_SYS_PL310_BASE 0xf8f02000
#ifndef __FTWDT010_H
#define __FTWDT010_H
+#include <clock_legacy.h>
+
struct ftwdt010_wdt {
unsigned int wdcounter; /* Counter Reg - 0x00 */
unsigned int wdload; /* Counter Auto Reload Reg - 0x04 */
/*
* Variable timeout should be set in ms.
- * (CONFIG_SYS_CLK_FREQ/1000) equals 1 ms.
+ * (get_board_sys_clk()/1000) equals 1 ms.
* WDLOAD = timeout * TIMEOUT_FACTOR.
*/
-#define FTWDT010_TIMEOUT_FACTOR (CONFIG_SYS_CLK_FREQ / 1000) /* 1 ms */
+#define FTWDT010_TIMEOUT_FACTOR (get_board_sys_clk() / 1000) /* 1 ms */
void ftwdt010_wdt_reset(void);
void ftwdt010_wdt_disable(void);
#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
CONFIG_SYS_CCSRBAR_PHYS_LOW)
-#ifndef CONFIG_SYS_IMMR
-#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
-#endif
-
#endif /* __MPC85xx_H__ */
#include <config.h>
-/*
- * All boards using a given driver must convert to self-init
- * at the same time, so do it here. When all drivers are
- * converted, this will go away.
- */
-#ifdef CONFIG_SPL_BUILD
-#if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_FSL_IFC)
-#define CONFIG_SYS_NAND_SELF_INIT
-#endif
-#else
-#if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_ATMEL)\
- || defined(CONFIG_NAND_FSL_IFC)
-#define CONFIG_SYS_NAND_SELF_INIT
-#endif
-#endif
-
extern void nand_init(void);
unsigned long nand_size(void);
int nand_mtd_to_devnum(struct mtd_info *mtd);
-#ifdef CONFIG_SYS_NAND_SELF_INIT
+#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
void board_nand_init(void);
int nand_register(int devnum, struct mtd_info *mtd);
#else
struct udevice;
-/* by default ENV use the same parameters than SF command */
-#ifndef CONFIG_ENV_SPI_BUS
-# define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
-#endif
-#ifndef CONFIG_ENV_SPI_CS
-# define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
-#endif
-#ifndef CONFIG_ENV_SPI_MAX_HZ
-# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
-#endif
-#ifndef CONFIG_ENV_SPI_MODE
-# define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
-#endif
-
struct spi_slave;
struct dm_spi_flash_ops {
*/
#include <common.h>
+#include <clock_legacy.h>
#include <bootstage.h>
#include <dm.h>
#include <errno.h>
-CONFIG_64BIT_PHYS_ADDR
-CONFIG_83XX
-CONFIG_83XX_PCICLK
-CONFIG_88F5182
CONFIG_A003399_NOR_WORKAROUND
CONFIG_A008044_WORKAROUND
-CONFIG_AEABI
CONFIG_AM335X_USB0
CONFIG_AM335X_USB0_MODE
CONFIG_AM335X_USB1
CONFIG_AM335X_USB1_MODE
-CONFIG_ANDES_PCU
-CONFIG_ANDES_PCU_BASE
-CONFIG_ARCH_ADPAG101P
-CONFIG_ARCH_HAS_ILOG2_U32
-CONFIG_ARCH_HAS_ILOG2_U64
-CONFIG_ARCH_OMAP4
-CONFIG_ARCH_RMOBILE_EXTRAM_BOOT
-CONFIG_ARCH_USE_BUILTIN_BSWAP
-CONFIG_ARC_MMU_VER
CONFIG_ARMV7_SECURE_BASE
CONFIG_ARMV7_SECURE_MAX_SIZE
CONFIG_ARMV7_SECURE_RESERVE_SIZE
CONFIG_ARMV8_SWITCH_TO_EL1
CONFIG_ARM_GIC_BASE_ADDRESS
CONFIG_ARP_TIMEOUT
-CONFIG_AT91C_PQFP_UHPBUG
-CONFIG_AT91RESET_EXTRST
-CONFIG_AT91RM9200
CONFIG_AT91SAM9260EK
CONFIG_AT91SAM9261EK
CONFIG_AT91SAM9G10
CONFIG_AT91SAM9G10EK
CONFIG_AT91SAM9G20EK
CONFIG_AT91SAM9G20EK_2MMC
-CONFIG_AT91SAM9G45EKES
CONFIG_AT91SAM9G45_LCD_BASE
CONFIG_AT91SAM9M10G45EK
-CONFIG_AT91_CAN
CONFIG_AT91_EFLASH
CONFIG_AT91_GPIO_PULLUP
CONFIG_AT91_LED
CONFIG_ATMEL_LCD_BGR555
CONFIG_ATMEL_LCD_RGB565
CONFIG_ATMEL_LEGACY
-CONFIG_ATMEL_MCI_8BIT
CONFIG_ATMEL_SPI0
CONFIG_AUTO_ZRELADDR
CONFIG_BACKSIDE_L2_CACHE
-CONFIG_BCH_CONST_M
-CONFIG_BCH_CONST_PARAMS
-CONFIG_BCH_CONST_T
CONFIG_BCM2835_GPIO
CONFIG_BIOSEMU
CONFIG_BITBANGMII_MULTI
CONFIG_BOARDNAME
CONFIG_BOARD_COMMON
CONFIG_BOARD_ECC_SUPPORT
-CONFIG_BOARD_IS_OPENRD_BASE
-CONFIG_BOARD_IS_OPENRD_CLIENT
-CONFIG_BOARD_IS_OPENRD_ULTIMATE
CONFIG_BOARD_NAME
CONFIG_BOARD_POSTCLK_INIT
CONFIG_BOARD_SIZE_LIMIT
CONFIG_BOOTFILE
CONFIG_BOOTMODE
CONFIG_BOOTP_BOOTFILESIZE
-CONFIG_BOOTP_DHCP_REQUEST_DELAY
-CONFIG_BOOTP_ID_CACHE_SIZE
CONFIG_BOOTP_MAY_FAIL
CONFIG_BOOTP_NISDOMAIN
-CONFIG_BOOTP_RANDOM_DELAY
CONFIG_BOOTP_SERVERIP
CONFIG_BOOTP_TIMEOFFSET
CONFIG_BOOTP_VENDOREX
CONFIG_BOOTSCRIPT_ADDR
CONFIG_BOOTSCRIPT_COPY_RAM
CONFIG_BOOTSCRIPT_HDR_ADDR
-CONFIG_BOOTSCRIPT_KEY_HASH
CONFIG_BOOT_RETRY_MIN
CONFIG_BOOT_RETRY_TIME
CONFIG_BPTR_VIRT_ADDR
CONFIG_BS_HDR_SIZE
CONFIG_BS_SIZE
CONFIG_BTB
-CONFIG_BUILD_ENVCRC
-CONFIG_BUS_WIDTH
-CONFIG_CDP_APPLIANCE_VLAN_TYPE
-CONFIG_CDP_CAPABILITIES
-CONFIG_CDP_DEVICE_ID
-CONFIG_CDP_DEVICE_ID_PREFIX
-CONFIG_CDP_PLATFORM
-CONFIG_CDP_PORT_ID
-CONFIG_CDP_POWER_CONSUMPTION
-CONFIG_CDP_TRIGGER
-CONFIG_CDP_VERSION
-CONFIG_CFG_DATA_SECTOR
CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
CONFIG_CF_DSPI
CONFIG_CF_SBF
-CONFIG_CF_V2
-CONFIG_CF_V3
-CONFIG_CF_V4
-CONFIG_CF_V4E
CONFIG_CHAIN_BOOT_CMD
CONFIG_CHIP_SELECTS_PER_CTRL
-CONFIG_CHIP_SELECT_QUAD_CAPABLE
CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
CONFIG_CI_UDC_HAS_HOSTPC
-CONFIG_CLK_1000_200_200
-CONFIG_CLK_1000_330_165
CONFIG_CLK_1000_400_200
-CONFIG_CLK_800_330_165
-CONFIG_CLK_DEBUG
CONFIG_CLOCKS
CONFIG_CLOCK_SYNTHESIZER
CONFIG_CM922T_XA10
CONFIG_CM_REMAP
CONFIG_CM_SPD_DETECT
CONFIG_CM_TCRAM
-CONFIG_COLDFIRE
CONFIG_COMMON_BOOT
-CONFIG_COMPAT
-CONFIG_CONS_EXTC_PINSEL
-CONFIG_CONS_EXTC_RATE
CONFIG_CONS_ON_SCC
CONFIG_CONS_SCIF0
CONFIG_CONS_SCIF1
CONFIG_CPLD_BR_PRELIM
CONFIG_CPLD_OR_PRELIM
CONFIG_CPM2
-CONFIG_CPU_ARMV8
-CONFIG_CPU_FREQ_HZ
-CONFIG_CPU_HAS_LLSC
-CONFIG_CPU_HAS_PREFETCH
-CONFIG_CPU_HAS_SMARTMIPS
-CONFIG_CPU_HAS_SR_RB
-CONFIG_CPU_HAS_WB
-CONFIG_CPU_LITTLE_ENDIAN
-CONFIG_CPU_MICROMIPS
-CONFIG_CPU_MIPSR2
-CONFIG_CPU_MONAHANS
-CONFIG_CPU_PXA25X
-CONFIG_CPU_PXA26X
-CONFIG_CPU_PXA27X
-CONFIG_CPU_PXA300
-CONFIG_CPU_SH7751
-CONFIG_CPU_TYPE_R
-CONFIG_CPU_VR41XX
CONFIG_CQSPI_REF_CLK
-CONFIG_CS8900_BUS16
-CONFIG_CS8900_BUS32
-CONFIG_CTL_JTAG
-CONFIG_CTL_TBE
CONFIG_CUSTOMER_BOARD_SUPPORT
-CONFIG_D2NET_V2
-CONFIG_DA850_EVM_MAX_CPU_CLK
CONFIG_DB_784MP_GP
CONFIG_DCACHE
-CONFIG_DCACHE_OFF
-CONFIG_DCFG_ADDR
CONFIG_DEBUG
-CONFIG_DEBUG_FS
CONFIG_DEBUG_LED
-CONFIG_DEBUG_LOCK_ALLOC
-CONFIG_DEBUG_SEMIHOSTING
-CONFIG_DEBUG_UART_LINFLEXUART
-CONFIG_DEBUG_WRITECOUNT
CONFIG_DEEP_SLEEP
CONFIG_DEFAULT
CONFIG_DEFAULT_IMMR
CONFIG_DFU_ALT_BOOT_SD
CONFIG_DFU_ALT_SYSTEM
CONFIG_DFU_ENV_SETTINGS
-CONFIG_DHCP_MIN_EXT_LEN
CONFIG_DIALOG_POWER
CONFIG_DIMM_SLOTS_PER_CTLR
-CONFIG_DISCONTIGMEM
CONFIG_DISCOVER_PHY
-CONFIG_DISPLAY_AER_xxxx
CONFIG_DM9000_BASE
CONFIG_DM9000_BYTE_SWAPPED
CONFIG_DM9000_DEBUG
CONFIG_DM9000_USE_16BIT
CONFIG_DMA_COHERENT
CONFIG_DMA_COHERENT_SIZE
-CONFIG_DMA_NONCOHERENT
-CONFIG_DNET_AUTONEG_TIMEOUT
CONFIG_DP_DDR_CTRL
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR
CONFIG_DP_DDR_NUM_CTRLS
CONFIG_DRIVER_DM9000
CONFIG_DSP_CLUSTER_START
-CONFIG_DWCDDR21MCTL
-CONFIG_DWCDDR21MCTL_BASE
CONFIG_DWC_AHSATA_BASE_ADDR
CONFIG_DWC_AHSATA_PORT_ID
CONFIG_DW_ALTDESCRIPTOR
-CONFIG_DW_AXI_BURST_LEN
CONFIG_DW_GMAC_DEFAULT_DMA_PBL
-CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
CONFIG_DW_WDT_BASE
CONFIG_DW_WDT_CLOCK_KHZ
CONFIG_E1000_NO_NVM
CONFIG_E300
CONFIG_E5500
-CONFIG_ECC
-CONFIG_EDB9301
-CONFIG_EDB93XX_INDUSTRIAL
-CONFIG_EDB93XX_SDCS0
-CONFIG_EDB93XX_SDCS1
-CONFIG_EDB93XX_SDCS2
-CONFIG_EDB93XX_SDCS3
CONFIG_EFLASH_PROTSECTORS
CONFIG_EHCI_DESC_BIG_ENDIAN
CONFIG_EHCI_HCD_INIT_AFTER_RESET
CONFIG_EMU
CONFIG_ENABLE_36BIT_PHYS
CONFIG_ENABLE_MMU
-CONFIG_ENABLE_MUST_CHECK
-CONFIG_ENV_ADDR_FLEX
-CONFIG_ENV_CALLBACK_LIST_DEFAULT
-CONFIG_ENV_CALLBACK_LIST_STATIC
-CONFIG_ENV_FLAGS_LIST_DEFAULT
CONFIG_ENV_FLAGS_LIST_STATIC
CONFIG_ENV_IS_EMBEDDED
CONFIG_ENV_MAX_ENTRIES
CONFIG_ENV_MIN_ENTRIES
-CONFIG_ENV_OFFSET_OOB
CONFIG_ENV_RANGE
CONFIG_ENV_REFLASH
CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS
CONFIG_ENV_SETTINGS_NAND_V2
CONFIG_ENV_SETTINGS_V1
CONFIG_ENV_SETTINGS_V2
-CONFIG_ENV_SIZE_FLEX
CONFIG_ENV_SROM_BANK
CONFIG_ENV_TOTAL_SIZE
CONFIG_ENV_VERSION
-CONFIG_EPH_POWER_EN
-CONFIG_EPOLL
CONFIG_ESBC_ADDR_64BIT
CONFIG_ESBC_HDR_LS
-CONFIG_ESDHC_DETECT_8_BIT_QUIRK
CONFIG_ESDHC_DETECT_QUIRK
CONFIG_ESDHC_HC_BLK_ADDR
CONFIG_ESPRESSO7420
CONFIG_ET1100_BASE
-CONFIG_ETHADDR
CONFIG_ETHBASE
CONFIG_ETHPRIME
-CONFIG_ETH_BUFSIZE
-CONFIG_ETH_RXSIZE
CONFIG_EXTRA_CLOCK
CONFIG_EXTRA_ENV
CONFIG_EXTRA_ENV_SETTINGS
CONFIG_EXTRA_ENV_SETTINGS_COMMON
-CONFIG_EXT_AHB2AHB_BASE
CONFIG_EXT_AHBAPBBRG_BASE
CONFIG_EXT_AHBPCIBRG_BASE
CONFIG_EXT_AHBSLAVE01_BASE
CONFIG_EXT_AHBSLAVE02_BASE
-CONFIG_EXT_PHY
CONFIG_EXT_USB_HOST_BASE
CONFIG_EXYNOS4
CONFIG_EXYNOS4210
CONFIG_EXYNOS_TMU
CONFIG_FACTORYSET
CONFIG_FB_ADDR
-CONFIG_FB_BACKLIGHT
-CONFIG_FB_DEFERRED_IO
CONFIG_FDTADDR
CONFIG_FDTFILE
-CONFIG_FEATURE_CLEAN_UP
-CONFIG_FEATURE_COMMAND_EDITING
-CONFIG_FEATURE_SH_APPLETS_ALWAYS_WIN
-CONFIG_FEATURE_SH_EXTRA_QUIET
-CONFIG_FEATURE_SH_FANCY_PROMPT
-CONFIG_FEATURE_SH_STANDALONE_SHELL
CONFIG_FEC_ENET_DEV
CONFIG_FEC_FIXED_SPEED
-CONFIG_FEC_MXC_25M_REF_CLK
CONFIG_FEC_MXC_PHYADDR
-CONFIG_FEC_MXC_SWAP_PACKET
CONFIG_FEC_XCV_TYPE
-CONFIG_FEROCEON
-CONFIG_FEROCEON_88FR131
-CONFIG_FILE
-CONFIG_FIXED_PHY
-CONFIG_FIXED_PHY_ADDR
CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
CONFIG_FLASH_BR_PRELIM
CONFIG_FLASH_CFI_LEGACY
CONFIG_FLASH_SPANSION_S29WS_N
CONFIG_FLASH_VERIFY
CONFIG_FM_PLAT_CLK_DIV
-CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
CONFIG_FORMIKE
CONFIG_FPGA_COUNT
-CONFIG_FPGA_DELAY
CONFIG_FPGA_STRATIX_V
CONFIG_FSL_CADMUS
CONFIG_FSL_CORENET
CONFIG_FSL_CPLD
CONFIG_FSL_DCU_SII9022A
-CONFIG_FSL_DEEP_SLEEP
CONFIG_FSL_DEVICE_DISABLE
CONFIG_FSL_DIU_CH7301
CONFIG_FSL_DIU_FB
CONFIG_FSL_ESDHC_PIN_MUX
CONFIG_FSL_FIXED_MMC_LOCATION
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
-CONFIG_FSL_I2C_CUSTOM_DFSR
-CONFIG_FSL_I2C_CUSTOM_FDR
CONFIG_FSL_IIM
CONFIG_FSL_ISBC_KEY_EXT
CONFIG_FSL_LBC
CONFIG_FSL_PMIC_CS
CONFIG_FSL_PMIC_MODE
CONFIG_FSL_QIXIS
-CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
CONFIG_FSL_SATA_V2
CONFIG_FSL_SDHC_V2_3
-CONFIG_FSL_SDRAM_TYPE
CONFIG_FSL_SERDES
CONFIG_FSL_SERDES1
CONFIG_FSL_SERDES2
CONFIG_FSL_SGMII_RISER
-CONFIG_FSL_TBCLK_EXTRA_DIV
-CONFIG_FSL_TRUST_ARCH_v1
-CONFIG_FSNOTIFY
-CONFIG_FS_POSIX_ACL
CONFIG_FTAHBC020S
CONFIG_FTAHBC020S_BASE
CONFIG_FTAPBBRG020S_01_BASE
CONFIG_FTCFC010_BASE
CONFIG_FTDMAC020_BASE
-CONFIG_FTGMAC100_BASE
CONFIG_FTGPIO010_BASE
-CONFIG_FTIDE020S_BASE
CONFIG_FTIIC010_BASE
CONFIG_FTINTC010_BASE
CONFIG_FTLCDC100_BASE
CONFIG_FTMAC100_BASE
-CONFIG_FTMAC110_BASE
CONFIG_FTPMU010
CONFIG_FTPMU010_BASE
CONFIG_FTPMU010_POWER
-CONFIG_FTPWM010_BASE
CONFIG_FTRTC010_BASE
CONFIG_FTRTC010_EXTCLK
CONFIG_FTRTC010_PCLK
CONFIG_FTSSP010_01_BASE
CONFIG_FTSSP010_02_BASE
CONFIG_FTTMR010_BASE
-CONFIG_FTTMR010_EXT_CLK
CONFIG_FTUART010_01_BASE
CONFIG_FTUART010_02_BASE
CONFIG_FTUART010_03_BASE
CONFIG_FTWDT010_BASE
CONFIG_FTWDT010_WATCHDOG
-CONFIG_FZOTG266HD0A_BASE
CONFIG_GATEWAYIP
-CONFIG_GLOBAL_DATA_NOT_REG10
CONFIG_GLOBAL_TIMER
CONFIG_GMII
-CONFIG_GPCNTRL
-CONFIG_GPIO_LED_INVERTED_TABLE
-CONFIG_GPIO_LED_STUBS
CONFIG_GREEN_LED
-CONFIG_GURNARD_FPGA
CONFIG_GURNARD_SPLASH
CONFIG_G_DNL_THOR_PRODUCT_NUM
CONFIG_G_DNL_THOR_VENDOR_NUM
CONFIG_HETROGENOUS_CLUSTERS
CONFIG_HIDE_LOGO_VERSION
CONFIG_HIKEY_GPIO
-CONFIG_HITACHI_SX14
CONFIG_HOSTNAME
CONFIG_HPS_ALTERAGRP_DBGATCLK
CONFIG_HPS_ALTERAGRP_MAINCLK
CONFIG_HW_ENV_SETTINGS
CONFIG_I2C_ENV_EEPROM_BUS
CONFIG_I2C_GSC
-CONFIG_I2C_MBB_TIMEOUT
CONFIG_I2C_MULTI_BUS
CONFIG_I2C_MVTWSI
CONFIG_I2C_MVTWSI_BASE
CONFIG_I2C_MVTWSI_BASE0
CONFIG_I2C_MVTWSI_BASE1
-CONFIG_I2C_MVTWSI_BASE2
-CONFIG_I2C_MVTWSI_BASE3
-CONFIG_I2C_MVTWSI_BASE4
-CONFIG_I2C_MVTWSI_BASE5
-CONFIG_I2C_REPEATED_START
CONFIG_I2C_RTC_ADDR
-CONFIG_I2C_TIMEOUT
CONFIG_ICACHE
CONFIG_ICS307_REFCLK_HZ
CONFIG_IDE_PREINIT
CONFIG_IDE_RESET
-CONFIG_IMA
CONFIG_IMX
CONFIG_IMX6_PWM_PER_CLK
CONFIG_IMX_HDMI
CONFIG_IMX_VIDEO_SKIP
-CONFIG_INETSPACE_V2
-CONFIG_INI_ALLOW_MULTILINE
-CONFIG_INI_CASE_INSENSITIVE
-CONFIG_INI_MAX_LINE
-CONFIG_INI_MAX_NAME
-CONFIG_INI_MAX_SECTION
-CONFIG_INTEGRITY
CONFIG_INTERRUPTS
CONFIG_IODELAY_RECALIBRATION
CONFIG_IOMUX_LPSR
CONFIG_IOMUX_SHARE_CONF_REG
-CONFIG_IOS
CONFIG_IO_TRACE
CONFIG_IPADDR
-CONFIG_IPROC
CONFIG_IRAM_BASE
CONFIG_IRAM_END
CONFIG_IRAM_SIZE
CONFIG_IRAM_STACK
CONFIG_IRAM_TOP
CONFIG_IRDA_BASE
-CONFIG_JFFS2_DEV
-CONFIG_JFFS2_LZO
-CONFIG_JFFS2_NAND
-CONFIG_JFFS2_PART_OFFSET
-CONFIG_JFFS2_PART_SIZE
-CONFIG_JFFS2_SUMMARY
CONFIG_JRSTARTR_JR0
-CONFIG_JTAG_CONSOLE
CONFIG_KEEP_SERVERADDR
CONFIG_KEY_REVOCATION
CONFIG_KIRKWOOD_EGIGA_INIT
-CONFIG_KIRKWOOD_GPIO
CONFIG_KIRKWOOD_PCIE_INIT
CONFIG_KIRKWOOD_RGMII_PAD_1V8
-CONFIG_KM8321
CONFIG_KMTEGR1
CONFIG_KM_BOARD_EXTRA_ENV
CONFIG_KM_COGE5UN
CONFIG_KSNET_SERDES_LANES_PER_SGMII
CONFIG_KSNET_SERDES_SGMII2_BASE
CONFIG_KSNET_SERDES_SGMII_BASE
-CONFIG_KVM_GUEST
-CONFIG_KW88F6192
-CONFIG_KW88F6281
-CONFIG_KW88F6702
CONFIG_L1_INIT_RAM
CONFIG_L2_CACHE
-CONFIG_LAN91C96_USE_32_BIT
CONFIG_LAYERSCAPE_NS_ACCESS
CONFIG_LBA48
-CONFIG_LBDAF
CONFIG_LCD_ALIGNMENT
-CONFIG_LCD_BMP_RLE8
CONFIG_LCD_INFO
CONFIG_LCD_INFO_BELOW_LOGO
CONFIG_LCD_IN_PSRAM
CONFIG_LD9040
CONFIG_LEGACY
CONFIG_LEGACY_BOOTCMD_ENV
-CONFIG_LITTLETON_LCD
-CONFIG_LMS283GF05
CONFIG_LOADS_ECHO
CONFIG_LOWPOWER_ADDR
CONFIG_LOWPOWER_FLAG
-CONFIG_LOW_MCFCLK
CONFIG_LPC32XX_ETH
-CONFIG_LPC32XX_ETH_BUFS_BASE
CONFIG_LPC32XX_HSUART
CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY
CONFIG_LPC32XX_NAND_MLC_NAND_TA
CONFIG_LPC32XX_NAND_SLC_WHOLD
CONFIG_LPC32XX_NAND_SLC_WSETUP
CONFIG_LPC32XX_NAND_SLC_WWIDTH
-CONFIG_LPC_BASE
-CONFIG_LPC_IO_BASE
CONFIG_LPUART
CONFIG_LPUART_32B_REG
-CONFIG_LQ038J7DH53
CONFIG_LS102XA_STREAM_ID
CONFIG_LSCHLV2
CONFIG_LSXHL
-CONFIG_M41T94_SPI_CS
-CONFIG_M520x
-CONFIG_M5301x
CONFIG_MACB_SEARCH_PHY
-CONFIG_MACRESET_TIMEOUT
CONFIG_MALLOC_F_ADDR
CONFIG_MALTA
-CONFIG_MARCO_MEMSET
-CONFIG_MASK_AER_AO
CONFIG_MAX_DSP_CPUS
-CONFIG_MAX_FPGA_DEVICES
CONFIG_MAX_MEM_MAPPED
-CONFIG_MAX_PKT
CONFIG_MAX_RAM_BANK_SIZE
-CONFIG_MCF5249
-CONFIG_MCF5253
CONFIG_MCFRTC
CONFIG_MCFTMR
-CONFIG_MDIO_TIMEOUT
CONFIG_MEMSIZE_IN_BYTES
-CONFIG_MEM_HOLE_16M
CONFIG_MEM_INIT_VALUE
CONFIG_MEM_REMAP
CONFIG_MFG_ENV_SETTINGS
CONFIG_MII_DEFAULT_TSEC
CONFIG_MII_INIT
-CONFIG_MIPS_HUGE_TLB_SUPPORT
-CONFIG_MIPS_MT_FPAFF
CONFIG_MISC_COMMON
-CONFIG_MIU_1BIT_INTERLEAVED
CONFIG_MIU_2BIT_21_7_INTERLEAVED
CONFIG_MIU_2BIT_INTERLEAVED
-CONFIG_MIU_LINEAR
CONFIG_MMCROOT
CONFIG_MMC_DEFAULT_DEV
-CONFIG_MMC_RPMB_TRACE
CONFIG_MMC_SUNXI_SLOT
-CONFIG_MMU
CONFIG_MONITOR_IS_IN_RAM
-CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION
-CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN
-CONFIG_MPC83XX_GPIO_0_INIT_VALUE
-CONFIG_MPC83XX_GPIO_1_INIT_DIRECTION
-CONFIG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN
-CONFIG_MPC83XX_GPIO_1_INIT_VALUE
CONFIG_MPC85XX_FEC
CONFIG_MPC85XX_FEC_NAME
-CONFIG_MPC8xxx_DISABLE_BPTR
CONFIG_MTD_CONCAT
-CONFIG_MTD_NAND_MUSEUM_IDS
CONFIG_MTD_NAND_VERIFY_WRITE
-CONFIG_MTD_ONENAND_VERIFY_WRITE
CONFIG_MTD_PARTITION
-CONFIG_MTD_UBI_BEB_RESERVE
-CONFIG_MTD_UBI_BLOCK
-CONFIG_MTD_UBI_DEBUG
-CONFIG_MTD_UBI_DEBUG_MSG
-CONFIG_MTD_UBI_DEBUG_MSG_BLD
-CONFIG_MTD_UBI_DEBUG_MSG_EBA
-CONFIG_MTD_UBI_DEBUG_MSG_IO
-CONFIG_MTD_UBI_DEBUG_MSG_WL
-CONFIG_MTD_UBI_DEBUG_PARANOID
-CONFIG_MTD_UBI_GLUEBI
-CONFIG_MTD_UBI_MODULE
-CONFIG_MULTI_CS
CONFIG_MVGBE_PORTS
-CONFIG_MVMFP_V2
CONFIG_MVS
-CONFIG_MV_ETH_RXQ
-CONFIG_MV_I2C_NUM
-CONFIG_MV_I2C_REG
CONFIG_MX27
CONFIG_MX27_CLK32
-CONFIG_MX27_TIMER_HIGH_PRECISION
-CONFIG_MX28_FEC_MAC_IN_OCOTP
-CONFIG_MXC_EPDC
CONFIG_MXC_GPT_HCLK
CONFIG_MXC_NAND_HWECC
CONFIG_MXC_NAND_IP_REGS_BASE
CONFIG_MXS_AUART
CONFIG_MXS_AUART_BASE
CONFIG_MXS_OCOTP
-CONFIG_MY_OPTION
CONFIG_NANDFLASH_SIZE
CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
CONFIG_NAND_CS_INIT
-CONFIG_NAND_DATA_REG
CONFIG_NAND_ECC_BCH
-CONFIG_NAND_ENV_DST
CONFIG_NAND_KIRKWOOD
CONFIG_NAND_KMETER1
-CONFIG_NAND_MODE_REG
CONFIG_NAND_OMAP_GPMC_WSCFG
CONFIG_NAND_SECBOOT
CONFIG_NAND_SPL
-CONFIG_NAND_U_BOOT
-CONFIG_NATSEMI
-CONFIG_NCEL2C100_BASE
-CONFIG_NCEMIC100_BASE
-CONFIG_NDS_DLM1_BASE
-CONFIG_NDS_DLM2_BASE
-CONFIG_NEO
-CONFIG_NET2BIG_V2
-CONFIG_NETCONSOLE_BUFFER_SIZE
CONFIG_NETDEV
CONFIG_NETMASK
-CONFIG_NETSPACE_LITE_V2
-CONFIG_NETSPACE_MAX_V2
-CONFIG_NETSPACE_MINI_V2
-CONFIG_NETSPACE_V2
-CONFIG_NET_MULTI
CONFIG_NET_RETRY_COUNT
CONFIG_NEVER_ASSERT_ODT_TO_CPU
CONFIG_NFS_TIMEOUT
CONFIG_NOBQFMAN
-CONFIG_NON_SECURE
CONFIG_NORBOOT
CONFIG_NORFLASH_PS32BIT
-CONFIG_NO_ETH
-CONFIG_NO_WAIT
CONFIG_NS16550_MIN_FUNCTIONS
-CONFIG_NS8382X
CONFIG_NUM_DSP_CPUS
-CONFIG_NUM_PAMU
CONFIG_ODROID_REV_AIN
-CONFIG_OFF_PADCONF
CONFIG_ORIGEN
CONFIG_OTHBOOTARGS
CONFIG_OVERWRITE_ETHADDR_ONCE
-CONFIG_PALMAS_AUDPWR
CONFIG_PALMAS_POWER
-CONFIG_PALMAS_SMPS7_FPWM
-CONFIG_PALMAS_USB_SS_PWR
-CONFIG_PARAVIRT
CONFIG_PCA953X
-CONFIG_PCA9698
CONFIG_PCI1
CONFIG_PCI2
CONFIG_PCIE
CONFIG_PCIE_IMX
CONFIG_PCIE_IMX_PERST_GPIO
CONFIG_PCIE_IMX_POWER_GPIO
-CONFIG_PCI_BOOTDELAY
CONFIG_PCI_CLK_FREQ
CONFIG_PCI_CONFIG_HOST_BRIDGE
-CONFIG_PCI_EHCI_DEVICE
-CONFIG_PCI_EHCI_DEVNO
CONFIG_PCI_GT64120
CONFIG_PCI_IO_BUS
CONFIG_PCI_IO_PHYS
CONFIG_PCI_MEM_PHYS
CONFIG_PCI_MEM_SIZE
CONFIG_PCI_MSC01
-CONFIG_PCI_NOSCAN
CONFIG_PCI_OHCI
-CONFIG_PCI_OHCI_DEVNO
CONFIG_PCI_PREF_BUS
CONFIG_PCI_PREF_PHYS
CONFIG_PCI_PREF_SIZE
CONFIG_PCI_SCAN_SHOW
-CONFIG_PCI_SYS_BUS
-CONFIG_PCI_SYS_PHYS
-CONFIG_PCI_SYS_SIZE
CONFIG_PEN_ADDR_BIG_ENDIAN
CONFIG_PHY_BASE_ADR
CONFIG_PHY_ET1011C_TX_CLK_FIX
CONFIG_PHY_ID
CONFIG_PHY_INTERFACE_MODE
CONFIG_PHY_IRAM_BASE
-CONFIG_PHY_MODE_NEED_CHANGE
CONFIG_PHY_RESET_DELAY
-CONFIG_PIXIS_SGMII_CMD
CONFIG_PL011_CLOCK
-CONFIG_PL011_SERIAL_RLCR
CONFIG_PL01x_PORTS
CONFIG_PM
CONFIG_PMC_BR_PRELIM
CONFIG_PME_PLAT_CLK_DIV
CONFIG_PMU
CONFIG_PMW_BASE
-CONFIG_PM_SLEEP
CONFIG_POST
CONFIG_POSTBOOTMENU
-CONFIG_POST_BSPEC1
-CONFIG_POST_BSPEC2
-CONFIG_POST_BSPEC3
-CONFIG_POST_BSPEC4
-CONFIG_POST_BSPEC5
CONFIG_POST_EXTERNAL_WORD_FUNCS
CONFIG_POST_SKIP_ENV_FLAGS
-CONFIG_POST_UART
-CONFIG_POST_WATCHDOG
CONFIG_POWER_FSL
CONFIG_POWER_FSL_MC13892
CONFIG_POWER_HI6553
CONFIG_POWER_LTC3676
CONFIG_POWER_LTC3676_I2C_ADDR
-CONFIG_POWER_MAX77696_I2C_ADDR
CONFIG_POWER_PFUZE100
CONFIG_POWER_PFUZE100_I2C_ADDR
CONFIG_POWER_PFUZE3000
CONFIG_POWER_TPS65217
CONFIG_POWER_TPS65218
CONFIG_POWER_TPS65910
-CONFIG_PPC64BRIDGE
CONFIG_PPC_CLUSTER_START
CONFIG_PPC_SPINTABLE_COMPATIBLE
CONFIG_PRAM
-CONFIG_PRINTK
-CONFIG_PROC_FS
-CONFIG_PROFILE_ALL_BRANCHES
-CONFIG_PROFILING
CONFIG_PSRAM_SCFG
CONFIG_PWM
CONFIG_PXA_LCD
CONFIG_PXA_PWR_I2C
CONFIG_PXA_STD_I2C
CONFIG_PXA_VGA
-CONFIG_PXA_VIDEO
CONFIG_QBMAN_CLK_DIV
CONFIG_QIXIS_I2C_ACCESS
CONFIG_QSPI
-CONFIG_QUOTA
CONFIG_RAMBOOT_NAND
CONFIG_RAMBOOT_SPIFLASH
CONFIG_RAMBOOT_TEXT_BASE
CONFIG_RAMDISK_ADDR
CONFIG_RAMDISK_BOOT
CONFIG_RD_LVL
-CONFIG_REALMODE_DEBUG
CONFIG_RED_LED
-CONFIG_REG
CONFIG_REMAKE_ELF
-CONFIG_REQ
CONFIG_RESERVED_01_BASE
CONFIG_RESERVED_02_BASE
CONFIG_RESERVED_03_BASE
CONFIG_RESTORE_FLASH
CONFIG_RES_BLOCK_SIZE
CONFIG_RMII
-CONFIG_RMSTP0_ENA
-CONFIG_RMSTP10_ENA
-CONFIG_RMSTP11_ENA
-CONFIG_RMSTP1_ENA
-CONFIG_RMSTP2_ENA
-CONFIG_RMSTP3_ENA
-CONFIG_RMSTP4_ENA
-CONFIG_RMSTP5_ENA
-CONFIG_RMSTP6_ENA
-CONFIG_RMSTP7_ENA
-CONFIG_RMSTP8_ENA
-CONFIG_RMSTP9_ENA
CONFIG_ROCKCHIP_CHIP_TAG
CONFIG_ROCKCHIP_MAX_INIT_SIZE
CONFIG_ROCKCHIP_SDHCI_MAX_FREQ
CONFIG_ROCKCHIP_STIMER_BASE
-CONFIG_ROM_STUBS
CONFIG_ROOTPATH
CONFIG_RTC_DS1337
CONFIG_RTC_DS1337_NOOSC
CONFIG_RTC_DS1338
-CONFIG_RTC_DS1339_TCR_VAL
CONFIG_RTC_DS1374
-CONFIG_RTC_DS1388
-CONFIG_RTC_DS1388_TCR_VAL
CONFIG_RTC_DS3231
CONFIG_RTC_FTRTC010
-CONFIG_RTC_M41T11
CONFIG_RTC_MC13XXX
CONFIG_RTC_MCFRRTC
-CONFIG_RTC_MCP79411
CONFIG_RTC_MXS
CONFIG_RTC_PT7C4338
-CONFIG_RX_DESCR_NUM
CONFIG_S5P
CONFIG_S5PC100
CONFIG_S5PC110
CONFIG_S5P_PA_SYSRAM
-CONFIG_S6E8AX0
CONFIG_SAMA5D3_LCD_BASE
CONFIG_SAMSUNG
CONFIG_SAMSUNG_ONENAND
CONFIG_SANDBOX_ARCH
-CONFIG_SANDBOX_BIG_ENDIAN
CONFIG_SANDBOX_SDL
CONFIG_SANDBOX_SPI_MAX_BUS
CONFIG_SANDBOX_SPI_MAX_CS
CONFIG_SAR_REG
CONFIG_SATA1
CONFIG_SATA2
-CONFIG_SATA_ULI5288
-CONFIG_SCF0403_LCD
CONFIG_SCIF_A
-CONFIG_SCIF_USE_EXT_CLK
CONFIG_SCSI_AHCI_PLAT
CONFIG_SCSI_DEV_LIST
CONFIG_SC_TIMER_CLK
CONFIG_SDCARD
CONFIG_SDRAM_OFFSET_FOR_RT
-CONFIG_SD_BOOT_QSPI
CONFIG_SECBOOT
CONFIG_SECURE_BL1_ONLY
-CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
-CONFIG_SECURITY
CONFIG_SEC_FW_SIZE
CONFIG_SERIAL_BOOT
CONFIG_SERIAL_FLASH
-CONFIG_SERIAL_HW_FLOW_CONTROL
CONFIG_SERIAL_SOFTWARE_FIFO
-CONFIG_SERIRQ_CONTINUOUS_MODE
CONFIG_SERVERIP
CONFIG_SETUP_INITRD_TAG
CONFIG_SET_BOOTARGS
CONFIG_SET_DFU_ALT_BUF_LEN
-CONFIG_SGI_IP28
CONFIG_SH73A0
CONFIG_SH7751_PCI
-CONFIG_SHARP_LM8V31
-CONFIG_SHEEVA_88SV131
-CONFIG_SH_CMT_CLK_FREQ
-CONFIG_SH_DSP
CONFIG_SH_ETHER_ALIGNE_SIZE
CONFIG_SH_ETHER_BASE_ADDR
CONFIG_SH_ETHER_CACHE_INVALIDATE
CONFIG_SH_ETHER_SH7734_MII
CONFIG_SH_ETHER_USE_PORT
CONFIG_SH_GPIO_PFC
-CONFIG_SH_MMCIF_CLK
CONFIG_SH_QSPI_BASE
CONFIG_SH_SCIF_CLK_FREQ
-CONFIG_SH_SDHI_FREQ
-CONFIG_SH_SDRAM_OFFSET
CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION
CONFIG_SKIP_TRUNOFF_WATCHDOG
CONFIG_SLIC
-CONFIG_SLTTMR
CONFIG_SMC91111
CONFIG_SMC91111_BASE
CONFIG_SMC91111_EXT_PHY
-CONFIG_SMC_AUTONEG_TIMEOUT
CONFIG_SMC_USE_32_BIT
-CONFIG_SMC_USE_IOFUNCS
CONFIG_SMDK5420
CONFIG_SMP_PEN_ADDR
CONFIG_SMSC_LPC47M
CONFIG_SMSC_SIO1007
-CONFIG_SMSTP0_ENA
-CONFIG_SMSTP10_ENA
-CONFIG_SMSTP11_ENA
-CONFIG_SMSTP1_ENA
-CONFIG_SMSTP2_ENA
-CONFIG_SMSTP3_ENA
-CONFIG_SMSTP4_ENA
-CONFIG_SMSTP5_ENA
-CONFIG_SMSTP6_ENA
-CONFIG_SMSTP7_ENA
-CONFIG_SMSTP8_ENA
-CONFIG_SMSTP9_ENA
CONFIG_SOCRATES
-CONFIG_SOC_OMAP3430
CONFIG_SOFT_I2C_READ_REPEATED_START
CONFIG_SPD_EEPROM
CONFIG_SPIFLASH
CONFIG_SPI_ADDR
CONFIG_SPI_BOOTING
-CONFIG_SPI_DATAFLASH_WRITE_VERIFY
CONFIG_SPI_FLASH_QUAD
CONFIG_SPI_FLASH_SIZE
CONFIG_SPI_HALF_DUPLEX
-CONFIG_SPI_IDLE_VAL
CONFIG_SPI_N25Q256A_RESET
CONFIG_SPL_ATMEL_SIZE
CONFIG_SPL_BOARD_LOAD_IMAGE
CONFIG_SPL_CMT
CONFIG_SPL_CMT_DEBUG
CONFIG_SPL_COMMON_INIT_DDR
-CONFIG_SPL_CONSOLE
-CONFIG_SPL_ETH_DEVICE
CONFIG_SPL_FLUSH_IMAGE
CONFIG_SPL_FS_LOAD_ARGS_NAME
CONFIG_SPL_FS_LOAD_KERNEL_NAME
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
CONFIG_SPL_GD_ADDR
CONFIG_SPL_INIT_MINIMAL
-CONFIG_SPL_JR0_LIODN_NS
-CONFIG_SPL_JR0_LIODN_S
CONFIG_SPL_MAX_FOOTPRINT
-CONFIG_SPL_MAX_PEB_SIZE
CONFIG_SPL_MAX_SIZE
-CONFIG_SPL_MXS_PSWITCH_WAIT
CONFIG_SPL_NAND_INIT
CONFIG_SPL_NAND_MINIMAL
CONFIG_SPL_NAND_RAW_ONLY
CONFIG_SPL_NAND_SOFTECC
-CONFIG_SPL_NAND_WORKSPACE
CONFIG_SPL_PAD_TO
-CONFIG_SPL_PANIC_ON_RAW_IMAGE
CONFIG_SPL_PBL_PAD
-CONFIG_SPL_PPAACT_ADDR
CONFIG_SPL_RELOC_MALLOC_ADDR
CONFIG_SPL_RELOC_MALLOC_SIZE
CONFIG_SPL_RELOC_STACK
CONFIG_SPL_SATA_BOOT_DEVICE
CONFIG_SPL_SIZE
CONFIG_SPL_SKIP_RELOCATE
-CONFIG_SPL_SPAACT_ADDR
CONFIG_SPL_SPI_FLASH_MINIMAL
CONFIG_SPL_STACK
CONFIG_SPL_STACK_ADDR
CONFIG_SPL_STACK_SIZE
CONFIG_SPL_START_S_PATH
CONFIG_SPL_TARGET
-CONFIG_SPL_UBOOT_KEY_HASH
CONFIG_SRAM_BASE
CONFIG_SRAM_SIZE
CONFIG_SRIO1
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE
-CONFIG_SSE2
CONFIG_STACKBASE
CONFIG_STANDALONE_LOAD_ADDR
-CONFIG_STATIC_BOARD_REV
CONFIG_STD_DEVICES_SETTINGS
-CONFIG_SXNI855T
-CONFIG_SYSFS
-CONFIG_SYSMGR_ISWGRP_HANDOFF
CONFIG_SYS_64BIT
CONFIG_SYS_64BIT_LBA
CONFIG_SYS_83XX_DDR_USES_CS0
-CONFIG_SYS_ADDRESS_MAP_A
CONFIG_SYS_AMASK0
-CONFIG_SYS_AMASK0_FINAL
CONFIG_SYS_AMASK1
CONFIG_SYS_AMASK1_FINAL
CONFIG_SYS_AMASK2
CONFIG_SYS_AMASK2_FINAL
CONFIG_SYS_AMASK3
-CONFIG_SYS_AMASK3_FINAL
CONFIG_SYS_AMASK4
-CONFIG_SYS_AMASK5
CONFIG_SYS_AMASK6
CONFIG_SYS_AMASK7
CONFIG_SYS_AT91_MAIN_CLOCK
CONFIG_SYS_ATA_IDE1_OFFSET
CONFIG_SYS_ATA_REG_OFFSET
CONFIG_SYS_ATA_STRIDE
-CONFIG_SYS_ATMEL_CPU_NAME
CONFIG_SYS_AUTOLOAD
CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
CONFIG_SYS_AUXCORE_BOOTDATA
CONFIG_SYS_BCSR
CONFIG_SYS_BFTIC3_BASE
CONFIG_SYS_BFTIC3_SIZE
-CONFIG_SYS_BITBANG_PHY_PORT
-CONFIG_SYS_BITBANG_PHY_PORTS
CONFIG_SYS_BMAN_CENA_BASE
CONFIG_SYS_BMAN_CENA_SIZE
CONFIG_SYS_BMAN_CINH_BASE
CONFIG_SYS_BMAN_SP_CENA_SIZE
CONFIG_SYS_BMAN_SP_CINH_SIZE
CONFIG_SYS_BMAN_SWP_ISDR_REG
-CONFIG_SYS_BOARD_NAME
CONFIG_SYS_BOOK3E_HV
CONFIG_SYS_BOOTCOUNT_BE
CONFIG_SYS_BOOTCOUNT_LE
-CONFIG_SYS_BOOTFILE_PREFIX
CONFIG_SYS_BOOTMAPSZ
CONFIG_SYS_BOOTM_LEN
CONFIG_SYS_BOOTPARAMS_LEN
CONFIG_SYS_CACHE_ACR0
CONFIG_SYS_CACHE_ACR1
CONFIG_SYS_CACHE_ACR2
-CONFIG_SYS_CACHE_ACR3
-CONFIG_SYS_CACHE_ACR4
-CONFIG_SYS_CACHE_ACR5
-CONFIG_SYS_CACHE_ACR6
-CONFIG_SYS_CACHE_ACR7
CONFIG_SYS_CACHE_DCACR
CONFIG_SYS_CACHE_ICACR
CONFIG_SYS_CACHE_STASHING
-CONFIG_SYS_CADMUS_BASE_REG
CONFIG_SYS_CBSIZE
CONFIG_SYS_CCCR
CONFIG_SYS_CCSRBAR
CONFIG_SYS_CCSRBAR_PHYS_HIGH
CONFIG_SYS_CCSRBAR_PHYS_LOW
CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-CONFIG_SYS_CFI_FLASH_CONFIG_REGS
CONFIG_SYS_CFI_FLASH_STATUS_POLL
-CONFIG_SYS_CF_INTC_REG1
-CONFIG_SYS_CH7301_I2C
CONFIG_SYS_CKEN
CONFIG_SYS_CLK
CONFIG_SYS_CLKTL_CBCDR
-CONFIG_SYS_CLK_FREQ_C100
-CONFIG_SYS_CLK_FREQ_C110
-CONFIG_SYS_CMD_CONFIGURE
-CONFIG_SYS_CMD_EL
-CONFIG_SYS_CMD_IAS
-CONFIG_SYS_CMD_INT
-CONFIG_SYS_CMD_SUSPEND
CONFIG_SYS_CORE_SRAM
CONFIG_SYS_CORE_SRAM_SIZE
CONFIG_SYS_CPC_REINIT_F
CONFIG_SYS_CPLD_FTIM2
CONFIG_SYS_CPLD_FTIM3
CONFIG_SYS_CPLD_SIZE
-CONFIG_SYS_CPM_INTERRUPT
CONFIG_SYS_CPRI
CONFIG_SYS_CPRI_CLK
CONFIG_SYS_CPUSPEED
CONFIG_SYS_CS3_FTIM2
CONFIG_SYS_CS3_FTIM3
CONFIG_SYS_CS3_MASK
-CONFIG_SYS_CS4_BASE
-CONFIG_SYS_CS4_CTRL
CONFIG_SYS_CS4_FTIM0
CONFIG_SYS_CS4_FTIM1
CONFIG_SYS_CS4_FTIM2
CONFIG_SYS_CS4_FTIM3
-CONFIG_SYS_CS4_MASK
-CONFIG_SYS_CS5_BASE
-CONFIG_SYS_CS5_CTRL
-CONFIG_SYS_CS5_FTIM0
-CONFIG_SYS_CS5_FTIM1
-CONFIG_SYS_CS5_FTIM2
-CONFIG_SYS_CS5_FTIM3
-CONFIG_SYS_CS5_MASK
-CONFIG_SYS_CS6_BASE
-CONFIG_SYS_CS6_CTRL
CONFIG_SYS_CS6_FTIM0
CONFIG_SYS_CS6_FTIM1
CONFIG_SYS_CS6_FTIM2
CONFIG_SYS_CS6_FTIM3
-CONFIG_SYS_CS6_MASK
-CONFIG_SYS_CS7_BASE
-CONFIG_SYS_CS7_CTRL
CONFIG_SYS_CS7_FTIM0
CONFIG_SYS_CS7_FTIM1
CONFIG_SYS_CS7_FTIM2
CONFIG_SYS_CS7_FTIM3
-CONFIG_SYS_CS7_MASK
CONFIG_SYS_CSOR0
-CONFIG_SYS_CSOR0_EXT
CONFIG_SYS_CSOR1
-CONFIG_SYS_CSOR1_EXT
CONFIG_SYS_CSOR2
-CONFIG_SYS_CSOR2_EXT
CONFIG_SYS_CSOR3
-CONFIG_SYS_CSOR3_EXT
CONFIG_SYS_CSOR4
-CONFIG_SYS_CSOR4_EXT
-CONFIG_SYS_CSOR5
-CONFIG_SYS_CSOR5_EXT
CONFIG_SYS_CSOR6
-CONFIG_SYS_CSOR6_EXT
CONFIG_SYS_CSOR7
-CONFIG_SYS_CSOR7_EXT
CONFIG_SYS_CSPR0
CONFIG_SYS_CSPR0_EXT
CONFIG_SYS_CSPR0_FINAL
CONFIG_SYS_CSPR3_FINAL
CONFIG_SYS_CSPR4
CONFIG_SYS_CSPR4_EXT
-CONFIG_SYS_CSPR5
-CONFIG_SYS_CSPR5_EXT
CONFIG_SYS_CSPR6
CONFIG_SYS_CSPR6_EXT
CONFIG_SYS_CSPR7
CONFIG_SYS_DA850_DDR2_SDTIMR
CONFIG_SYS_DA850_DDR2_SDTIMR2
CONFIG_SYS_DA850_PLL0_PLLM
-CONFIG_SYS_DA850_PLL0_PREDIV
CONFIG_SYS_DA850_PLL1_PLLM
CONFIG_SYS_DA850_SYSCFG_SUSPSRC
-CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
CONFIG_SYS_DAVINCI_I2C_SLAVE
CONFIG_SYS_DAVINCI_I2C_SLAVE1
CONFIG_SYS_DAVINCI_I2C_SLAVE2
CONFIG_SYS_DAVINCI_I2C_SPEED
CONFIG_SYS_DAVINCI_I2C_SPEED1
CONFIG_SYS_DAVINCI_I2C_SPEED2
-CONFIG_SYS_DBAT0L
-CONFIG_SYS_DBAT0U
-CONFIG_SYS_DBAT1L
-CONFIG_SYS_DBAT1U
-CONFIG_SYS_DBAT2L
-CONFIG_SYS_DBAT2U
-CONFIG_SYS_DBAT3L
-CONFIG_SYS_DBAT3U
-CONFIG_SYS_DBAT4L
-CONFIG_SYS_DBAT4U
-CONFIG_SYS_DBAT5L
-CONFIG_SYS_DBAT5U
-CONFIG_SYS_DBAT6L
-CONFIG_SYS_DBAT6U
-CONFIG_SYS_DBAT7L
-CONFIG_SYS_DBAT7U
CONFIG_SYS_DCACHE_INV
CONFIG_SYS_DCSRBAR
CONFIG_SYS_DCSRBAR_PHYS
CONFIG_SYS_DCSR_DCFG_ADDR
CONFIG_SYS_DCSR_DCFG_OFFSET
CONFIG_SYS_DCU_ADDR
-CONFIG_SYS_DDR2_CS0_BNDS
-CONFIG_SYS_DDR2_CS0_CONFIG
-CONFIG_SYS_DDR2_CS1_BNDS
-CONFIG_SYS_DDR2_CS1_CONFIG
-CONFIG_SYS_DDR2_CS2_BNDS
-CONFIG_SYS_DDR2_CS2_CONFIG
-CONFIG_SYS_DDR2_CS3_BNDS
-CONFIG_SYS_DDR2_CS3_CONFIG
CONFIG_SYS_DDRCDR
CONFIG_SYS_DDRCDR_VALUE
-CONFIG_SYS_DDRD
-CONFIG_SYS_DDRTC
CONFIG_SYS_DDRUA
CONFIG_SYS_DDR_BLOCK1_SIZE
CONFIG_SYS_DDR_BLOCK2_BASE
CONFIG_SYS_DDR_CLK_CNTL
CONFIG_SYS_DDR_CLK_CONTROL
CONFIG_SYS_DDR_CLK_CTRL
-CONFIG_SYS_DDR_CLK_CTRL_1000
-CONFIG_SYS_DDR_CLK_CTRL_1200
CONFIG_SYS_DDR_CLK_CTRL_667
CONFIG_SYS_DDR_CLK_CTRL_800
-CONFIG_SYS_DDR_CLK_CTRL_900
CONFIG_SYS_DDR_CONFIG
CONFIG_SYS_DDR_CONFIG_2
CONFIG_SYS_DDR_CONFIG_256
CONFIG_SYS_DDR_CONTROL
CONFIG_SYS_DDR_CONTROL_2
-CONFIG_SYS_DDR_CPO
CONFIG_SYS_DDR_CS0_BNDS
CONFIG_SYS_DDR_CS0_CONFIG
CONFIG_SYS_DDR_CS0_CONFIG_2
CONFIG_SYS_DDR_CS1_BNDS
CONFIG_SYS_DDR_CS1_CONFIG
CONFIG_SYS_DDR_CS1_CONFIG_2
-CONFIG_SYS_DDR_CS2_BNDS
-CONFIG_SYS_DDR_CS2_CONFIG
-CONFIG_SYS_DDR_CS3_BNDS
-CONFIG_SYS_DDR_CS3_CONFIG
CONFIG_SYS_DDR_DATA_INIT
CONFIG_SYS_DDR_INIT_ADDR
CONFIG_SYS_DDR_INIT_EXT_ADDR
CONFIG_SYS_DDR_INTERVAL
-CONFIG_SYS_DDR_INTERVAL_1000
-CONFIG_SYS_DDR_INTERVAL_1200
CONFIG_SYS_DDR_INTERVAL_667
CONFIG_SYS_DDR_INTERVAL_800
-CONFIG_SYS_DDR_INTERVAL_900
CONFIG_SYS_DDR_MODE
CONFIG_SYS_DDR_MODE2
CONFIG_SYS_DDR_MODE_1
-CONFIG_SYS_DDR_MODE_1_1000
-CONFIG_SYS_DDR_MODE_1_1200
CONFIG_SYS_DDR_MODE_1_667
CONFIG_SYS_DDR_MODE_1_800
-CONFIG_SYS_DDR_MODE_1_900
CONFIG_SYS_DDR_MODE_2
-CONFIG_SYS_DDR_MODE_2_1000
-CONFIG_SYS_DDR_MODE_2_1200
CONFIG_SYS_DDR_MODE_2_667
CONFIG_SYS_DDR_MODE_2_800
-CONFIG_SYS_DDR_MODE_2_900
CONFIG_SYS_DDR_MODE_CONTROL
-CONFIG_SYS_DDR_MODE_WEAK
CONFIG_SYS_DDR_RAW_TIMING
CONFIG_SYS_DDR_RCW_1
CONFIG_SYS_DDR_RCW_2
CONFIG_SYS_DDR_SIZE
CONFIG_SYS_DDR_SR_CNTR
CONFIG_SYS_DDR_TIMING_0
-CONFIG_SYS_DDR_TIMING_0_1000
-CONFIG_SYS_DDR_TIMING_0_1200
CONFIG_SYS_DDR_TIMING_0_667
CONFIG_SYS_DDR_TIMING_0_800
-CONFIG_SYS_DDR_TIMING_0_900
CONFIG_SYS_DDR_TIMING_1
-CONFIG_SYS_DDR_TIMING_1_1000
-CONFIG_SYS_DDR_TIMING_1_1200
CONFIG_SYS_DDR_TIMING_1_667
CONFIG_SYS_DDR_TIMING_1_800
-CONFIG_SYS_DDR_TIMING_1_900
CONFIG_SYS_DDR_TIMING_2
-CONFIG_SYS_DDR_TIMING_2_1000
-CONFIG_SYS_DDR_TIMING_2_1200
CONFIG_SYS_DDR_TIMING_2_667
CONFIG_SYS_DDR_TIMING_2_800
-CONFIG_SYS_DDR_TIMING_2_900
CONFIG_SYS_DDR_TIMING_3
-CONFIG_SYS_DDR_TIMING_3_1000
-CONFIG_SYS_DDR_TIMING_3_1200
CONFIG_SYS_DDR_TIMING_3_667
CONFIG_SYS_DDR_TIMING_3_800
-CONFIG_SYS_DDR_TIMING_3_900
CONFIG_SYS_DDR_TIMING_4
CONFIG_SYS_DDR_TIMING_5
-CONFIG_SYS_DDR_WRITE_DATA_DELAY
-CONFIG_SYS_DDR_WRLVL_CNTL
CONFIG_SYS_DDR_WRLVL_CONTROL
CONFIG_SYS_DDR_WRLVL_CONTROL_667
CONFIG_SYS_DDR_WRLVL_CONTROL_800
-CONFIG_SYS_DDR_ZQ_CNTL
CONFIG_SYS_DDR_ZQ_CONTROL
CONFIG_SYS_DEBUG
CONFIG_SYS_DEBUG_SERVER_FW_ADDR
CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
-CONFIG_SYS_DEFAULT_VIDEO_MODE
CONFIG_SYS_DIALOG_PMIC_I2C_ADDR
-CONFIG_SYS_DIMM_SLOTS_PER_CTLR
-CONFIG_SYS_DIRECT_FLASH_NFS
CONFIG_SYS_DIRECT_FLASH_TFTP
CONFIG_SYS_DISCOVER_PHY
CONFIG_SYS_DIU_ADDR
-CONFIG_SYS_DP501_BASE
-CONFIG_SYS_DP501_DIFFERENTIAL
-CONFIG_SYS_DP501_I2C
-CONFIG_SYS_DP501_VCAPCTRL0
CONFIG_SYS_DPAA_DCE
CONFIG_SYS_DPAA_FMAN
CONFIG_SYS_DPAA_PME
CONFIG_SYS_DRAM_BASE
CONFIG_SYS_DRAM_SIZE
CONFIG_SYS_DRAM_TEST
-CONFIG_SYS_DSPI_CS0
-CONFIG_SYS_DSPI_CS2
CONFIG_SYS_DSPI_CTAR0
CONFIG_SYS_DSPI_CTAR1
CONFIG_SYS_DSPI_CTAR2
CONFIG_SYS_DSPI_CTAR3
CONFIG_SYS_DV_NOR_BOOT_CFG
-CONFIG_SYS_EBI_CFGR_VAL
-CONFIG_SYS_EBI_CSA_VAL
CONFIG_SYS_EEPROM_BUS_NUM
CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
CONFIG_SYS_EEPROM_WREN
CONFIG_SYS_EHCI_USB1_ADDR
-CONFIG_SYS_ELO3_DMA3
-CONFIG_SYS_EMAC_TI_CLKDIV
CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
CONFIG_SYS_ENET_BD_BASE
-CONFIG_SYS_ENV_ADDR
CONFIG_SYS_ENV_SECT_SIZE
CONFIG_SYS_ETHOC_BASE
CONFIG_SYS_ETHOC_BUFFER_ADDR
CONFIG_SYS_EXCEPTION_VECTORS_HIGH
CONFIG_SYS_FAST_CLK
CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-CONFIG_SYS_FAULT_MII_ADDR
CONFIG_SYS_FDT_BASE
CONFIG_SYS_FDT_PAD
-CONFIG_SYS_FEC0_IOBASE
-CONFIG_SYS_FEC1_IOBASE
CONFIG_SYS_FECI2C
CONFIG_SYS_FEC_BUF_USE_SRAM
-CONFIG_SYS_FIXED_PHY_ADDR
-CONFIG_SYS_FIXED_PHY_PORT
-CONFIG_SYS_FIXED_PHY_PORTS
CONFIG_SYS_FLASH0
CONFIG_SYS_FLASH1
CONFIG_SYS_FLASH1_BASE_PHYS
CONFIG_SYS_FLASH1_BASE_PHYS_EARLY
-CONFIG_SYS_FLASHBOOT
-CONFIG_SYS_FLASH_AUTOPROTECT_LIST
CONFIG_SYS_FLASH_BANKS_LIST
CONFIG_SYS_FLASH_BANKS_SIZES
CONFIG_SYS_FLASH_BASE
CONFIG_SYS_FLASH_BASE_PHYS
CONFIG_SYS_FLASH_BASE_PHYS_EARLY
CONFIG_SYS_FLASH_BR_PRELIM
-CONFIG_SYS_FLASH_CFI_AMD_RESET
CONFIG_SYS_FLASH_CFI_NONBLOCK
CONFIG_SYS_FLASH_CFI_WIDTH
CONFIG_SYS_FLASH_CHECKSUM
-CONFIG_SYS_FLASH_CHECK_BLANK_BEFORE_ERASE
CONFIG_SYS_FLASH_EMPTY_INFO
CONFIG_SYS_FLASH_ERASE_TOUT
-CONFIG_SYS_FLASH_LEGACY_256Kx8
-CONFIG_SYS_FLASH_LEGACY_512Kx16
-CONFIG_SYS_FLASH_LEGACY_512Kx8
CONFIG_SYS_FLASH_LOCK_TOUT
CONFIG_SYS_FLASH_OR_PRELIM
CONFIG_SYS_FLASH_PARMSECT_SZ
CONFIG_SYS_FLASH_SECT_SZ
CONFIG_SYS_FLASH_SIZE
CONFIG_SYS_FLASH_UNLOCK_TOUT
-CONFIG_SYS_FLASH_VERIFY_AFTER_WRITE
CONFIG_SYS_FLASH_WRITE_TOUT
CONFIG_SYS_FLYCNFG_VAL
CONFIG_SYS_FM1_10GEC1_PHY_ADDR
CONFIG_SYS_FM1_CLK
-CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR
CONFIG_SYS_FM1_DTSEC1_PHY_ADDR
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
CONFIG_SYS_FM1_DTSEC2_PHY_ADDR
CONFIG_SYS_FM1_DTSEC4_PHY_ADDR
CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR
CONFIG_SYS_FM1_DTSEC5_PHY_ADDR
-CONFIG_SYS_FM1_DTSEC_MDIO_ADDR
CONFIG_SYS_FM1_QSGMII11_PHY_ADDR
CONFIG_SYS_FM1_QSGMII21_PHY_ADDR
-CONFIG_SYS_FM1_TGEC_MDIO_ADDR
CONFIG_SYS_FM2_10GEC1_PHY_ADDR
CONFIG_SYS_FM2_CLK
CONFIG_SYS_FM2_DTSEC1_PHY_ADDR
CONFIG_SYS_FM2_DTSEC2_PHY_ADDR
CONFIG_SYS_FM2_DTSEC3_PHY_ADDR
CONFIG_SYS_FM2_DTSEC4_PHY_ADDR
-CONFIG_SYS_FM2_DTSEC_MDIO_ADDR
-CONFIG_SYS_FM2_TGEC_MDIO_ADDR
CONFIG_SYS_FMAN_V3
CONFIG_SYS_FM_MURAM_SIZE
-CONFIG_SYS_FORM_3U_CPCI
-CONFIG_SYS_FORM_3U_VPX
-CONFIG_SYS_FORM_6U_CPCI
-CONFIG_SYS_FORM_6U_VPX
-CONFIG_SYS_FORM_AMC
-CONFIG_SYS_FORM_ATCA_AMC
-CONFIG_SYS_FORM_ATCA_PMC
-CONFIG_SYS_FORM_CUSTOM
-CONFIG_SYS_FORM_PCI
-CONFIG_SYS_FORM_PCI_EXPRESS
-CONFIG_SYS_FORM_PMC
-CONFIG_SYS_FORM_PMC_XMC
-CONFIG_SYS_FORM_VME
-CONFIG_SYS_FORM_XMC
CONFIG_SYS_FPGAREG_DATE
CONFIG_SYS_FPGAREG_DIPSW
CONFIG_SYS_FPGAREG_FREQ
CONFIG_SYS_FPGAREG_RESET_CODE
CONFIG_SYS_FPGA_AMASK
CONFIG_SYS_FPGA_BASE
-CONFIG_SYS_FPGA_CHECK_BUSY
-CONFIG_SYS_FPGA_CHECK_CTRLC
-CONFIG_SYS_FPGA_CHECK_ERROR
-CONFIG_SYS_FPGA_COUNT
CONFIG_SYS_FPGA_CSOR
CONFIG_SYS_FPGA_CSPR
CONFIG_SYS_FPGA_CSPR_EXT
CONFIG_SYS_FPGA_FTIM1
CONFIG_SYS_FPGA_FTIM2
CONFIG_SYS_FPGA_FTIM3
-CONFIG_SYS_FPGA_NO_RFL_HI
CONFIG_SYS_FPGA_PROG_FEEDBACK
-CONFIG_SYS_FPGA_PROG_TIME
CONFIG_SYS_FPGA_SIZE
CONFIG_SYS_FPGA_WAIT
-CONFIG_SYS_FPGA_WAIT_BUSY
-CONFIG_SYS_FPGA_WAIT_CONFIG
-CONFIG_SYS_FPGA_WAIT_INIT
-CONFIG_SYS_FSL_AIOP1_BASE
-CONFIG_SYS_FSL_AIOP1_SIZE
-CONFIG_SYS_FSL_B4860QDS_XFI_ERR
CONFIG_SYS_FSL_BMAN_ADDR
CONFIG_SYS_FSL_BMAN_OFFSET
-CONFIG_SYS_FSL_CCSR_BASE
CONFIG_SYS_FSL_CCSR_GUR_BE
CONFIG_SYS_FSL_CCSR_GUR_LE
CONFIG_SYS_FSL_CCSR_SCFG_BE
CONFIG_SYS_FSL_CCSR_SCFG_LE
-CONFIG_SYS_FSL_CCSR_SIZE
CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR
CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR
CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR
CONFIG_SYS_FSL_CPC_OFFSET
CONFIG_SYS_FSL_CSU_ADDR
CONFIG_SYS_FSL_DCFG_ADDR
-CONFIG_SYS_FSL_DCSR_BASE
CONFIG_SYS_FSL_DCSR_DDR2_ADDR
CONFIG_SYS_FSL_DCSR_DDR3_ADDR
CONFIG_SYS_FSL_DCSR_DDR4_ADDR
CONFIG_SYS_FSL_DCSR_DDR_ADDR
-CONFIG_SYS_FSL_DCSR_SIZE
CONFIG_SYS_FSL_DCU_BE
CONFIG_SYS_FSL_DCU_LE
CONFIG_SYS_FSL_DDR2_ADDR
-CONFIG_SYS_FSL_DDR3L
CONFIG_SYS_FSL_DDR3_ADDR
CONFIG_SYS_FSL_DDR_ADDR
CONFIG_SYS_FSL_DDR_EMU
CONFIG_SYS_FSL_DDR_INTLV_256B
CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
-CONFIG_SYS_FSL_DRAM_BASE1
-CONFIG_SYS_FSL_DRAM_BASE2
-CONFIG_SYS_FSL_DRAM_BASE3
-CONFIG_SYS_FSL_DRAM_SIZE1
-CONFIG_SYS_FSL_DRAM_SIZE2
-CONFIG_SYS_FSL_DRAM_SIZE3
CONFIG_SYS_FSL_DSPI_BE
CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR
CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
CONFIG_SYS_FSL_ERRATUM_A008751
-CONFIG_SYS_FSL_ERRATUM_A_004934
CONFIG_SYS_FSL_ESDHC_ADDR
CONFIG_SYS_FSL_ESDHC_BE
CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
CONFIG_SYS_FSL_ESDHC_LE
CONFIG_SYS_FSL_ESDHC_NUM
CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
-CONFIG_SYS_FSL_ESDHC_USE_PIO
CONFIG_SYS_FSL_FM
CONFIG_SYS_FSL_FM1_ADDR
CONFIG_SYS_FSL_FM1_DTSEC1_ADDR
CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET
CONFIG_SYS_FSL_FMAN_ADDR
CONFIG_SYS_FSL_GUTS_ADDR
-CONFIG_SYS_FSL_I2C
-CONFIG_SYS_FSL_IFC_BASE
-CONFIG_SYS_FSL_IFC_BASE1
-CONFIG_SYS_FSL_IFC_BASE2
CONFIG_SYS_FSL_IFC_BE
CONFIG_SYS_FSL_IFC_LE
-CONFIG_SYS_FSL_IFC_SIZE
-CONFIG_SYS_FSL_IFC_SIZE1
-CONFIG_SYS_FSL_IFC_SIZE1_1
-CONFIG_SYS_FSL_IFC_SIZE2
CONFIG_SYS_FSL_ISBC_VER
CONFIG_SYS_FSL_JR0_ADDR
CONFIG_SYS_FSL_JR0_OFFSET
CONFIG_SYS_FSL_LS1_CLK_ADDR
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR
CONFIG_SYS_FSL_MAX_NUM_OF_SEC
-CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR
-CONFIG_SYS_FSL_MC_BASE
-CONFIG_SYS_FSL_MC_SIZE
-CONFIG_SYS_FSL_NI_BASE
-CONFIG_SYS_FSL_NI_SIZE
-CONFIG_SYS_FSL_NO_SERDES
CONFIG_SYS_FSL_NUM_CC_PLL
CONFIG_SYS_FSL_NUM_CC_PLLS
CONFIG_SYS_FSL_OCRAM_BASE
CONFIG_SYS_FSL_PAMU_OFFSET
CONFIG_SYS_FSL_PCIE_COMPAT
CONFIG_SYS_FSL_PCI_VER_3_X
-CONFIG_SYS_FSL_PEBUF_BASE
-CONFIG_SYS_FSL_PEBUF_SIZE
CONFIG_SYS_FSL_PEX_LUT_BE
CONFIG_SYS_FSL_PEX_LUT_LE
CONFIG_SYS_FSL_PMIC_I2C_ADDR
CONFIG_SYS_FSL_PMU_ADDR
CONFIG_SYS_FSL_PMU_CLTBENR
-CONFIG_SYS_FSL_QBMAN_BASE
-CONFIG_SYS_FSL_QBMAN_SIZE
-CONFIG_SYS_FSL_QBMAN_SIZE_1
CONFIG_SYS_FSL_QMAN_ADDR
CONFIG_SYS_FSL_QMAN_OFFSET
CONFIG_SYS_FSL_QMAN_V3
CONFIG_SYS_FSL_QSPI_BASE
-CONFIG_SYS_FSL_QSPI_BASE1
-CONFIG_SYS_FSL_QSPI_BASE2
CONFIG_SYS_FSL_QSPI_LE
-CONFIG_SYS_FSL_QSPI_SIZE
-CONFIG_SYS_FSL_QSPI_SIZE1
-CONFIG_SYS_FSL_QSPI_SIZE2
CONFIG_SYS_FSL_RAID_ENGINE
CONFIG_SYS_FSL_RAID_ENGINE_ADDR
CONFIG_SYS_FSL_RAID_ENGINE_OFFSET
CONFIG_SYS_FSL_SRK_LE
CONFIG_SYS_FSL_TBCLK_DIV
CONFIG_SYS_FSL_TIMER_ADDR
-CONFIG_SYS_FSL_USB1_ADDR
CONFIG_SYS_FSL_USB1_PHY_ENABLE
-CONFIG_SYS_FSL_USB2_ADDR
CONFIG_SYS_FSL_USB2_PHY_ENABLE
-CONFIG_SYS_FSL_USB_CTRL_PHY_EN
-CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN
CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
-CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE
-CONFIG_SYS_FSL_USB_HS_DISCNCT_INC
-CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN
CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV
-CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN
-CONFIG_SYS_FSL_USB_PLLPRG2_MFI
-CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK
-CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN
-CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN
-CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN
-CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV
-CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK
-CONFIG_SYS_FSL_USB_PWRFLT_CR_EN
-CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL
-CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK
-CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0
-CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3
-CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0
-CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3
-CONFIG_SYS_FSL_USB_SYS_CLK_VALID
-CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN
-CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK
CONFIG_SYS_FSL_USDHC_NUM
CONFIG_SYS_FSL_WDOG_BE
CONFIG_SYS_FSL_WRIOP1_ADDR
-CONFIG_SYS_FSL_WRIOP1_BASE
CONFIG_SYS_FSL_WRIOP1_MDIO1
CONFIG_SYS_FSL_WRIOP1_MDIO2
-CONFIG_SYS_FSL_WRIOP1_SIZE
-CONFIG_SYS_FSL_XHCI_USB1_ADDR
-CONFIG_SYS_FSL_XHCI_USB2_ADDR
-CONFIG_SYS_FSL_XHCI_USB3_ADDR
-CONFIG_SYS_FSMC_BASE
-CONFIG_SYS_FSMC_NAND_16BIT
-CONFIG_SYS_FSMC_NAND_8BIT
CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS
CONFIG_SYS_GPDR1_VAL
CONFIG_SYS_GPDR2_VAL
CONFIG_SYS_GPDR3_VAL
-CONFIG_SYS_GPIO1_DAT
-CONFIG_SYS_GPIO1_DIR
CONFIG_SYS_GPIO1_EN
CONFIG_SYS_GPIO1_FUNC
CONFIG_SYS_GPIO1_LED
CONFIG_SYS_GPIO1_OUT
-CONFIG_SYS_GPIO1_PRELIM
-CONFIG_SYS_GPIO2_DAT
-CONFIG_SYS_GPIO2_DIR
-CONFIG_SYS_GPIO2_PRELIM
CONFIG_SYS_GPIO_EN
CONFIG_SYS_GPIO_FUNC
CONFIG_SYS_GPIO_OUT
CONFIG_SYS_GPSR2_VAL
CONFIG_SYS_GPSR3_VAL
CONFIG_SYS_HALT_BEFOR_RAM_JUMP
-CONFIG_SYS_HELP_CMD_WIDTH
-CONFIG_SYS_HIGH
CONFIG_SYS_HMI_BASE
-CONFIG_SYS_HRCW_HIGH
-CONFIG_SYS_HRCW_LOW
CONFIG_SYS_HZ_CLOCK
-CONFIG_SYS_I2C2_FSL_OFFSET
-CONFIG_SYS_I2C2_OFFSET
-CONFIG_SYS_I2C2_PINMUX_CLR
-CONFIG_SYS_I2C2_PINMUX_REG
-CONFIG_SYS_I2C2_PINMUX_SET
-CONFIG_SYS_I2C_0
-CONFIG_SYS_I2C_2
-CONFIG_SYS_I2C_5
-CONFIG_SYS_I2C_BASE0
-CONFIG_SYS_I2C_BASE1
-CONFIG_SYS_I2C_BASE2
-CONFIG_SYS_I2C_BASE3
-CONFIG_SYS_I2C_BASE4
-CONFIG_SYS_I2C_BASE5
CONFIG_SYS_I2C_BUSES
-CONFIG_SYS_I2C_CLK_OFFSET
-CONFIG_SYS_I2C_DIRECT_BUS
CONFIG_SYS_I2C_DVI_ADDR
CONFIG_SYS_I2C_DVI_BUS_NUM
CONFIG_SYS_I2C_EEPROM_CCID
CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS
CONFIG_SYS_I2C_EXPANDER_ADDR
CONFIG_SYS_I2C_FPGA_ADDR
-CONFIG_SYS_I2C_FRAM
CONFIG_SYS_I2C_G762_ADDR
CONFIG_SYS_I2C_IFDR_DIV
CONFIG_SYS_I2C_INIT_BOARD
CONFIG_SYS_I2C_LDI_ADDR
-CONFIG_SYS_I2C_LPC32XX_SLAVE
-CONFIG_SYS_I2C_LPC32XX_SPEED
CONFIG_SYS_I2C_MAX_HOPS
CONFIG_SYS_I2C_NOPROBES
CONFIG_SYS_I2C_PCA953X_ADDR
CONFIG_SYS_I2C_RTC_ADDR
CONFIG_SYS_I2C_TCA642X_ADDR
CONFIG_SYS_I2C_TCA642X_BUS_NUM
-CONFIG_SYS_IBAT0L
-CONFIG_SYS_IBAT0U
-CONFIG_SYS_IBAT1L
-CONFIG_SYS_IBAT1U
-CONFIG_SYS_IBAT2L
-CONFIG_SYS_IBAT2U
-CONFIG_SYS_IBAT3L
-CONFIG_SYS_IBAT3U
-CONFIG_SYS_IBAT4L
-CONFIG_SYS_IBAT4U
-CONFIG_SYS_IBAT5L
-CONFIG_SYS_IBAT5U
-CONFIG_SYS_IBAT6L
-CONFIG_SYS_IBAT6U
-CONFIG_SYS_IBAT7L
-CONFIG_SYS_IBAT7U
CONFIG_SYS_ICACHE_INV
-CONFIG_SYS_ICS8N3QV01_I2C
CONFIG_SYS_IDE_MAXBUS
CONFIG_SYS_IDE_MAXDEVICE
CONFIG_SYS_IFC_ADDR
CONFIG_SYS_INIT_SP_OFFSET
CONFIG_SYS_INPUT_CLKSRC
CONFIG_SYS_INTERLAKEN
-CONFIG_SYS_INTR_BASE
CONFIG_SYS_INT_FLASH_BASE
CONFIG_SYS_INT_FLASH_ENABLE
CONFIG_SYS_IO_BASE
-CONFIG_SYS_ISA_BASE
CONFIG_SYS_ISA_IO
CONFIG_SYS_ISA_IO_BASE_ADDRESS
-CONFIG_SYS_ISA_MEM
CONFIG_SYS_JFFS2_FIRST_BANK
CONFIG_SYS_JFFS2_FIRST_SECTOR
CONFIG_SYS_JFFS2_NUM_BANKS
-CONFIG_SYS_JFFS2_SORT_FRAGMENTS
CONFIG_SYS_KMBEC_FPGA_BASE
CONFIG_SYS_KMBEC_FPGA_SIZE
-CONFIG_SYS_KWD_CONFIG
CONFIG_SYS_L2_PL310
CONFIG_SYS_L2_SIZE
CONFIG_SYS_L3_SIZE
CONFIG_SYS_LDB_CLOCK
CONFIG_SYS_LIME_BASE
CONFIG_SYS_LIME_SIZE
-CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE
CONFIG_SYS_LOADS_BAUD_CHANGE
CONFIG_SYS_LOW
CONFIG_SYS_LOWMEM_BASE
-CONFIG_SYS_LOW_RES_TIMER
CONFIG_SYS_LPAE_SDRAM_BASE
CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH
CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS
-CONFIG_SYS_LS_MC_DPC_IN_DDR
CONFIG_SYS_LS_MC_DPC_MAX_LENGTH
-CONFIG_SYS_LS_MC_DPL_IN_DDR
CONFIG_SYS_LS_MC_DPL_MAX_LENGTH
CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE
CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
-CONFIG_SYS_LS_MC_FW_IN_DDR
-CONFIG_SYS_LS_PPA_FW_IN_xxx
CONFIG_SYS_M41T11_BASE_YEAR
-CONFIG_SYS_M41T11_EXT_CENTURY_DATA
CONFIG_SYS_MAIN_PWR_ON
CONFIG_SYS_MALLOC_SIMPLE
CONFIG_SYS_MAMR
CONFIG_SYS_MASTER_CLOCK
CONFIG_SYS_MATRIX_EBI0CSA_VAL
CONFIG_SYS_MATRIX_EBICSA_VAL
-CONFIG_SYS_MATRIX_MCFG_REMAP
CONFIG_SYS_MAXARGS
CONFIG_SYS_MAX_FLASH_BANKS
CONFIG_SYS_MAX_FLASH_BANKS_DETECT
CONFIG_SYS_MAX_I2C_BUS
CONFIG_SYS_MAX_NAND_CHIPS
CONFIG_SYS_MAX_NAND_DEVICE
-CONFIG_SYS_MAX_PCI_EPS
CONFIG_SYS_MBAR
CONFIG_SYS_MBAR2
CONFIG_SYS_MCATT0_VAL
CONFIG_SYS_MCATT1_VAL
CONFIG_SYS_MCFRRTC_BASE
-CONFIG_SYS_MCFRTC_BASE
-CONFIG_SYS_MCF_SYNCR
CONFIG_SYS_MCIO0_VAL
CONFIG_SYS_MCIO1_VAL
CONFIG_SYS_MCKR
CONFIG_SYS_MCKR1_VAL
CONFIG_SYS_MCKR2_VAL
CONFIG_SYS_MCKR_CSS
-CONFIG_SYS_MCKR_VAL
CONFIG_SYS_MCMEM0_VAL
CONFIG_SYS_MCMEM1_VAL
CONFIG_SYS_MDCNFG_VAL
CONFIG_SYS_MDIO1_OFFSET
-CONFIG_SYS_MDIO_BASE_ADDR
CONFIG_SYS_MDMRS_VAL
CONFIG_SYS_MDREFR_VAL
CONFIG_SYS_MECR_VAL
CONFIG_SYS_MEMAC_LITTLE_ENDIAN
CONFIG_SYS_MEMORY_BASE
CONFIG_SYS_MEMORY_SIZE
-CONFIG_SYS_MEM_MAP
CONFIG_SYS_MEM_RESERVE_SECURE
CONFIG_SYS_MEM_SIZE
CONFIG_SYS_MEM_TOP_HIDE
CONFIG_SYS_MFD
CONFIG_SYS_MHZ
-CONFIG_SYS_MII_MODE
CONFIG_SYS_MIPS_TIMER_FREQ
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
CONFIG_SYS_MPC83xx_ESDHC_OFFSET
CONFIG_SYS_MPC83xx_USB1_ADDR
CONFIG_SYS_MPC83xx_USB1_OFFSET
-CONFIG_SYS_MPC83xx_USB2_ADDR
-CONFIG_SYS_MPC83xx_USB2_OFFSET
CONFIG_SYS_MPC85XX_NO_RESETVEC
CONFIG_SYS_MPC85xx_CPM_ADDR
CONFIG_SYS_MPC85xx_CPM_OFFSET
CONFIG_SYS_MPC8xxx_DDR2_OFFSET
CONFIG_SYS_MPC8xxx_DDR3_OFFSET
CONFIG_SYS_MPC8xxx_DDR_OFFSET
-CONFIG_SYS_MPC8xxx_GUTS_ADDR
CONFIG_SYS_MPC8xxx_PIC_ADDR
-CONFIG_SYS_MPC92469AC
CONFIG_SYS_MRAM_BASE
CONFIG_SYS_MRAM_SIZE
CONFIG_SYS_MSC0_VAL
CONFIG_SYS_MSC1_VAL
CONFIG_SYS_MSC2_VAL
-CONFIG_SYS_MX5_CLK32
-CONFIG_SYS_MX5_HCLK
-CONFIG_SYS_MX6_CLK32
-CONFIG_SYS_MX6_HCLK
-CONFIG_SYS_MX7_CLK32
-CONFIG_SYS_MX7_HCLK
-CONFIG_SYS_MXS_VDD5V_ONLY
CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
-CONFIG_SYS_NAND_ACTL_ALE
-CONFIG_SYS_NAND_ACTL_CLE
-CONFIG_SYS_NAND_ACTL_DELAY
-CONFIG_SYS_NAND_ACTL_NCE
-CONFIG_SYS_NAND_ALE
CONFIG_SYS_NAND_AMASK
CONFIG_SYS_NAND_BASE
CONFIG_SYS_NAND_BASE2
CONFIG_SYS_NAND_BASE_LIST
CONFIG_SYS_NAND_BASE_PHYS
-CONFIG_SYS_NAND_BOOT
CONFIG_SYS_NAND_BR_PRELIM
-CONFIG_SYS_NAND_BUSWIDTH_16
-CONFIG_SYS_NAND_CLE
CONFIG_SYS_NAND_CS
CONFIG_SYS_NAND_CSOR
CONFIG_SYS_NAND_CSPR
CONFIG_SYS_NAND_CSPR_EXT
CONFIG_SYS_NAND_DATA_BASE
-CONFIG_SYS_NAND_DBW_16
CONFIG_SYS_NAND_DBW_8
CONFIG_SYS_NAND_DDR_LAW
CONFIG_SYS_NAND_ECCBYTES
CONFIG_SYS_NAND_HW_ECC
CONFIG_SYS_NAND_HW_ECC_OOBFIRST
CONFIG_SYS_NAND_LARGEPAGE
-CONFIG_SYS_NAND_LBLAWAR_PRELIM
-CONFIG_SYS_NAND_LBLAWBAR_PRELIM
CONFIG_SYS_NAND_MASK_ALE
CONFIG_SYS_NAND_MASK_CLE
CONFIG_SYS_NAND_MAX_ECCPOS
CONFIG_SYS_NAND_OR_PRELIM
CONFIG_SYS_NAND_PAGE_2K
CONFIG_SYS_NAND_PAGE_4K
-CONFIG_SYS_NAND_QUIET
CONFIG_SYS_NAND_READY_PIN
CONFIG_SYS_NAND_REGS_BASE
-CONFIG_SYS_NAND_SELECT_DEVICE
CONFIG_SYS_NAND_SIZE
CONFIG_SYS_NAND_SPL_KERNEL_OFFS
CONFIG_SYS_NAND_U_BOOT_DST
CONFIG_SYS_NOR_FTIM2
CONFIG_SYS_NOR_FTIM3
CONFIG_SYS_NS16550_CLK
-CONFIG_SYS_NS16550_CLK_DIV
CONFIG_SYS_NS16550_COM1
CONFIG_SYS_NS16550_COM2
CONFIG_SYS_NS16550_COM3
CONFIG_SYS_NS16550_COM4
CONFIG_SYS_NS16550_COM5
CONFIG_SYS_NS16550_COM6
-CONFIG_SYS_NS16550_IER
CONFIG_SYS_NS16550_MEM32
CONFIG_SYS_NS16550_PORT_MAPPED
CONFIG_SYS_NS16550_REG_SIZE
CONFIG_SYS_NUM_FM2_DTSEC
CONFIG_SYS_NUM_FMAN
CONFIG_SYS_NUM_I2C_BUSES
-CONFIG_SYS_NUM_IRQS
-CONFIG_SYS_NVRAM_ACCESS_ROUTINE
CONFIG_SYS_NVRAM_BASE_ADDR
CONFIG_SYS_NVRAM_SIZE
CONFIG_SYS_OBIR
-CONFIG_SYS_OHCI_BE_CONTROLLER
CONFIG_SYS_OHCI_SWAP_REG_ACCESS
CONFIG_SYS_OMAP_ABE_SYSCK
CONFIG_SYS_ONENAND_BASE
CONFIG_SYS_ONENAND_BLOCK_SIZE
-CONFIG_SYS_ONENAND_PAGE_SIZE
-CONFIG_SYS_OR0_REMAP
-CONFIG_SYS_OR1_REMAP
CONFIG_SYS_OR_TIMING_MRAM
CONFIG_SYS_OSCIN_FREQ
-CONFIG_SYS_OSD_DH
CONFIG_SYS_OSPR_OFFSET
CONFIG_SYS_PACNT
CONFIG_SYS_PADAT
CONFIG_SYS_PBI_FLASH_BASE
CONFIG_SYS_PBI_FLASH_WINDOW
CONFIG_SYS_PBSIZE
-CONFIG_SYS_PCA953X_NVM_WP
CONFIG_SYS_PCCNT
CONFIG_SYS_PCDAT
CONFIG_SYS_PCDDR
CONFIG_SYS_PCI1_MEM_SIZE
CONFIG_SYS_PCI1_MEM_VIRT
CONFIG_SYS_PCI2_ADDR
-CONFIG_SYS_PCI64_MEMORY_BUS
CONFIG_SYS_PCIE
CONFIG_SYS_PCIE1_ADDR
CONFIG_SYS_PCIE1_BASE
CONFIG_SYS_PCIE1_MEM_PHYS
CONFIG_SYS_PCIE1_MEM_SIZE
CONFIG_SYS_PCIE1_MEM_VIRT
-CONFIG_SYS_PCIE1_NAME
CONFIG_SYS_PCIE1_PHYS_ADDR
CONFIG_SYS_PCIE1_PHYS_BASE
-CONFIG_SYS_PCIE1_PHYS_SIZE
CONFIG_SYS_PCIE1_VIRT_ADDR
CONFIG_SYS_PCIE2_ADDR
CONFIG_SYS_PCIE2_BASE
CONFIG_SYS_PCIE2_MEM_PHYS
CONFIG_SYS_PCIE2_MEM_SIZE
CONFIG_SYS_PCIE2_MEM_VIRT
-CONFIG_SYS_PCIE2_NAME
CONFIG_SYS_PCIE2_PHYS_ADDR
CONFIG_SYS_PCIE2_PHYS_BASE
-CONFIG_SYS_PCIE2_PHYS_SIZE
CONFIG_SYS_PCIE2_VIRT_ADDR
CONFIG_SYS_PCIE3_ADDR
CONFIG_SYS_PCIE3_IO_PHYS
CONFIG_SYS_PCIE3_IO_VIRT
CONFIG_SYS_PCIE3_MEM_PHYS
CONFIG_SYS_PCIE3_MEM_VIRT
-CONFIG_SYS_PCIE3_NAME
CONFIG_SYS_PCIE3_PHYS_ADDR
CONFIG_SYS_PCIE3_PHYS_SIZE
CONFIG_SYS_PCIE4_ADDR
CONFIG_SYS_PCIE4_MEM_BUS
CONFIG_SYS_PCIE4_MEM_PHYS
CONFIG_SYS_PCIE4_MEM_VIRT
-CONFIG_SYS_PCIE4_NAME
CONFIG_SYS_PCIE4_PHYS_ADDR
-CONFIG_SYS_PCIE4_PHYS_SIZE
CONFIG_SYS_PCIE_MMAP_SIZE
-CONFIG_SYS_PCI_BAR0
-CONFIG_SYS_PCI_BAR1
-CONFIG_SYS_PCI_BAR2
-CONFIG_SYS_PCI_BAR3
-CONFIG_SYS_PCI_BAR4
-CONFIG_SYS_PCI_BAR5
-CONFIG_SYS_PCI_CACHE_LINE_SIZE
-CONFIG_SYS_PCI_CFG_PHYS
-CONFIG_SYS_PCI_EP_MEMORY_BASE
CONFIG_SYS_PCI_IO_BASE
-CONFIG_SYS_PCI_IO_BUS
CONFIG_SYS_PCI_IO_PHYS
CONFIG_SYS_PCI_IO_SIZE
CONFIG_SYS_PCI_MAP_END
CONFIG_SYS_PCI_MAP_START
-CONFIG_SYS_PCI_MEMORY_BUS
-CONFIG_SYS_PCI_MEMORY_PHYS
-CONFIG_SYS_PCI_MEMORY_SIZE
CONFIG_SYS_PCI_MEM_BASE
-CONFIG_SYS_PCI_MEM_BUS
CONFIG_SYS_PCI_MEM_PHYS
CONFIG_SYS_PCI_MEM_SIZE
CONFIG_SYS_PCI_MMIO_BASE
CONFIG_SYS_PCI_MMIO_PHYS
CONFIG_SYS_PCI_MMIO_SIZE
-CONFIG_SYS_PCI_NR_INBOUND_WIN
CONFIG_SYS_PCI_SLV_MEM_BUS
CONFIG_SYS_PCI_SLV_MEM_LOCAL
CONFIG_SYS_PCI_SLV_MEM_SIZE
-CONFIG_SYS_PCI_SYS_MEM_BUS
-CONFIG_SYS_PCI_SYS_MEM_PHYS
-CONFIG_SYS_PCI_SYS_MEM_SIZE
-CONFIG_SYS_PCI_TBATR0
-CONFIG_SYS_PCI_TBATR1
-CONFIG_SYS_PCI_TBATR2
-CONFIG_SYS_PCI_TBATR3
-CONFIG_SYS_PCI_TBATR4
-CONFIG_SYS_PCI_TBATR5
CONFIG_SYS_PDCNT
CONFIG_SYS_PEHLPAR
-CONFIG_SYS_PEPAR
-CONFIG_SYS_PFPAR
-CONFIG_SYS_PHY_UBOOT_BASE
-CONFIG_SYS_PIOC_ASR_VAL
-CONFIG_SYS_PIOC_BSR_VAL
CONFIG_SYS_PIOC_PDR_VAL
CONFIG_SYS_PIOC_PDR_VAL1
CONFIG_SYS_PIOC_PPUDR_VAL
CONFIG_SYS_PIOD_PDR_VAL1
CONFIG_SYS_PIOD_PPUDR_VAL
CONFIG_SYS_PIO_MODE
-CONFIG_SYS_PIXIS_VBOOT_ENABLE
-CONFIG_SYS_PIXIS_VBOOT_MASK
-CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
CONFIG_SYS_PJPAR
CONFIG_SYS_PL310_BASE
CONFIG_SYS_PLLAR_VAL
-CONFIG_SYS_PLLBR_VAL
CONFIG_SYS_PLLCR
CONFIG_SYS_PLL_BYPASS
CONFIG_SYS_PLL_FDR
CONFIG_SYS_PMC_BASE
CONFIG_SYS_PMC_BASE_PHYS
CONFIG_SYS_PME_CLK
-CONFIG_SYS_PORTTC
-CONFIG_SYS_POST_BSPEC1
-CONFIG_SYS_POST_BSPEC2
-CONFIG_SYS_POST_BSPEC3
-CONFIG_SYS_POST_BSPEC4
-CONFIG_SYS_POST_BSPEC5
-CONFIG_SYS_POST_CACHE
-CONFIG_SYS_POST_CODEC
-CONFIG_SYS_POST_COPROC
-CONFIG_SYS_POST_CPU
-CONFIG_SYS_POST_DSP
-CONFIG_SYS_POST_ECC
-CONFIG_SYS_POST_ETHER
-CONFIG_SYS_POST_FLASH
-CONFIG_SYS_POST_FLASH_END
-CONFIG_SYS_POST_FLASH_NUM
-CONFIG_SYS_POST_FLASH_START
-CONFIG_SYS_POST_FPU
-CONFIG_SYS_POST_HOTKEYS_GPIO
-CONFIG_SYS_POST_I2C
-CONFIG_SYS_POST_I2C_ADDRS
-CONFIG_SYS_POST_I2C_IGNORES
CONFIG_SYS_POST_MEMORY
CONFIG_SYS_POST_MEM_REGIONS
-CONFIG_SYS_POST_OCM
-CONFIG_SYS_POST_RTC
-CONFIG_SYS_POST_SPR
-CONFIG_SYS_POST_SYSMON
-CONFIG_SYS_POST_UART
-CONFIG_SYS_POST_USB
-CONFIG_SYS_POST_WATCHDOG
-CONFIG_SYS_POST_WORD_ADDR
-CONFIG_SYS_PPC_DDR_WIMGE
-CONFIG_SYS_PQSPAR
-CONFIG_SYS_PSDPAR
CONFIG_SYS_PSSR_VAL
-CONFIG_SYS_PTCPAR
-CONFIG_SYS_PTDPAR
CONFIG_SYS_PTV
CONFIG_SYS_PUAPAR
CONFIG_SYS_QMAN_CENA_BASE
CONFIG_SYS_RCAR_I2C1_BASE
CONFIG_SYS_RCAR_I2C2_BASE
CONFIG_SYS_RCAR_I2C3_BASE
-CONFIG_SYS_READ_SPD
CONFIG_SYS_RESET_ADDR
CONFIG_SYS_RESET_ADDRESS
-CONFIG_SYS_RESET_SCTRL
CONFIG_SYS_RFD
CONFIG_SYS_RGMII1_PHY_ADDR
CONFIG_SYS_RGMII2_PHY_ADDR
CONFIG_SYS_RSTC_RMR_VAL
CONFIG_SYS_RTC_BUS_NUM
CONFIG_SYS_RTC_CNT
-CONFIG_SYS_RTC_OSCILLATOR
-CONFIG_SYS_RTC_REG_BASE_ADDR
CONFIG_SYS_RTC_SETUP
CONFIG_SYS_RX_ETH_BUFFER
CONFIG_SYS_SATA
CONFIG_SYS_SATA2
CONFIG_SYS_SATA2_FLAGS
CONFIG_SYS_SATA2_OFFSET
-CONFIG_SYS_SATA_ENV_DEV
CONFIG_SYS_SATA_FAT_BOOT_PARTITION
CONFIG_SYS_SATA_MAX_DEVICE
CONFIG_SYS_SBFHDR_DATA_OFFSET
CONFIG_SYS_SBFHDR_SIZE
-CONFIG_SYS_SCCR_ENCCM
-CONFIG_SYS_SCCR_PCICM
-CONFIG_SYS_SCCR_PCIEXP1CM
-CONFIG_SYS_SCCR_PCIEXP2CM
CONFIG_SYS_SCCR_SATACM
CONFIG_SYS_SCCR_TSEC1CM
-CONFIG_SYS_SCCR_TSEC1ON
CONFIG_SYS_SCCR_TSEC2CM
-CONFIG_SYS_SCCR_TSEC2ON
-CONFIG_SYS_SCCR_TSECCM
CONFIG_SYS_SCCR_USBDRCM
-CONFIG_SYS_SCCR_USBMPHCM
CONFIG_SYS_SCR
CONFIG_SYS_SCSI_MAX_DEVICE
CONFIG_SYS_SCSI_MAX_LUN
CONFIG_SYS_SCSI_MAX_SCSI_ID
-CONFIG_SYS_SDIO0
-CONFIG_SYS_SDIO0_MAX_CLK
-CONFIG_SYS_SDIO1
-CONFIG_SYS_SDIO1_MAX_CLK
-CONFIG_SYS_SDIO2
-CONFIG_SYS_SDIO2_MAX_CLK
-CONFIG_SYS_SDIO3
-CONFIG_SYS_SDIO3_MAX_CLK
-CONFIG_SYS_SDIO_BASE0
-CONFIG_SYS_SDIO_BASE1
-CONFIG_SYS_SDIO_BASE2
-CONFIG_SYS_SDIO_BASE3
CONFIG_SYS_SDRAM
-CONFIG_SYS_SDRAM1
CONFIG_SYS_SDRAM_BASE
CONFIG_SYS_SDRAM_BASE0
CONFIG_SYS_SDRAM_BASE1
-CONFIG_SYS_SDRAM_BASE1xx
CONFIG_SYS_SDRAM_BASE2
CONFIG_SYS_SDRAM_CFG
CONFIG_SYS_SDRAM_CFG1
CONFIG_SYS_SDRAM_MODE
CONFIG_SYS_SDRAM_SIZE
CONFIG_SYS_SDRAM_SIZE0
-CONFIG_SYS_SDRAM_SIZE1
CONFIG_SYS_SDRAM_SIZE_LAW
CONFIG_SYS_SDRAM_VAL
CONFIG_SYS_SDRAM_VAL1
CONFIG_SYS_SH_SDHI_NR_CHANNEL
CONFIG_SYS_SICRH
CONFIG_SYS_SICRL
-CONFIG_SYS_SIL1178_I2C
CONFIG_SYS_SMC0_CYCLE0_VAL
CONFIG_SYS_SMC0_MODE0_VAL
CONFIG_SYS_SMC0_PULSE0_VAL
CONFIG_SYS_SMC0_SETUP0_VAL
-CONFIG_SYS_SMC_CSR0_VAL
-CONFIG_SYS_SPCR_OPT
CONFIG_SYS_SPD_BUS_NUM
CONFIG_SYS_SPI_ARGS_OFFS
CONFIG_SYS_SPI_ARGS_SIZE
CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE
CONFIG_SYS_SPI_FLASH_U_BOOT_START
CONFIG_SYS_SPI_KERNEL_OFFS
-CONFIG_SYS_SPI_MXC_WAIT
-CONFIG_SYS_SPI_RTC_DEVID
CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
CONFIG_SYS_SPI_U_BOOT_SIZE
CONFIG_SYS_SPL_ARGS_ADDR
CONFIG_SYS_SST_SECT
CONFIG_SYS_SST_SECTSZ
CONFIG_SYS_STACK_SIZE
-CONFIG_SYS_STATUS_C
-CONFIG_SYS_STATUS_OK
CONFIG_SYS_SXCNFG_VAL
CONFIG_SYS_TBIPA_VALUE
CONFIG_SYS_TCLK
CONFIG_SYS_TIMER_BASE
CONFIG_SYS_TIMER_COUNTER
CONFIG_SYS_TIMER_COUNTS_DOWN
-CONFIG_SYS_TIMER_PRESCALER
CONFIG_SYS_TIMER_RATE
CONFIG_SYS_TMPVIRT
-CONFIG_SYS_TMRINTR_MASK
-CONFIG_SYS_TMRINTR_NO
-CONFIG_SYS_TMRINTR_PEND
-CONFIG_SYS_TMRINTR_PRI
-CONFIG_SYS_TMRPND_REG
-CONFIG_SYS_TMR_BASE
CONFIG_SYS_TSEC1_OFFSET
CONFIG_SYS_TSEC2_OFFSET
CONFIG_SYS_TSEC3_OFFSET
CONFIG_SYS_TX_ETH_BUFFER
-CONFIG_SYS_UART1_ALT1_GPIO
-CONFIG_SYS_UART2_ALT1_GPIO
CONFIG_SYS_UART2_ALT3_GPIO
-CONFIG_SYS_UART2_PRI_GPIO
-CONFIG_SYS_UART_BASE
CONFIG_SYS_UART_PORT
CONFIG_SYS_UBOOT_BASE
CONFIG_SYS_UBOOT_START
-CONFIG_SYS_UDELAY_BASE
CONFIG_SYS_UEC
-CONFIG_SYS_UEC1_PHY_ADDR
CONFIG_SYS_UEC2_ETH_TYPE
CONFIG_SYS_UEC2_INTERFACE_SPEED
CONFIG_SYS_UEC2_INTERFACE_TYPE
CONFIG_SYS_UEC2_RX_CLK
CONFIG_SYS_UEC2_TX_CLK
CONFIG_SYS_UEC2_UCC_NUM
-CONFIG_SYS_UEC3_PHY_ADDR
-CONFIG_SYS_UEC4_PHY_ADDR
-CONFIG_SYS_UECx_PHY_ADDR
CONFIG_SYS_ULB_CLK
CONFIG_SYS_UNIFY_CACHE
-CONFIG_SYS_UNSPEC_PHYID
-CONFIG_SYS_UNSPEC_STRID
CONFIG_SYS_USB_FAT_BOOT_PARTITION
CONFIG_SYS_USB_OHCI_BOARD_INIT
CONFIG_SYS_USB_OHCI_CPU_INIT
CONFIG_SYS_USE_DATAFLASH_CS1
CONFIG_SYS_USE_DATAFLASH_CS3
CONFIG_SYS_USE_FLASH
-CONFIG_SYS_USE_MAIN_OSCILLATOR
CONFIG_SYS_USE_MMC
CONFIG_SYS_USE_NAND
CONFIG_SYS_USE_NANDFLASH
CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR
CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN
CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT
-CONFIG_SYS_VCXK_AUTODETECT
CONFIG_SYS_VCXK_BASE
CONFIG_SYS_VCXK_DEFAULT_LINEALIGN
CONFIG_SYS_VCXK_DOUBLEBUFFERED
CONFIG_SYS_VCXK_REQUEST_DDR
CONFIG_SYS_VCXK_REQUEST_PIN
CONFIG_SYS_VCXK_REQUEST_PORT
-CONFIG_SYS_VCXK_RESET_DDR
-CONFIG_SYS_VCXK_RESET_PIN
-CONFIG_SYS_VCXK_RESET_PORT
CONFIG_SYS_VIDEO_LOGO_MAX_SIZE
CONFIG_SYS_VSC7385_BASE
CONFIG_SYS_VSC7385_BASE_PHYS
CONFIG_SYS_VSC7385_BR_PRELIM
CONFIG_SYS_VSC7385_OR_PRELIM
-CONFIG_SYS_WATCHDOG_FREQ
CONFIG_SYS_WATCHDOG_VALUE
CONFIG_SYS_WDTC_WDMR_VAL
CONFIG_SYS_WRITE_SWAPPED_DATA
CONFIG_SYS_XHCI_USB1_ADDR
CONFIG_SYS_XHCI_USB2_ADDR
CONFIG_SYS_XHCI_USB3_ADDR
-CONFIG_SYS_XIMG_LEN
-CONFIG_TAM3517_SETTINGS
CONFIG_TCA642X
CONFIG_TEGRA_BOARD_STRING
CONFIG_TEGRA_CLOCK_SCALING
CONFIG_TEGRA_ENABLE_UARTA
-CONFIG_TEGRA_ENABLE_UARTB
-CONFIG_TEGRA_ENABLE_UARTC
CONFIG_TEGRA_ENABLE_UARTD
-CONFIG_TEGRA_ENABLE_UARTE
CONFIG_TEGRA_GPU
CONFIG_TEGRA_LP0
-CONFIG_TEGRA_NAND
CONFIG_TEGRA_PMU
CONFIG_TEGRA_SLINK_CTRLS
CONFIG_TEGRA_SPI
CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
CONFIG_TESTPIN_MASK
CONFIG_TESTPIN_REG
-CONFIG_TEST_LIST_SORT
-CONFIG_TFTP_FILE_NAME_MAX_LEN
CONFIG_TFTP_PORT
CONFIG_THOR_RESET_OFF
CONFIG_THUNDERX
CONFIG_TSECV2_1
CONFIG_TSEC_TBICR_SETTINGS
CONFIG_TWL6030_POWER
-CONFIG_TX_DESCR_NUM
CONFIG_TZSW_RESERVED_DRAM_SIZE
CONFIG_UBIFS_VOLUME
CONFIG_UBI_PART
CONFIG_UBOOT_SECTOR_START
CONFIG_UDP_CHECKSUM
CONFIG_UEC_ETH
-CONFIG_UEC_ETH1
CONFIG_UEC_ETH2
-CONFIG_UEC_ETH3
-CONFIG_UEC_ETH4
-CONFIG_UEC_ETH5
-CONFIG_UEC_ETH6
-CONFIG_UEC_ETH7
-CONFIG_UEC_ETH8
-CONFIG_UID16
-CONFIG_ULPI_REF_CLK
CONFIG_UPDATEB
-CONFIG_UPDATE_LOAD_ADDR
CONFIG_USART_BASE
CONFIG_USART_ID
-CONFIG_USBD_CONFIGURATION_STR
-CONFIG_USBD_CTRL_INTERFACE_STR
-CONFIG_USBD_DATA_INTERFACE_STR
CONFIG_USBD_HS
CONFIG_USBD_MANUFACTURER
CONFIG_USBD_PRODUCTID_CDCACM
CONFIG_USBD_PRODUCTID_GSERIAL
CONFIG_USBD_PRODUCT_NAME
-CONFIG_USBD_SERIAL_BULK_HS_PKTSIZE
-CONFIG_USBD_SERIAL_BULK_PKTSIZE
-CONFIG_USBD_SERIAL_INT_ENDPOINT
-CONFIG_USBD_SERIAL_INT_PKTSIZE
-CONFIG_USBD_SERIAL_IN_ENDPOINT
-CONFIG_USBD_SERIAL_IN_PKTSIZE
-CONFIG_USBD_SERIAL_OUT_ENDPOINT
-CONFIG_USBD_SERIAL_OUT_PKTSIZE
CONFIG_USBD_VENDORID
CONFIG_USBNET_DEV_ADDR
CONFIG_USB_ATMEL
CONFIG_USB_ATMEL_CLK_SEL_PLLB
CONFIG_USB_ATMEL_CLK_SEL_UPLL
-CONFIG_USB_BIN_FIXUP
CONFIG_USB_BOOTING
CONFIG_USB_DEVICE
CONFIG_USB_DEV_BASE
-CONFIG_USB_DEV_PULLUP_GPIO
-CONFIG_USB_EHCI_BASE
-CONFIG_USB_EHCI_BASE_LIST
CONFIG_USB_EHCI_EXYNOS
-CONFIG_USB_EHCI_FARADAY
CONFIG_USB_EHCI_TXFIFO_THRESH
-CONFIG_USB_ETH_QMULT
-CONFIG_USB_ETH_SUBSET
CONFIG_USB_EXT2_BOOT
CONFIG_USB_FAT_BOOT
-CONFIG_USB_GADGET_AMD5536UDC
CONFIG_USB_GADGET_AT91
-CONFIG_USB_GADGET_DUMMY_HCD
CONFIG_USB_GADGET_DWC2_OTG_PHY
-CONFIG_USB_GADGET_FOTG210
-CONFIG_USB_GADGET_FSL_USB2
-CONFIG_USB_GADGET_GOKU
-CONFIG_USB_GADGET_IMX
-CONFIG_USB_GADGET_M66592
-CONFIG_USB_GADGET_MQ11XX
-CONFIG_USB_GADGET_MUSBHSFC
-CONFIG_USB_GADGET_N9604
-CONFIG_USB_GADGET_NET2280
-CONFIG_USB_GADGET_OMAP
-CONFIG_USB_GADGET_PXA27X
-CONFIG_USB_GADGET_PXA2XX
-CONFIG_USB_GADGET_SA1100
-CONFIG_USB_INVENTRA_DMA
CONFIG_USB_ISP1301_I2C_ADDR
CONFIG_USB_MAX_CONTROLLER_COUNT
-CONFIG_USB_MUSB_TIMEOUT
-CONFIG_USB_MUSB_TUSB6010
CONFIG_USB_OHCI_LPC32XX
CONFIG_USB_OHCI_NEW
-CONFIG_USB_OTG
-CONFIG_USB_OTG_BLACKLIST_HUB
-CONFIG_USB_PXA25X_SMALL
-CONFIG_USB_TI_CPPI_DMA
CONFIG_USB_TTY
-CONFIG_USB_TUSB_OMAP_DMA
-CONFIG_USB_ULPI_TIMEOUT
CONFIG_USB_XHCI_EXYNOS
CONFIG_USE_INTERRUPT
CONFIG_USE_ONENAND_BOARD_INIT
-CONFIG_UTBIPAR_INIT_TBIPA
-CONFIG_U_BOOT_HDR_ADDR
CONFIG_U_BOOT_HDR_SIZE
CONFIG_VAR_SIZE_SPL
CONFIG_VERY_BIG_RAM
CONFIG_VIDEO_BCM2835
CONFIG_VIDEO_BMP_LOGO
CONFIG_VIDEO_DA8XX
-CONFIG_VIDEO_FONT_4X6
CONFIG_VIDEO_LOGO
-CONFIG_VIDEO_MXS_MODE_SYSTEM
-CONFIG_VIDEO_STD_TIMINGS
-CONFIG_VID_FLS_ENV
-CONFIG_VM86
-CONFIG_VOIPAC_LCD
-CONFIG_VOL_MONITOR_INA220
-CONFIG_VOL_MONITOR_IR36021_READ
-CONFIG_VOL_MONITOR_IR36021_SET
CONFIG_VSC7385_ENET
CONFIG_VSC7385_IMAGE
CONFIG_VSC7385_IMAGE_SIZE
CONFIG_VSC9953
-CONFIG_WATCHDOG_NOWAYOUT
CONFIG_WATCHDOG_PRESC
CONFIG_WATCHDOG_RC
CONFIG_WATCHDOG_TIMEOUT
-CONFIG_WD_PERIOD
-CONFIG_X86EMU_DEBUG
CONFIG_X86EMU_RAW_IO
CONFIG_X86_MRC_ADDR
CONFIG_X86_REFCODE_ADDR
CONFIG_X86_REFCODE_RUN_ADDR
-CONFIG_XGI_XG22_BASE
-CONFIG_XSENGINE
CONFIG_XTFPGA
-CONFIG_YAFFS_AUTO_UNICODE
-CONFIG_YAFFS_CASE_INSENSITIVE
-CONFIG_YAFFS_DEFINES_TYPES
-CONFIG_YAFFS_UNICODE
-CONFIG_YAFFS_UTIL
-CONFIG_YAFFS_WINCE
-CONFIG_YELLOW_LED
-CONFIG_ZLT
-CONFIG_eTSEC_MDIO_BUS
projects / thirdparty / u-boot.git / commitdiff
