+++ /dev/null
-From 3b6fbfd6785ef4b4bb8dea412242e4ce94327f9a Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Mon, 1 Feb 2021 12:12:34 +0100
-Subject: drm/amdgpu: enable only one high prio compute queue
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-From: Nirmoy Das <nirmoy.das@amd.com>
-
-[ Upstream commit 8c0225d79273968a65e73a4204fba023ae02714d ]
-
-For high priority compute to work properly we need to enable
-wave limiting on gfx pipe. Wave limiting is done through writing
-into mmSPI_WCL_PIPE_PERCENT_GFX register. Enable only one high
-priority compute queue to avoid race condition between multiple
-high priority compute queues writing that register simultaneously.
-
-Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
-Acked-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 15 ++++++++-------
- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 +-
- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 ++----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 ++----
- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 ++-----
- 5 files changed, 15 insertions(+), 21 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
-index c485ec86804e..034a0f3b4c66 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
-@@ -193,15 +193,16 @@ static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
- }
-
- bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
-- int pipe, int queue)
-+ struct amdgpu_ring *ring)
- {
-- bool multipipe_policy = amdgpu_gfx_is_multipipe_capable(adev);
-- int cond;
-- /* Policy: alternate between normal and high priority */
-- cond = multipipe_policy ? pipe : queue;
--
-- return ((cond % 2) != 0);
-+ /* Policy: use 1st queue as high priority compute queue if we
-+ * have more than one compute queue.
-+ */
-+ if (adev->gfx.num_compute_rings > 1 &&
-+ ring == &adev->gfx.compute_ring[0])
-+ return true;
-
-+ return false;
- }
-
- void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
-index f353a5b71804..6e0cba6f4bdc 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
-@@ -373,7 +373,7 @@ void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
- bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
- int pipe, int queue);
- bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
-- int pipe, int queue);
-+ struct amdgpu_ring *ring);
- int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
- int pipe, int queue);
- void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
-index 4ebb43e09099..4cc83b399b66 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
-@@ -4334,8 +4334,7 @@ static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
- irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
- + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
- + ring->pipe;
-- hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
-- ring->queue) ?
-+ hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
- AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
- /* type-2 packets are deprecated on MEC, use type-3 instead */
- r = amdgpu_ring_init(adev, ring, 1024,
-@@ -6361,8 +6360,7 @@ static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct
- struct amdgpu_device *adev = ring->adev;
-
- if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
-- if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
-- ring->queue)) {
-+ if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
- mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
- mqd->cp_hqd_queue_priority =
- AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index c36258d56b44..f2f603fa0288 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -1915,8 +1915,7 @@ static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
- + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
- + ring->pipe;
-
-- hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
-- ring->queue) ?
-+ hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
- AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_RING_PRIO_DEFAULT;
- /* type-2 packets are deprecated on MEC, use type-3 instead */
- r = amdgpu_ring_init(adev, ring, 1024,
-@@ -4434,8 +4433,7 @@ static void gfx_v8_0_mqd_set_priority(struct amdgpu_ring *ring, struct vi_mqd *m
- struct amdgpu_device *adev = ring->adev;
-
- if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
-- if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
-- ring->queue)) {
-+ if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
- mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
- mqd->cp_hqd_queue_priority =
- AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
-index 957c12b72767..fa843bda70ba 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
-@@ -2228,8 +2228,7 @@ static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
- irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
- + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
- + ring->pipe;
-- hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
-- ring->queue) ?
-+ hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
- AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
- /* type-2 packets are deprecated on MEC, use type-3 instead */
- return amdgpu_ring_init(adev, ring, 1024,
-@@ -3384,9 +3383,7 @@ static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *m
- struct amdgpu_device *adev = ring->adev;
-
- if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
-- if (amdgpu_gfx_is_high_priority_compute_queue(adev,
-- ring->pipe,
-- ring->queue)) {
-+ if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
- mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
- mqd->cp_hqd_queue_priority =
- AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
---
-2.30.1
-
nvme-tcp-add-clean-action-for-failed-reconnection.patch
asoc-intel-add-dmi-quirk-table-to-soc_intel_is_byt_c.patch
btrfs-fix-error-handling-in-commit_fs_roots.patch
-drm-amdgpu-enable-only-one-high-prio-compute-queue.patch
perf-x86-kvm-add-cascade-lake-xeon-steppings-to-isol.patch
asoc-intel-sof-sdw-indent-and-add-quirks-consistentl.patch
asoc-intel-sof_sdw-detect-dmic-number-based-on-mach-.patch
+++ /dev/null
-From c600a1fe05eceaa1c6f8a766b483b85257d9398b Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Mon, 1 Feb 2021 12:12:34 +0100
-Subject: drm/amdgpu: enable only one high prio compute queue
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-From: Nirmoy Das <nirmoy.das@amd.com>
-
-[ Upstream commit 8c0225d79273968a65e73a4204fba023ae02714d ]
-
-For high priority compute to work properly we need to enable
-wave limiting on gfx pipe. Wave limiting is done through writing
-into mmSPI_WCL_PIPE_PERCENT_GFX register. Enable only one high
-priority compute queue to avoid race condition between multiple
-high priority compute queues writing that register simultaneously.
-
-Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
-Acked-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 15 ++++++++-------
- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 +-
- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 ++----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 ++----
- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 ++-----
- 5 files changed, 15 insertions(+), 21 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
-index cd2c676a2797..8e0a6c62322e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
-@@ -193,15 +193,16 @@ static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
- }
-
- bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
-- int pipe, int queue)
-+ struct amdgpu_ring *ring)
- {
-- bool multipipe_policy = amdgpu_gfx_is_multipipe_capable(adev);
-- int cond;
-- /* Policy: alternate between normal and high priority */
-- cond = multipipe_policy ? pipe : queue;
--
-- return ((cond % 2) != 0);
-+ /* Policy: use 1st queue as high priority compute queue if we
-+ * have more than one compute queue.
-+ */
-+ if (adev->gfx.num_compute_rings > 1 &&
-+ ring == &adev->gfx.compute_ring[0])
-+ return true;
-
-+ return false;
- }
-
- void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
-index 6b5a8f4642cc..72dbcd2bc6a6 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
-@@ -380,7 +380,7 @@ void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
- bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
- int pipe, int queue);
- bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
-- int pipe, int queue);
-+ struct amdgpu_ring *ring);
- int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
- int pipe, int queue);
- void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
-index e7d6da05011f..3a291befcddc 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
-@@ -4495,8 +4495,7 @@ static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
- irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
- + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
- + ring->pipe;
-- hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
-- ring->queue) ?
-+ hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
- AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
- /* type-2 packets are deprecated on MEC, use type-3 instead */
- r = amdgpu_ring_init(adev, ring, 1024,
-@@ -6545,8 +6544,7 @@ static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct
- struct amdgpu_device *adev = ring->adev;
-
- if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
-- if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
-- ring->queue)) {
-+ if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
- mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
- mqd->cp_hqd_queue_priority =
- AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 37639214cbbb..b0284c4659ba 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -1923,8 +1923,7 @@ static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
- + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
- + ring->pipe;
-
-- hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
-- ring->queue) ?
-+ hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
- AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_RING_PRIO_DEFAULT;
- /* type-2 packets are deprecated on MEC, use type-3 instead */
- r = amdgpu_ring_init(adev, ring, 1024,
-@@ -4442,8 +4441,7 @@ static void gfx_v8_0_mqd_set_priority(struct amdgpu_ring *ring, struct vi_mqd *m
- struct amdgpu_device *adev = ring->adev;
-
- if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
-- if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
-- ring->queue)) {
-+ if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
- mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
- mqd->cp_hqd_queue_priority =
- AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
-index 5f4805e4d04a..3e800193a604 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
-@@ -2228,8 +2228,7 @@ static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
- irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
- + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
- + ring->pipe;
-- hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
-- ring->queue) ?
-+ hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
- AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
- /* type-2 packets are deprecated on MEC, use type-3 instead */
- return amdgpu_ring_init(adev, ring, 1024,
-@@ -3391,9 +3390,7 @@ static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *m
- struct amdgpu_device *adev = ring->adev;
-
- if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
-- if (amdgpu_gfx_is_high_priority_compute_queue(adev,
-- ring->pipe,
-- ring->queue)) {
-+ if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
- mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
- mqd->cp_hqd_queue_priority =
- AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
---
-2.30.1
-
alsa-usb-audio-add-djm-450-to-the-quirks-table.patch
asoc-intel-add-dmi-quirk-table-to-soc_intel_is_byt_c.patch
btrfs-fix-error-handling-in-commit_fs_roots.patch
-drm-amdgpu-enable-only-one-high-prio-compute-queue.patch
perf-x86-kvm-add-cascade-lake-xeon-steppings-to-isol.patch
asoc-intel-sof-sdw-indent-and-add-quirks-consistentl.patch
asoc-intel-sof_sdw-detect-dmic-number-based-on-mach-.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
