Merge branch 'clk-determine-rate' into clk-next

* clk-determine-rate: (120 commits)
  clk: microchip: core: remove duplicate roclk_determine_rate()
  clk: nxp: Fix pll0 rate check condition in LPC18xx CGU driver
  clk: scmi: migrate round_rate() to determine_rate()
  clk: ti: fapll: convert from round_rate() to determine_rate()
  clk: ti: dra7-atl: convert from round_rate() to determine_rate()
  clk: ti: divider: convert from round_rate() to determine_rate()
  clk: ti: composite: convert from round_rate() to determine_rate()
  clk: ti: dpll: convert from round_rate() to determine_rate()
  clk: ti: dpll: change error return from ~0 to -EINVAL
  clk: ti: dpll: remove round_rate() in favor of determine_rate()
  clk: tegra: tegra210-emc: convert from round_rate() to determine_rate()
  clk: tegra: super: convert from round_rate() to determine_rate()
  clk: tegra: pll: convert from round_rate() to determine_rate()
  clk: tegra: periph: divider: convert from round_rate() to determine_rate()
  clk: tegra: divider: convert from round_rate() to determine_rate()
  clk: tegra: audio-sync: convert from round_rate() to determine_rate()
  clk: fixed-factor: drop round_rate() clk ops
  clk: divider: remove round_rate() in favor of determine_rate()
  clk: visconti: pll: convert from round_rate() to determine_rate()
  clk: versatile: vexpress-osc: convert from round_rate() to determine_rate()
  ...

diff --cc drivers/clk/at91/clk-sam9x60-pll.c
Simple merge

diff --cc drivers/clk/clk-ep93xx.c
Simple merge

diff --cc drivers/clk/clk-scmi.c
Simple merge

diff --cc drivers/clk/mediatek/clk-pll.c
index d717a120793b200e165c261514960095fae7af4c,139d3bfcf45f9ab094aa429e7b2913abaa3e29ea..cd2b6ce551c6b0333cbe0a4f0d155ba2411f757a
--- 1/drivers/clk/mediatek/clk-pll.c
--- 2/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@@ -309,16 -286,6 +312,16 @@@ const struct clk_ops mtk_pll_ops = 
        .set_rate       = mtk_pll_set_rate,
  };
  
-       .round_rate     = mtk_pll_round_rate,
 +const struct clk_ops mtk_pll_fenc_clr_set_ops = {
 +      .is_prepared    = mtk_pll_fenc_is_prepared,
 +      .prepare        = mtk_pll_prepare_setclr,
 +      .unprepare      = mtk_pll_unprepare_setclr,
 +      .recalc_rate    = mtk_pll_recalc_rate,
++      .determine_rate = mtk_pll_determine_rate,
 +      .set_rate       = mtk_pll_set_rate,
 +};
 +EXPORT_SYMBOL_GPL(mtk_pll_fenc_clr_set_ops);
 +
  struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
                                        const struct mtk_pll_data *data,
                                        void __iomem *base,

diff --cc drivers/clk/mediatek/clk-pll.h
Simple merge

diff --cc drivers/clk/nxp/clk-lpc32xx.c
Simple merge

diff --cc drivers/clk/xilinx/clk-xlnx-clock-wizard.c
Simple merge