arm64: dts: qcom: ipq5424: Add USB controller and phy nodes

The IPQ5424 SoC has both USB2.0 and USB3.0 controllers. The USB3.0
can connect to either of USB2.0 or USB3.0 phy and operate in the
respective mode.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241118052839.382431-7-quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
index 2b509bb2266ce7a8b5bba4fbbb001073d31625b6..b6e4bb3328b380e7aa20e99bf0d8ae03b3a7f808 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
@@ -16,6 +16,57 @@
        aliases {
                serial0 = &uart1;
        };
+
+       vreg_misc_3p3: regulator-usb-3p3 {
+               compatible = "regulator-fixed";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
+               regulator-always-on;
+               regulator-name = "usb_hs_vdda_3p3";
+       };
+
+       vreg_misc_1p8: regulator-usb-1p8 {
+               compatible = "regulator-fixed";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               regulator-boot-on;
+               regulator-always-on;
+               regulator-name = "vdda_1p8_usb";
+       };
+
+       vreg_misc_0p925: regulator-usb-0p925 {
+               compatible = "regulator-fixed";
+               regulator-min-microvolt = <925000>;
+               regulator-max-microvolt = <925000>;
+               regulator-boot-on;
+               regulator-always-on;
+               regulator-name = "vdd_core_usb";
+       };
+};
+
+&dwc_0 {
+       dr_mode = "host";
+};
+
+&dwc_1 {
+       dr_mode = "host";
+};
+
+&qusb_phy_0 {
+       vdd-supply = <&vreg_misc_0p925>;
+       vdda-pll-supply = <&vreg_misc_1p8>;
+       vdda-phy-dpdm-supply = <&vreg_misc_3p3>;
+
+       status = "okay";
+};
+
+&qusb_phy_1 {
+       vdd-supply = <&vreg_misc_0p925>;
+       vdda-pll-supply = <&vreg_misc_1p8>;
+       vdda-phy-dpdm-supply = <&vreg_misc_3p3>;
+
+       status = "okay";
 };
 
 &sleep_clk {
@@ -36,6 +87,13 @@
        };
 };
 
+&ssphy_0 {
+       vdda-pll-supply = <&vreg_misc_1p8>;
+       vdda-phy-supply = <&vreg_misc_0p925>;
+
+       status = "okay";
+};
+
 &tlmm {
        spi0_default_state: spi0-default-state {
                clk-pins {
@@ -97,6 +155,14 @@
        status = "okay";
 };
 
+&usb2 {
+       status = "okay";
+};
+
+&usb3 {
+       status = "okay";
+};
+
 &xo_board {
        clock-frequency = <24000000>;
 };

diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
index 3277e25d57f5562c533c80a26bbae7d34fc9579c..3ab2ffa10f635c02b37c65b25b28a2cae417e142 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
@@ -276,6 +276,165 @@
                        clocks = <&sleep_clk>;
                };
 
+               qusb_phy_1: phy@71000 {
+                       compatible = "qcom,ipq5424-qusb2-phy";
+                       reg = <0 0x00071000 0 0x180>;
+                       #phy-cells = <0>;
+
+                       clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
+                               <&xo_board>;
+                       clock-names = "cfg_ahb", "ref";
+
+                       resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
+                       status = "disabled";
+               };
+
+               usb2: usb2@1e00000 {
+                       compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
+                       reg = <0 0x01ef8800 0 0x400>;
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+
+                       clocks = <&gcc GCC_USB1_MASTER_CLK>,
+                                <&gcc GCC_USB1_SLEEP_CLK>,
+                                <&gcc GCC_USB1_MOCK_UTMI_CLK>,
+                                <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
+                                <&gcc GCC_CNOC_USB_CLK>;
+
+                       clock-names = "core",
+                                     "sleep",
+                                     "mock_utmi",
+                                     "iface",
+                                     "cfg_noc";
+
+                       assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
+                                         <&gcc GCC_USB1_MOCK_UTMI_CLK>;
+                       assigned-clock-rates = <200000000>,
+                                              <24000000>;
+
+                       interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "pwr_event",
+                                         "qusb2_phy",
+                                         "dm_hs_phy_irq",
+                                         "dp_hs_phy_irq";
+
+                       resets = <&gcc GCC_USB1_BCR>;
+                       qcom,select-utmi-as-pipe-clk;
+                       status = "disabled";
+
+                       dwc_1: usb@1e00000 {
+                               compatible = "snps,dwc3";
+                               reg = <0 0x01e00000 0 0xe000>;
+                               clocks = <&gcc GCC_USB1_MOCK_UTMI_CLK>;
+                               clock-names = "ref";
+                               interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
+                               phys = <&qusb_phy_1>;
+                               phy-names = "usb2-phy";
+                               tx-fifo-resize;
+                               snps,is-utmi-l1-suspend;
+                               snps,hird-threshold = /bits/ 8 <0x0>;
+                               snps,dis_u2_susphy_quirk;
+                               snps,dis_u3_susphy_quirk;
+                       };
+               };
+
+               qusb_phy_0: phy@7b000 {
+                       compatible = "qcom,ipq5424-qusb2-phy";
+                       reg = <0 0x0007b000 0 0x180>;
+                       #phy-cells = <0>;
+
+                       clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+                               <&xo_board>;
+                       clock-names = "cfg_ahb", "ref";
+
+                       resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+                       status = "disabled";
+               };
+
+               ssphy_0: phy@7d000 {
+                       compatible = "qcom,ipq5424-qmp-usb3-phy";
+                       reg = <0 0x0007d000 0 0xa00>;
+                       #phy-cells = <0>;
+
+                       clocks = <&gcc GCC_USB0_AUX_CLK>,
+                                <&xo_board>,
+                                <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+                                <&gcc GCC_USB0_PIPE_CLK>;
+                       clock-names = "aux",
+                                     "ref",
+                                     "cfg_ahb",
+                                     "pipe";
+
+                       resets = <&gcc GCC_USB0_PHY_BCR>,
+                                <&gcc GCC_USB3PHY_0_PHY_BCR>;
+                       reset-names = "phy",
+                                     "phy_phy";
+
+                       #clock-cells = <0>;
+                       clock-output-names = "usb0_pipe_clk";
+
+                       status = "disabled";
+               };
+
+               usb3: usb3@8a00000 {
+                       compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
+                       reg = <0 0x08af8800 0 0x400>;
+
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+
+                       clocks = <&gcc GCC_USB0_MASTER_CLK>,
+                                <&gcc GCC_USB0_SLEEP_CLK>,
+                                <&gcc GCC_USB0_MOCK_UTMI_CLK>,
+                                <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+                                <&gcc GCC_CNOC_USB_CLK>;
+
+                       clock-names = "core",
+                                     "sleep",
+                                     "mock_utmi",
+                                     "iface",
+                                     "cfg_noc";
+
+                       assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
+                                         <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+                       assigned-clock-rates = <200000000>,
+                                              <24000000>;
+
+                       interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&intc GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&intc GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "pwr_event",
+                                         "qusb2_phy",
+                                         "dm_hs_phy_irq",
+                                         "dp_hs_phy_irq";
+
+                       resets = <&gcc GCC_USB_BCR>;
+                       status = "disabled";
+
+                       dwc_0: usb@8a00000 {
+                               compatible = "snps,dwc3";
+                               reg = <0 0x08a00000 0 0xcd00>;
+                               clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+                               clock-names = "ref";
+                               interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
+                               phys = <&qusb_phy_0>, <&ssphy_0>;
+                               phy-names = "usb2-phy", "usb3-phy";
+                               tx-fifo-resize;
+                               snps,is-utmi-l1-suspend;
+                               snps,hird-threshold = /bits/ 8 <0x0>;
+                               snps,dis_u2_susphy_quirk;
+                               snps,dis_u3_susphy_quirk;
+                               snps,dis-u1-entry-quirk;
+                               snps,dis-u2-entry-quirk;
+                       };
+               };
+
                timer@f420000 {
                        compatible = "arm,armv7-timer-mem";
                        reg = <0 0xf420000 0 0x1000>;