5.4-stable patches

added patches:
	asoc-fsl_micfil-fix-the-naming-style-for-mask-definition.patch

diff --git a/queue-5.4/asoc-fsl_micfil-fix-the-naming-style-for-mask-definition.patch b/queue-5.4/asoc-fsl_micfil-fix-the-naming-style-for-mask-definition.patch
new file mode 100644 (file)
index 0000000..362ba11
--- /dev/null
+++ b/queue-5.4/asoc-fsl_micfil-fix-the-naming-style-for-mask-definition.patch
@@ -0,0 +1,45 @@
+From 101b096bc2549618f18bc08ae3a0e364b3c8fff1 Mon Sep 17 00:00:00 2001
+From: Shengjiu Wang <shengjiu.wang@nxp.com>
+Date: Thu, 5 May 2022 15:34:07 +0800
+Subject: ASoC: fsl_micfil: fix the naming style for mask definition
+
+From: Shengjiu Wang <shengjiu.wang@nxp.com>
+
+commit 101b096bc2549618f18bc08ae3a0e364b3c8fff1 upstream.
+
+Remove the _SHIFT for the mask definition.
+
+Fixes: 17f2142bae4b ("ASoC: fsl_micfil: use GENMASK to define register bit fields")
+Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
+Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
+Link: https://lore.kernel.org/r/1651736047-28809-1-git-send-email-shengjiu.wang@nxp.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ sound/soc/fsl/fsl_micfil.h |    8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/sound/soc/fsl/fsl_micfil.h
++++ b/sound/soc/fsl/fsl_micfil.h
+@@ -75,9 +75,9 @@
+ #define MICFIL_FIFO_STAT_FIFOX_UNDER(ch)      BIT((ch) + 8)
+ 
+ /* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/
+-#define MICFIL_VAD0_CTRL1_CHSEL_SHIFT GENMASK(26, 24)
+-#define MICFIL_VAD0_CTRL1_CICOSR_SHIFT        GENMASK(19, 16)
+-#define MICFIL_VAD0_CTRL1_INITT_SHIFT GENMASK(12, 8)
++#define MICFIL_VAD0_CTRL1_CHSEL               GENMASK(26, 24)
++#define MICFIL_VAD0_CTRL1_CICOSR      GENMASK(19, 16)
++#define MICFIL_VAD0_CTRL1_INITT               GENMASK(12, 8)
+ #define MICFIL_VAD0_CTRL1_ST10                BIT(4)
+ #define MICFIL_VAD0_CTRL1_ERIE                BIT(3)
+ #define MICFIL_VAD0_CTRL1_IE          BIT(2)
+@@ -107,7 +107,7 @@
+ 
+ /* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */
+ #define MICFIL_VAD0_ZCD_ZCDTH         GENMASK(25, 16)
+-#define MICFIL_VAD0_ZCD_ZCDADJ_SHIFT  GENMASK(11, 8)
++#define MICFIL_VAD0_ZCD_ZCDADJ                GENMASK(11, 8)
+ #define MICFIL_VAD0_ZCD_ZCDAND                BIT(4)
+ #define MICFIL_VAD0_ZCD_ZCDAUT                BIT(2)
+ #define MICFIL_VAD0_ZCD_ZCDEN         BIT(0)

diff --git a/queue-5.4/series b/queue-5.4/series
index 69932eab010fd5e0d96ff8b2986961d94f738a2d..ffb18a1037738209a25ee712ba7a45b7436f60c7 100644 (file)
--- a/queue-5.4/series
+++ b/queue-5.4/series
@@ -200,3 +200,4 @@ sunrpc-correct-error-code-comment-in-xs_tcp_setup_so.patch
 sunrpc-replace-internal-use-of-sockwq_async_nospace.patch
 sunrpc-clear-xprt_sock_upd_timeout-when-reset-transp.patch
 sh-intc-fix-use-after-free-bug-in-register_intc_cont.patch
+asoc-fsl_micfil-fix-the-naming-style-for-mask-definition.patch