]> git.ipfire.org Git - thirdparty/binutils-gdb.git/commitdiff
Create ChangeLog.linaro files for backports, and fix ChangeLog files.
authorAdhemerval Zanella <adhemerval.zanella@linaro.org>
Thu, 20 Oct 2016 14:57:41 +0000 (12:57 -0200)
committerAdhemerval Zanella <adhemerval.zanella@linaro.org>
Thu, 24 Aug 2017 12:46:31 +0000 (09:46 -0300)
14 files changed:
bfd/ChangeLog
bfd/ChangeLog.linaro
gas/ChangeLog
gas/ChangeLog.linaro [new file with mode: 0644]
gas/testsuite/ChangeLog
gas/testsuite/ChangeLog.linaro [new file with mode: 0644]
include/opcode/ChangeLog
include/opcode/ChangeLog.linaro [new file with mode: 0644]
ld/ChangeLog
ld/ChangeLog.linaro [new file with mode: 0644]
ld/testsuite/ChangeLog
ld/testsuite/ChangeLog.linaro [new file with mode: 0644]
opcodes/ChangeLog
opcodes/ChangeLog.linaro [new file with mode: 0644]

index 3b376cb9b273d09ddd7ce0aeca405f23d674b38f..035acd36d78e521a6181f36b848fb4c2422809aa 100644 (file)
@@ -1,158 +1,3 @@
-2015-01-13  Thomas Preud'homme <thomas.preudhomme@arm.com>
-
-       * elfnn-aarch64.c (elfNN_aarch64_final_link_relocate): Use SYMBOLIC_BIND
-       to check if a symbol should be bound symbolically.
-
-2015-07-25  Thomas Preud'homme  <thomas.preudhomme@arm.com>
-
-       * elf32-arm.c (elf32_arm_final_link_relocate): Use SYMBOLIC_BIND to
-       check if a symbol should be bound symbolically.
-       * elf32-hppa.c (elf32_hppa_check_relocs,
-       elf32_hppa_adjust_dynamic_symbol, elf32_hppa_relocate_section,
-       elf32_hppa_finish_dynamic_symbol): Likewise.
-       * elf32-m68k.c (elf_m68k_check_relocs,
-       elf_m68k_relocate_section): Likewise.
-       * elf32-nios2.c (nios2_elf32_relocate_section,
-       nios2_elf32_check_relocs, allocate_dynrelocs): Likewise.
-       * elf32-tic6x.c (elf32_tic6x_finish_dynamic_symbol,
-       elf32_tic6x_relocate_section): Likewise.
-
-2015-04-01  Tejas Belagod  <tejas.belagod@arm.com>
-           Marcus Shawcroft  <marcus.shawcroft@arm.com>
-           Jiong Wang  <jiong.wang@arm.com>
-
-       * bfd-in.h (bfd_elf64_aarch64_set_options)
-       (bfd_elf32_aarch64_set_options): Add parameter.
-       * bfd-in2.h: Regenerated.
-       * elfnn-aarch64.c (aarch64_erratum_843419_stub)
-       (_bfd_aarch64_adrp_p, _bfd_aarch64_erratum_843419_sequence_p)
-       (_bfd_aarch64_erratum_843419_stub_name)
-       (_bfd_aarch64_erratum_843419_fixup)
-       (_bfd_aarch64_erratum_843419_scan)
-       (_bfd_aarch64_erratum_843419_branch_to_stub)
-       (_bfd_aarch64_erratum_843419_p): Define.
-       (enum elf_aarch64_stub_type): Define
-       aarch64_stub_erratum_843419_veneer.
-       (struct elf_aarch64_stub_hash_entry): Define adrp_offset.
-       (struct elf_aarch64_link_hash_table): Define fix_erratum_843419
-       and fix_erratum_843419_adr.
-       (stub_hash_newfunc): Initialize adrp_offset;
-       (_bfd_aarch64_add_stub_entry_after): Define.
-       (aarch64_map_one_stub, aarch64_build_one_stub)
-       (aarch64_size_one_stub): Handle
-       aarch64_stub_erratum_843419_veneer.
-       (_bfd_aarch64_resize_stubs): Round stub section size.
-       (elfNN_aarch64_size_stubs): Add scan for 843419.
-       (bfd_elfNN_aarch64_set_options): Add parameter. Initialize
-       fix_erratum_843419 and fix_erratum_843419_adr.
-       (struct erratum_835769_branch_to_stub_data): Add info.
-       (elfNN_aarch64_write_section): Initialise info.  Handle 843419.
-       (elfNN_aarch64_size_dynamic_sections): Handle 843419.
-       * elfxx-aarch64.c (_bfd_aarch64_decode_adrp_imm)
-       (_bfd_aarch64_sign_extend): Define.
-       (reencode_adr_imm): Remove static. Rename to:
-       (_bfd_aarch64_reencode_adr_imm): Define.
-       (_bfd_aarch64_elf_put_addend): Call _bfd_aarch64_reencode_adr_imm.
-       * elfxx-aarch64.h (AARCH64_ADR_OP, AARCH64_ADRP_OP)
-       (AARCH64_ADRP_OP_MASK, _bfd_aarch64_sign_extend)
-       (_bfd_aarch64_decode_adrp_imm, _bfd_aarch64_reencode_adr_imm):
-       Define.
-
-2015-03-25  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-
-       * elfnn-aarch64.c (_bfd_aarch64_resize_stubs): Adjust stub section
-       size for initial branch.
-       (elfNN_aarch64_build_stubs): Write initial branch.
-       _bfd_aarch64_decode_(elfNN_aarch64_output_arch_local_syms): Write
-       mapping symbol on initial branch.
-
-2015-03-25  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-
-       * elfnn-aarch64.c (_bfd_aarch64_erratum_835769_scan):
-       Update erratum count.
-
-2015-03-24  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-
-       * elfnn-aarch64.c (_bfd_aarch64_create_or_find_stub_sec): Factor
-       code into:
-       (_bfd_aarch64_get_stub_for_link_section): Define.
-
-2015-03-24  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-
-       * elfnn-aarch64.c (_bfd_aarch64_create_or_find_stub_sec): Adjust
-       update of section_group[].stub_sec.
-
-2015-03-24  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-
-       * elfnn-aarch64.c (struct aarch64_erratum_835769_fix) Remove.
-       (erratum_835769_scan) Drop fix_table_size_p and fixes_p arguments.
-       Delete fixes, fix_table_size and associated code.  Call
-       _bfd_aarch64_add_stub_entry_in_group. Rename to...
-       (bfd_aarch64_erratum_835769_scan): Define.
-       (elfNN_aarch64_size_stubs): Delete erratum_835769_fixes,
-       erratum_835769_fix_table_size, i and associated code.  Relocate
-       call to _bfd_aarch64_erratum_835769_scan.  Delete adhoc stub size
-       correction.  Delete construction of stub entry from
-       erratum_835769_fixes array.
-
-2015-03-24  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-
-       * elfnn-aarch64.c (elfNN_aarch64_size_stubs): Use
-       _bfd_aarch64_add_stub_entry_in_group.
-
-2015-03-23  Keith Seitz  <keiths@redhat.com>
-
-       * elfnn-aarch64.c (_bfd_aarch64_create_or_find_stub_sec): Add
-       missing ';'.
-
-2015-03-04  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-
-       * elfnn-aarch64.c (elfNN_aarch64_size_stubs): Factor out
-       stub resize code into...
-       (bfd_aarch64_resize_stubs): Define.
-
-2015-03-23  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-
-       * elfnn-aarch64.c (_bfd_aarch64_create_or_find_stub_sec): Factor stub
-       creation code into...
-       (bfd_aarch64_create_stub_section): Define.
-
-2015-03-23  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-
-       * elfnn-aarch64.c (_bfd_aarch64_create_or_find_stub_sec): Rename
-       from elf_aarch64_create_or_find_stub_sec.
-       (_bfd_aarch64_add_stub_entry_in_group): Rename from
-       elfNN_aarch64_add_stub.  Call
-       _bfd_aarch64_create_or_find_stub_sec.
-       (elfNN_aarch64_size_stubs, elfNN_aarch64_size_stubs): Call
-       _bfd_aarch64_add_stub_entry_in_group.
-
-2015-03-23  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-
-       * elfnn-aarch64.c (erratum_835769_scan) Add comment.  Reverse
-       sense of boolean return.
-       (elfNN_aarch64_size_stubs): Adjust for above.
-
-2015-03-23  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-
-       * elfnn-aarch64.c (elf_aarch64_create_or_find_stub_sec):
-       Remove unused parameter.
-       (elfNN_aarch64_size_stubs): Adjust for above.
-
-2015-03-23  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-
-       * elfnn-aarch64.c (elfNN_aarch64_size_stubs): Remove bfd_indx.
-
-2015-03-23  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-
-       * elfnn-aarch64.c (aarch64_erratum_835769_fixes)
-       (num_aarch64_erratum_835769_fixes): Remove.
-       (elfNN_aarch64_size_stubs): Remove assignments to above.
-
-       * elfxx-aarch64.c (decode_add_imm, decode_movw_imm)
-       (decode_tst_branch_ofs_14, decode_ld_lit_ofs_19)
-       (decode_cond_branch_ofs_19, decode_branch_ofs_26): Remove.
-
 2015-01-05  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR ld/17773
index d7e37ac7377109f886b3ae78b4713ec4b425ada4..b9031fc569cf044270312547a3aab4313961ce40 100644 (file)
@@ -1,3 +1,157 @@
+2016-10-20  Adhemerval Zanella  <adhemerval.zanella@linaro.org>
+
+       Backport from 2.25.
+       
+       2015-01-13  Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+       * elfnn-aarch64.c (elfNN_aarch64_final_link_relocate): Use SYMBOLIC_BIND
+       to check if a symbol should be bound symbolically.
+
+       2015-07-25  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+       * elf32-arm.c (elf32_arm_final_link_relocate): Use SYMBOLIC_BIND to
+       check if a symbol should be bound symbolically.
+       * elf32-hppa.c (elf32_hppa_check_relocs,
+       elf32_hppa_adjust_dynamic_symbol, elf32_hppa_relocate_section,
+       elf32_hppa_finish_dynamic_symbol): Likewise.
+       * elf32-m68k.c (elf_m68k_check_relocs,
+       elf_m68k_relocate_section): Likewise.
+       * elf32-nios2.c (nios2_elf32_relocate_section,
+       nios2_elf32_check_relocs, allocate_dynrelocs): Likewise.
+       * elf32-tic6x.c (elf32_tic6x_finish_dynamic_symbol,
+       elf32_tic6x_relocate_section): Likewise.
+
+       2015-04-01  Tejas Belagod  <tejas.belagod@arm.com>
+                   Marcus Shawcroft  <marcus.shawcroft@arm.com>
+                   Jiong Wang  <jiong.wang@arm.com>
+
+       * bfd-in.h (bfd_elf64_aarch64_set_options)
+       (bfd_elf32_aarch64_set_options): Add parameter.
+       * bfd-in2.h: Regenerated.
+       * elfnn-aarch64.c (aarch64_erratum_843419_stub)
+       (_bfd_aarch64_adrp_p, _bfd_aarch64_erratum_843419_sequence_p)
+       (_bfd_aarch64_erratum_843419_stub_name)
+       (_bfd_aarch64_erratum_843419_fixup)
+       (_bfd_aarch64_erratum_843419_scan)
+       (_bfd_aarch64_erratum_843419_branch_to_stub)
+       (_bfd_aarch64_erratum_843419_p): Define.
+       (enum elf_aarch64_stub_type): Define
+       aarch64_stub_erratum_843419_veneer.
+       (struct elf_aarch64_stub_hash_entry): Define adrp_offset.
+       (struct elf_aarch64_link_hash_table): Define fix_erratum_843419
+       and fix_erratum_843419_adr.
+       (stub_hash_newfunc): Initialize adrp_offset;
+       (_bfd_aarch64_add_stub_entry_after): Define.
+       (aarch64_map_one_stub, aarch64_build_one_stub)
+       (aarch64_size_one_stub): Handle
+       aarch64_stub_erratum_843419_veneer.
+       (_bfd_aarch64_resize_stubs): Round stub section size.
+       (elfNN_aarch64_size_stubs): Add scan for 843419.
+       (bfd_elfNN_aarch64_set_options): Add parameter. Initialize
+       fix_erratum_843419 and fix_erratum_843419_adr.
+       (struct erratum_835769_branch_to_stub_data): Add info.
+       (elfNN_aarch64_write_section): Initialise info.  Handle 843419.
+       (elfNN_aarch64_size_dynamic_sections): Handle 843419.
+       * elfxx-aarch64.c (_bfd_aarch64_decode_adrp_imm)
+       (_bfd_aarch64_sign_extend): Define.
+       (reencode_adr_imm): Remove static. Rename to:
+       (_bfd_aarch64_reencode_adr_imm): Define.
+       (_bfd_aarch64_elf_put_addend): Call _bfd_aarch64_reencode_adr_imm.
+       * elfxx-aarch64.h (AARCH64_ADR_OP, AARCH64_ADRP_OP)
+       (AARCH64_ADRP_OP_MASK, _bfd_aarch64_sign_extend)
+       (_bfd_aarch64_decode_adrp_imm, _bfd_aarch64_reencode_adr_imm):
+       Define.
+
+       2015-03-25  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+       * elfnn-aarch64.c (_bfd_aarch64_resize_stubs): Adjust stub section
+       size for initial branch.
+       (elfNN_aarch64_build_stubs): Write initial branch.
+       _bfd_aarch64_decode_(elfNN_aarch64_output_arch_local_syms): Write
+       mapping symbol on initial branch.
+
+       2015-03-25  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+       * elfnn-aarch64.c (_bfd_aarch64_erratum_835769_scan):
+       Update erratum count.
+
+       2015-03-24  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+       * elfnn-aarch64.c (_bfd_aarch64_create_or_find_stub_sec): Factor
+       code into:
+       (_bfd_aarch64_get_stub_for_link_section): Define.
+
+       2015-03-24  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+       * elfnn-aarch64.c (_bfd_aarch64_create_or_find_stub_sec): Adjust
+       update of section_group[].stub_sec.
+
+       2015-03-24  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+       * elfnn-aarch64.c (struct aarch64_erratum_835769_fix) Remove.
+       (erratum_835769_scan) Drop fix_table_size_p and fixes_p arguments.
+       Delete fixes, fix_table_size and associated code.  Call
+       _bfd_aarch64_add_stub_entry_in_group. Rename to...
+       (bfd_aarch64_erratum_835769_scan): Define.
+       (elfNN_aarch64_size_stubs): Delete erratum_835769_fixes,
+       erratum_835769_fix_table_size, i and associated code.  Relocate
+       call to _bfd_aarch64_erratum_835769_scan.  Delete adhoc stub size
+       correction.  Delete construction of stub entry from
+       erratum_835769_fixes array.
+
+       2015-03-24  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+       * elfnn-aarch64.c (elfNN_aarch64_size_stubs): Use
+       _bfd_aarch64_add_stub_entry_in_group.
+
+       2015-03-23  Keith Seitz  <keiths@redhat.com>
+
+       * elfnn-aarch64.c (_bfd_aarch64_create_or_find_stub_sec): Add
+       missing ';'.
+
+       2015-03-04  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+       * elfnn-aarch64.c (elfNN_aarch64_size_stubs): Factor out
+       stub resize code into...
+       (bfd_aarch64_resize_stubs): Define.
+
+       2015-03-23  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+       * elfnn-aarch64.c (_bfd_aarch64_create_or_find_stub_sec): Factor stub
+       creation code into...
+       (bfd_aarch64_create_stub_section): Define.
+
+       2015-03-23  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+       * elfnn-aarch64.c (_bfd_aarch64_create_or_find_stub_sec): Rename
+       from elf_aarch64_create_or_find_stub_sec.
+       (_bfd_aarch64_add_stub_entry_in_group): Rename from
+       elfNN_aarch64_add_stub.  Call
+       _bfd_aarch64_create_or_find_stub_sec.
+       (elfNN_aarch64_size_stubs, elfNN_aarch64_size_stubs): Call
+       _bfd_aarch64_add_stub_entry_in_group.
+
+       2015-03-23  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+       * elfnn-aarch64.c (erratum_835769_scan) Add comment.  Reverse
+       sense of boolean return.
+       (elfNN_aarch64_size_stubs): Adjust for above.
+
+       2015-03-04  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+       * elfnn-aarch64.c (elf_aarch64_create_or_find_stub_sec):
+       Remove unused parameter.
+       (elfNN_aarch64_size_stubs): Adjust for above.
+       * elfnn-aarch64.c (elfNN_aarch64_size_stubs): Remove bfd_indx.
+
+       * elfnn-aarch64.c (aarch64_erratum_835769_fixes)
+       (num_aarch64_erratum_835769_fixes): Remove.
+       (elfNN_aarch64_size_stubs): Remove assignments to above.
+
+       * elfxx-aarch64.c (decode_add_imm, decode_movw_imm)
+       (decode_tst_branch_ofs_14, decode_ld_lit_ofs_19)
+       (decode_cond_branch_ofs_19, decode_branch_ofs_26): Remove.
+
 2015-10-06  Adhemerval Zanella  <adhemerval.zanella@linaro.org>
 
        Linaro binutils 2.25-2015.10 released.
index df9c5c830c7f76ece8d5437e6e3a7400988722f8..627940a381467dbb7d387d2e5c61904179078f6b 100644 (file)
-2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
+2014-12-23  Tristan Gingold  <gingold@adacore.com>
 
-       * config/tc-aarch64.c (aarch64_hint_opt_hsh): New.
-       (parse_barrier_psb): New.
-       (parse_operands): Add case for AARCH64_OPND_BARRIER_PSB.
-       (md_begin): Set up aarch64_hint_opt_hsh.
+       * configure: Regenerate.
 
+2014-12-23  Tristan Gingold  <gingold@adacore.com>
+
+       * configure: Regenerate.
+
+2014-12-19  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+       * config/tc-mips.c (md_apply_fix): Apply alignment check
+       to the symbol and offset rather than *valP for
+       BFD_RELOC_MIPS_18_PCREL_S3.  Also update the error message
+       for BFD_RELOC_MIPS_19_PCREL_S2.
+
+2014-11-18  Igor Zamyatin  <igor.zamyatin@intel.com>
+
+       * config/tc-i386-intel.c (i386_operator): Remove last argument
+       from lex_got call.
+       * config/tc-i386.c (reloc): Remove bnd_prefix from parameters'
+       list.  Return always BFD_RELOC_32_PCREL.
+       * (output_branch): Remove condition for BFD_RELOC_X86_64_PC32_BND.
+       * (output_jump): Update call to reloc accordingly.
+       * (output_interseg_jump): Likewise.
+       * (output_disp): Likewise.
+       * (output_imm): Likewise.
+       * (x86_cons_fix_new): Likewise.
+       * (lex_got): Remove bnd_prefix from parameters' list in macro and
+       declarations. Don't use BFD_RELOC_X86_64_PLT32_BND.
+       * (x86_cons): Update call to lex_got accordingly.
+       * (i386_immediate): Likewise.
+       * (i386_displacement): Likewise.
+       * (md_apply_fix): Don't use BFD_RELOC_X86_64_PLT32_BND nor
+       BFD_RELOC_X86_64_PC32_BND.
+       * (tc_gen_reloc): Likewise.
+
+2014-11-17  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
+
+       * config/tc-aarch64.c (aarch64_cpus): Add "xgene2".
+       * doc/c-aarch64.texi: Document it.
+
+2014-11-17  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
+
+       * config/tc-aarch64.c (aarch64_cpus): Add "xgene1".
+       * doc/c-aarch64.texi: Rename xgene-1 to xgene1.
+
+2014-11-18  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+       Apply trunk patch:
+       * config/tc-aarch64.c (aarch64_cpus): Add CRC feature for
+       cortex-A53 and cortex-A57.
+
+2014-11-17  Nick Clifton  <nickc@redhat.com>
+
+       Apply trunk patches:
+
+       2014-11-13  Nick Clifton  <nickc@redhat.com>
+
+       PR binutils/17512
+       * config/obj-coff.c (coff_obj_symbol_new_hook): Set the is_sym
+       field.
+
+2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
+
+       * config/tc-i386.c (cpu_arch): Add .avx512vbmi.
+       * doc/c-i386.texi: Document it.
+
+2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
+
+       * config/tc-i386.c (cpu_arch): Add .avx512ifma.
+       * doc/c-i386.texi: Document it.
+
+2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
+
+       * config/tc-i386.c (cpu_arch): Add .pcommit.
+       * doc/c-i386.texi: Document it.
+
+2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
+
+       * config/tc-i386.c (cpu_arch): Add .clwb.
+       * doc/c-i386.texi: Document it.
+
+2014-11-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * config/tc-i386.c (cpu_arch): Re-arrange avx512* and xsave*
+       items.
+
+       * doc/c-i386.texi: Re-arrange avx512* and xsave*.  Add
+       clflushopt and se1.  Remove duplicated entries.
+
+2014-11-12  Alan Modra  <amodra@gmail.com>
+
+       PR ld/17482
+       * config/tc-i386.c (output_insn): Don't test x86_elf_abi when
+       not ELF.
+
+2014-11-11  Nick Clifton  <nickc@redhat.com>
+
+       * po/uk.po: Updated Ukranian translation.
+
+2014-11-10  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+       Apply trunk patch:
+       * config/tc-mips.c (mips_elf_final_processing): Add INSN_ISA32R6
+       and INSN_ISA64R6 support.
+
+2014-11-07  H.J. Lu  <hongjiu.lu@intel.com>
+
+       Apply trunk patch:
+       2014-11-07  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR ld/17482
+       * config/tc-i386.c (output_insn): Add a dummy REX_OPCODE prefix
+       for structions with R_X86_64_GOTTPOFF relocation for x32 if needed.
+
+2014-11-03  Nick Clifton  <nickc@redhat.com>
+
+       Apply trunk patch:
+       2014-11-03  Nick Clifton  <nickc@redhat.com>
+       * config/tc-msp430.c (msp430_srcoperand): Fix range test for
+       20-bit values.
+
+2014-10-30  Nick Clifton  <nickc@redhat.com>
+
+       Apply trunk patches
+       2014-10-30  Dr Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
+       * config/tc-aarch64.h (MAX_MEM_FOR_RS_ALIGN_CODE): Define to 7.
+       * config/tc-aarch64.c (aarch64_handle_align): Rewrite to handle
+       large alignments with a constant fragment size of
+       MAX_MEM_FOR_RS_ALIGN_CODE.
+
+2014-10-29  Nick Clifton  <nickc@redhat.com>
+
+       * po/uk.po: New Ukranian translation.
+
+2014-10-28  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+       Apply trunk patches
+       2014-10-22  Matthew Fortune  <matthew.fortune@imgtec.com>
+       * doc/as.texinfo: Update the MIPS FP ABI descriptions.
+       * doc/c-mips.texi: Spell check and correct throughout.
+
+2014-10-28  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+       Apply trunk patches
+       2014-10-21  Maciej W. Rozycki  <macro@codesourcery.com>
+       * config/tc-mips.c (s_insn): Set file options.
+
+2014-10-28  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+       Apply trunk patches
+       2014-10-17  Matthew Fortune  <matthew.fortune@imgtec.com>
+       * doc/c-mips.texi: Fix bad @value references.
+
+2014-10-28  Alan Modra  <amodra@gmail.com>
+       Apply trunk patches
+       2014-10-18  Alan Modra  <amodra@gmail.com>
+       PR 17493
+       * write.c (adjust_reloc_syms): Don't allow symbols in reg_section
+       to be reduced to reg_section section symbol.
+       * gas/config/tc-i386.c (i386_finalize_immediate): Reject all
+       reg_section immediates.
+
+       2014-10-15  Chen Gang  <gang.chen.5i5j@gmail.com>
+       * config/tc-tic4x.c (md_assemble): Correct strncat size.
+
+2014-10-15  Tristan Gingold  <gingold@adacore.com>
+
+       * configure: Regenerate.
+
+2014-10-14  Tristan Gingold  <gingold@adacore.com>
+
+       * NEWS: Add marker for 2.25.
+
+2014-10-14  Alan Modra  <amodra@gmail.com>
+
+       PR 17453
+       * config/tc-i386.c (fits_in_signed_long): Use unsigned param and
+       expression to avoid signed overflow.
+       (fits_in_signed_byte, fits_in_unsigned_byte, fits_in_unsigned_word,
+       fits_in_signed_word, fits_in_unsigned_long): Similarly.
+       * expr.c (operand <'-'>): Avoid signed overflow.
+       * read.c (s_comm_internal): Likewise.
+
+2014-10-14  Alan Modra  <amodra@gmail.com>
+
+       * config/tc-sparc.c (sparc_md_end): Fix unused variable warnings.
+
+2014-10-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * config/tc-sparc.c (v9a_asr_table): Entry for %cps removed.
+       (sparc_arch_table): Remove the HWCAP_RANDOM, HWCAP_TRANS and
+       HWCAP_ASI_CACHE_SPARING from the architectures using them.
+       (HWS_V8): New define.
+       (HWS_V9): Likewise.
+       (HWS_VA): Likewise.
+       (HWS_VB): Likewise.
+       (HWS_VC): Likewise.
+       (HWS_VD): Likewise.
+       (HWS_VE): Likewise.
+       (HWS_VV): Likewise.
+       (sparc_arch): Use the HWS_* macros.  Fix the `sparc4' architecture
+       to cover the HWCAP_ASI_BLK_INIT and HWCAP_IMA capabilities.
+       (hwcap_seen): Variable widened to 64 bits.
+       (hwcap_allowed): Likewise.
+       (sparc_arch): new field `hwcap2_allowed'.
+       (sparc_arch_table): provide hwcap2_allowed values for existing
+       archs.
+       (sparc_md_end): Add a HWCAPS2 object attribute to the elf object
+       in case any of the HWCAP2_* caps are used.
+       (sparc_ip): Take into account the new hwcaps2 bitmap to build the
+       list of seen/allowed hwcaps.
+       (get_hwcap_name): Argument widened to 64 bits to handle HWCAP2
+       bits.
+       (HWS_VM): New define.
+       (HWS2_VM): Likewise.
+       (sparc_arch): New architectures `sparc5', `v9m' and `v8plusm'.
+       (v9a_asr_table): Add the %mwait (%asr28) ancillary state register
+       to the table.
+       (sparc_ip): Handle the %mcdper ancillary state register as an
+       operand.
+       (sparc_ip): Handle } arguments as fdrd floating point registers
+       (double) that are the same than frs1.
+       * doc/c-sparc.texi (Sparc-Opts): Document the -Av9e, -Av8pluse and
+       -xarch=v9e command line options.  Also fix the description of the
+       -Av9v and -Av8plusv command line options.
+       Document the -Av9m, -Av8plusm,-Asparc5, -xarch=v9m and
+       -xarch=sparc5 command line options.
+
+2014-09-29  Terry Guo  <terry.guo@arm.com>
+
+       * as.c (create_obj_attrs_section): Move it and call it from ...
+       * write.c (create_obj_attrs_section): ... here.
+       (subsegs_finish_section): Refactored.
+
+2014-09-27  Alan Modra  <amodra@gmail.com>
+
+       * dwarf2dbg.c (all_segs_hash): Delete.
+       (get_line_subseg): Delete last_seg, last_subseg, last_line_subseg.
+       Retrieve line_seg for section via seg_info.
+       * subsegs.h (segment_info_typet): Add dwarf2_line_seg.
+
+2014-09-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR gas/17421
+       * config/tc-i386.c (md_assemble): Disallow VEX/EVEX encoded
+       instructions in 16-bit mode.
+
+2014-09-22  Alan Modra  <amodra@gmail.com>
+
+       * config/tc-m68k.c (md_assemble): Add assert to work around
+       bogus trunk gcc warning.
+       * config/tc-pj.h (md_convert_frag): Warning fix.
+       * config/tc-xtensa.c (xg_assemble_vliw_tokens): Warning fix.
+
+2014-09-17  Tristan Gingold  <gingold@adacore.com>
+
+       * config/tc-arm.c (move_or_literal_pool, add_to_lit_pool): Use
+       bfd_int64_t instead of int64_t.
+
+2014-09-16  Ilya Tocar  <ilya.tocar@intel.com>
+
+       * config/tc-i386.c (evexrcig): New.
+       (build_evex_prefix): Force rounding bits.
+       (OPTION_MEVEXRCIG): New.
+       (md_longopts): Add mevexrcig.
+       (md_parse_option): Handle OPTION_MEVEXRCIG.
+       (md_show_usage): Document mevexrcig.
+       * doc/c-i386.texi (mevexrcig): Document new option.
+
+2014-09-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
+
+       * config/tc-nds32.c (nds32_fsrs, nds32_fdrs, nds32_gprs): Remove.
+       (relax_table): Add new relaxation pattern.
+       (do_pseudo_la_internal, do_pseudo_ls_bhw): Expand for PIC suffix.
+       (do_pseudo_move, do_pseudo_neg, do_pseudo_pushpopm): Fix.
+       (get_range_type, nds32_elf_record_fixup_exp, nds32_get_align,
+       nds32_elf_build_relax_relation, md_assemble, invalid_prev_frag,
+       nds32_relax_frag, md_estimate_size_before_relax): Adjust relaxation.
+       (relocation_table): Remove.
+       (relax_ls_table): Load-store relaxation pattern.
+       (hint_map): Define-use chain pattern.
+       (nds32_find_reloc_table, nds32_match_hint_insn): Analysis
+       relaxation pattern.
+       (nds32_parse_name): Parse PIC suffix.
+       * config/tc-nds32.h: Declare.
+
+2014-09-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * config/tc-i386.c (OPTION_omit_lock_prefix): Renamed to ...
+       (OPTION_OMIT_LOCK_PREFIX): This.
+       (md_longopts): Updated.
+       (md_parse_option): Likewise.
+
+2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
+           Matthew Fortune  <matthew.fortune@imgtec.com>
+
+       * config/tc-mips.c (mips_nan2008): New static global.
+       (mips_flag_nan2008): Removed.
+       (LL_SC_FMT): New define.
+       (COP12_FMT): Updated.
+       (ISA_IS_R6): New define.
+       (ISA_HAS_64BIT_REGS): Add mips64r6.
+       (ISA_HAS_DROR): Likewise.
+       (ISA_HAS_64BIT_FPRS): Add mips32r6 and mips64r6.
+       (ISA_HAS_ROR): Likewise.
+       (ISA_HAS_ODD_SINGLE_FPR): Likewise.
+       (ISA_HAS_MXHC1): Likewise.
+       (hilo_interlocks): Likewise.
+       (md_longopts): Likewise.
+       (ISA_HAS_LEGACY_NAN): New define.
+       (options): Add OPTION_MIPS32R6 and OPTION_MIPS64R6.
+       (mips_ase): Add field rem_rev.
+       (mips_ases): Updated to add which ISA an ASE was removed in.
+       (mips_isa_rev): Add support for mips32r6 and mips64r6.
+       (mips_check_isa_supports_ase): Add support to check if an ASE
+       has been removed in the specified MIPS ISA revision.
+       (validate_mips_insn): Skip '-' character.
+       (macro_build): Likewise.
+       (mips_check_options): Prevent R6 working with fp32, mips16,
+       micromips, or branch relaxation.
+       (file_mips_check_options): Set R6 floating point registers to
+       64 bit.  Also deal with the nan2008 option.
+       (limited_pcrel_reloc_p): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
+       BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
+       BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
+       BFD_RELOC_LO16_PCREL.
+       (operand_reg_mask): Add support for OP_SAME_RS_RT, OP_CHECK_PREV
+       and OP_NON_ZERO_REG.
+       (match_check_prev_operand): New static function.
+       (match_same_rs_rt_operand): New static function.
+       (match_non_zero_reg_operand): New static function.
+       (match_operand): Added entries for: OP_SAME_RS_RT, OP_CHECK_PREV
+       and OP_NON_ZERO_REG.
+       (insns_between): Added case to deal with forbidden slots.
+       (append_insn): Added support for relocs: BFD_RELOC_MIPS_21_PCREL_S2
+       and BFD_RELOC_MIPS_26_PCREL_S2.
+       (match_insn): Add support for operands -A, -B, +' and +".  Also
+       skip '-' character.
+       (mips_percent_op): Add entries for %pcrel_hi and %pcrel_lo.
+       (md_parse_option): Add support for mips32r6 and mips64r6.  Also
+       update the nan option handling.
+       (md_pcrel_from): Add cases for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
+       BFD_RELOC_MIPS_26_PCREL_S2.
+       (mips_force_relocation): Prevent forced relaxation for MIPS r6.
+       (md_apply_fix): Add support for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
+       BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
+       BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
+       BFD_RELOC_LO16_PCREL.
+       (s_mipsset): Add support for mips32r6 and mips64r6.
+       (s_nan): Update to support the new nan2008 framework.
+       (tc_gen_reloc): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
+       BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
+       BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
+       BFD_RELOC_LO16_PCREL.
+       (mips_elf_final_processing): Updated to use the mips_nan2008.
+       (mips_cpu_info_table): Add entries for mips32r6 and mips64r6.
+       (macro): Enable ldc2, sdc2, ll, lld, swc2, sc, scd, cache, pref
+       macros for R6.
+       (mips_fix_adjustable): Make PC relative R6 relocations relative
+       to the symbol and not the section.
+       * configure.ac: Add support for mips32r6 and mips64r6.
+       * configure: Regenerate.
+       * doc/c-mips.texi: Document the -mips32r6 and -mips64r6 command line
+       options.
+       * doc/as.texinfo: Likewise.
+
+2014-09-15  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+       * tc-mips.c (check_fpabi): Move softfloat and singlefloat
+       checks higher.
+
+2014-09-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * config/tc-sparc.c (sparc_ip): Update the set of allowed hwcaps
+       when bumping the current architecture.
+       (md_begin): Adjust the highetst architecture level also when a
+       specific architecture is not requested.
+
+2014-09-12  Andrew Bennett  <andrew.bennett@imgtec.com>
+
+       * configure.tgt: Add mips*-img-elf* target triple.
+
+2014-09-12  Alan Modra  <amodra@gmail.com>
+
+       * config/tc-i386.c (match_template): Remove redundant "!!" testing
+       single-bit bitfields.
+       (build_modrm_byte): Don't compare single-bit bitfields to "1".
+
+2014-09-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * config/tc-arm.c (arm_cpus): Add cortex-a17.
+
+2014-09-03  Jiong Wang  <jiong.wang@arm.com>
+
+       * config/tc-aarch64.c (parse_sys_reg): Remove the restriction on op0
+       field.
+
+2014-09-03  Jiong Wang  <jiong.wang@arm.com>
+
+       * config/tc-aarch64.c (parse_operands): Recognize PAIRREG.
+       (aarch64_features): Add entry for lse extension.
+
+2014-08-26  Jiong Wang  <jiong.wang@arm.com>
+
+       * config/tc-arm.c (aeabi_set_public_attributes): Update selected_cpu
+       based on the info we got during parsing.
+       (arm_handle_align): Make sure the p2align expanding logic under thumb
+       unchanged.
+
+2014-08-26  Maciej W. Rozycki  <macro@codesourcery.com>
+
+       * config/tc-mips.c (macro) <M_SAA_AB>: Remove duplicate code and
+       jump to...
+       <M_SAAD_AB>: ... here.  Assert that !microMIPS.
+
+2014-08-26  Jan-Benedict Glaw  <jbglaw@lug-owl.de>
+
+       * config/tc-moxie.h (md_convert_frag): Silence warning.
+
+2014-08-22  Richard Henderson  <rth@redhat.com>
+
+       * config/tc-aarch64.c (tc_aarch64_regname_to_dw2regnum): Fix
+       register number for vector register types.
+       * config/tc-aarch64.h (DWARF2_LINE_MIN_INSN_LENGTH): Set to 4.
+       (DWARF2_CIE_DATA_ALIGNMENT): Set to -8.
+
+2014-08-22  Maciej W. Rozycki  <macro@codesourcery.com>
+
+       * config/tc-ppc.c (md_assemble): Only set the PPC_APUINFO_VLE
+       flag if both the processor and opcode flags match.
+
+2014-08-22  Maciej W. Rozycki  <macro@codesourcery.com>
+
+       * config/tc-arm.c (add_to_lit_pool): Preinitialize `imm1'.
+
+2014-08-20  Maciej W. Rozycki  <macro@codesourcery.com>
+
+       * dw2gencfi.c (make_debug_seg): Replace leading spaces with tabs.
+       (dot_cfi_val_encoded_addr, output_cfi_insn): Likewise.
+       (output_cie, cfi_change_reg_numbers, cfi_finish): Likewise.
+
+2014-08-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * config/tc-arm.c (parse_ifimm_zero): New function.
+       (enum operand_parse_code): Add OP_RSVD_FI0 value.
+       (parse_operands): Handle OP_RSVD_FI0.
+       (asm_opcode_insns): Use RSVD_FI0 for second operand of vcmp, vcmpe.
+
+2014-08-20  Alan Modra  <amodra@gmail.com>
+
+       * Makefile.am: Typo fix.
+       * Makefile.in: Regenerate.
+       * po/POTFILES.in: Regenerate.
+
+2014-08-19  Andreas Tobler  <andreast@fgznet.ch>
+
+       * Makefile.am: Add FreeBSD ARM support.
+       * Mafefile.in: Regenerate.
+       * configure.tgt: Add FreeBSD ARM support.
+       * config/te-armfbsdeabi.h: New file.
+       * config/te-armfbsdvfp.h: Likewise.
+
+2014-08-19  Alan Modra  <amodra@gmail.com>
+
+       * configure: Regenerate.
+
+2014-08-18  Nick Clifton  <nickc@redhat.com>
+
+       * config/tc-rl78.c (md_apply_fix): Correct handling of small sized
+       RELOC_RL78_DIFF fixups.
+
+2014-08-18  Alan Modra  <amodra@gmail.com>
+
+       * read.c (parse_mri_cons): Warning fix.
+
+2014-08-14  Alan Modra  <amodra@gmail.com>
+
+       * configure.ac: Move ACX_LARGEFILE after LT_INIT.
+       * config.in: Regenerate.
+       * configure: Regenerate.
+
+2014-08-06  Ilya Tocar  <ilya.tocar@intel.com>
+
+       * config/tc-i386.c (omit_lock_prefix): New.
+       (output_insn): Omit lock prefix if omit_lock_prefix is true.
+       (OPTION_omit_lock_prefix): New.
+       (md_longopts): Add momit-lock-prefix.
+       (md_parse_option): Handle momit-lock-prefix.
+       (md_show_usage): Add momit-lock-prefix=[no|yes].
+       * doc/c-i386.texi (momit-lock-prefix): Document.
+
+2014-08-01  Takashi Yoshii  <yoshii.takashi@renesas.com>
+
+       PR 10378
+       * config/tc-sh.c (tc_gen_reloc): Fix initialization of addend in
+       SWITCH_TABLE case.
+
+2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+       * config/tc-mips.c: Rename INSN_LOAD_COPROC_DELAY to INSN_LOAD_COPROC
+       and INSN_COPROC_MOVE_DELAY to INSN_COPROC_MOVE throughout.
+
+2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+       * config/tc-mips.c (mips_flags_frag): New static global.
+       (struct mips_set_options): Add oddspreg field.
+       (file_mips_opts, mips_opts): Initialize oddspreg.
+       (ISA_HAS_ODD_SINGLE_FPR): Add CPU argument and update for R5900 and
+       Loongson-3a.
+       (enum options, md_longopts, md_parse_option): Add -mfpxx, -modd-spreg
+       and -mno-odd-spreg options.
+       (md_begin): Create .MIPS.abiflags section.
+       (fpabi_incompatible_with, fpabi_requires): New static function.
+       (check_fpabi): Likewise.
+       (mips_check_options): Handle fp=xx and oddspreg restrictions.
+       (file_mips_check_options): Set oddspreg by default for fp=xx.
+       (mips_oddfpreg_ok): Re-write function.
+       (check_regno): Check odd numbered registers regardless of FPR size.
+       For fp != 32 use as_bad instead of as_warn.
+       (match_float_constant): Rewrite check regarding FP register width.  Add
+       support for generating constants when MXHC1 is present.  Handle fp=xx
+       to comply with the ABI.
+       (macro): Update M_LI_DD similarly to match_float_constant.  Generate
+       MTHC1 when available.  Check that correct code can be generated for
+       fp=xx and fp=64 ABIs.
+       (parse_code_option, s_mipsset): Add fp=xx, oddspreg and nooddspreg
+       options.
+       (mips_convert_ase_flags): New static function.
+       (mips_elf_final_processing): Use fpabi == Val_GNU_MIPS_ABI_FP_OLD_64
+       to determine when to add the EF_MIPS_FP64 flag.  Populate the
+       .MIPS.abiflags section.
+       (md_mips_end): Update .gnu_attribute based on command line and .module
+       as applicable.  Use check_fpabi to ensure .gnu.attribute and command
+       line/.module options are consistent.
+       * doc/as.texinfo: Add missing -mgp64/-mfp64 options and document new
+       -mfpxx, -modd-spreg and -mno-odd-spreg options.
+       * doc/c-mips.texi: Document -mfpxx, -modd-spreg, -mno-odd-spreg,
+       gnu_attribute values and FP ABIs.
+
+2014-07-27  Joel Sherrill <joel.sherrill@oarcorp.com>
+
+       Add RTEMS target support and simplify matching
+
+       * gas/configure.tgt (or1k*-*-rtems*): Ensure a match.
+       (or1k*-*-*): Use or1k* to match or1knd and or1kZ.
+
+2014-07-27  Anthony Green  <green@moxielogic.com>
+
+       * configure.tgt (generic_target): Add moxie-*-moxiebox*
+       * config/tc-moxie.c: Remove moxie_target_format.
+       (md_begin): Set default target_big_endian.
+       * config/tc-moxie.h: Only set TARGET_BYTES_BIG_ENDIAN if unset.
+       (TARGET_FORMAT): Set based on target_big_endian.
+
+2014-07-26  Alan Modra  <amodra@gmail.com>
+
+       * config/bfin-parse.y: Don't include obstack.h.
+       * config/obj-aout.c: Likewise.
+       * config/obj-coff.c: Likewise.
+       * config/obj-som.c: Likewise.
+       * config/tc-bfin.c: Likewise.
+       * config/tc-i960.c: Likewise.
+       * config/tc-rl78.c: Likewise.
+       * config/tc-rx.c: Likewise.
+       * config/tc-tic4x.c: Likewise.
+       * expr.c: Likewise.
+       * listing.c: Likewise.
+       * config/obj-elf.c (elf_file_symbol): Make name_length a size_t.
+       * config/tc-aarch64.c (symbol_locate): Likewise.
+       * config/tc-arm.c (symbol_locate): Likewise.
+       * config/tc-mmix.c (mmix_handle_mmixal): Make len_0 a size_t.
+       * config/tc-score.c (s3_build_score_ops_hsh): Make len a size_t.
+       (s3_build_dependency_insn_hsh): Likewise.
+       * config/tc-score7.c (s7_build_score_ops_hsh): Likewise.
+       (s7_build_dependency_insn_hsh): Likewise.
+       * frags.c (frag_grow): Make parameter a size_t, and use size_t locals.
+       (frag_new): Make parameter a size_t.
+       (frag_var_init): Make max_chars and var parameters size_t.
+       (frag_var, frag_variant): Likewise.
+       (frag_room): Return a size_t.
+       (frag_align_pattern): Make n_fill parameter a size_t.
+       * frags.h: Update function prototypes.
+       * symbols.c (save_symbol_name): Make name_length a size_t.
+
+2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
+           Alexander Ivchenko  <alexander.ivchenko@intel.com>
+           Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
+           Sergey Lega  <sergey.s.lega@intel.com>
+           Anna Tikhonova  <anna.tikhonova@intel.com>
+           Ilya Tocar  <ilya.tocar@intel.com>
+           Andrey Turetskiy  <andrey.turetskiy@intel.com>
+           Ilya Verbin  <ilya.verbin@intel.com>
+           Kirill Yukhin  <kirill.yukhin@intel.com>
+           Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+       * config/tc-i386.c (cpu_arch): Add .avx512dq, CPU_AVX512DQ_FLAGS.
+       * doc/c-i386.texi: Document avx512dq/.avx512dq.
+
+2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
+           Alexander Ivchenko  <alexander.ivchenko@intel.com>
+           Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
+           Sergey Lega  <sergey.s.lega@intel.com>
+           Anna Tikhonova  <anna.tikhonova@intel.com>
+           Ilya Tocar  <ilya.tocar@intel.com>
+           Andrey Turetskiy  <andrey.turetskiy@intel.com>
+           Ilya Verbin  <ilya.verbin@intel.com>
+           Kirill Yukhin  <kirill.yukhin@intel.com>
+           Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+       * config/tc-i386.c (cpu_arch): Add .avx512bw, CPU_AVX512BW_FLAGS.
+       * doc/c-i386.texi: Document avx512bw/.avx512bw.
+
+2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
+           Alexander Ivchenko  <alexander.ivchenko@intel.com>
+           Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
+           Sergey Lega  <sergey.s.lega@intel.com>
+           Anna Tikhonova  <anna.tikhonova@intel.com>
+           Ilya Tocar  <ilya.tocar@intel.com>
+           Andrey Turetskiy  <andrey.turetskiy@intel.com>
+           Ilya Verbin  <ilya.verbin@intel.com>
+           Kirill Yukhin  <kirill.yukhin@intel.com>
+           Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+       * config/tc-i386.c (cpu_arch): Add .avx512vl, CPU_AVX512VL_FLAGS.
+       (build_vex_prefix): Don't abort on VEX.W.
+       (check_VecOperands): Support BROADCAST_1TO4 and BROADCAST_1TO2.
+       (check_VecOperations): Ditto.
+       * doc/c-i386.texi: Document avx512vl/.avx512vl.
+
+2014-07-21  Joel Sherrill  <joel.sherrill@oarcorp.com>
+
+       Add or reactivate or1k-*-rtems*
+       * gas/configure.tgt (or1k-*-rtems*): Add.
+
+2014-07-17  Ilya Tocar  <ilya.tocar@intel.com>
+
+       * config/tc-i386.c (parse_register): Set need_vrex.
+
+2014-07-15  Jiong Wang  <jiong.wang@arm.com>
+
+       * config/tc-arm.c (add_to_lit_pool): Use "inst.operands[1].imm" for
+       sign extension.  Casting the type of imm1 and imm2 to offsetT.  Fix
+       one logic error when checking X_op.
+
+2014-07-14  Andreas Schwab  <schwab@linux-m68k.org>
+
+       * config/tc-m68k.c (md_convert_frag_1): Don't complain with
+       --pcrel about TAB (DBCCLBR, LONG) conversion.
+
+2014-07-12  David Majnemer  <david.majnemer@gmail.com>
+
+       * read.c (assign_symbol): Don't force "set" symbols local for PE.
+
+2014-07-08  Jiong Wang  <jiong.wang@arm.com>
+
+       * config/tc-arm.c (literal_pool): New field "alignment".
+       (find_or_make_literal_pool): Initialize "alignment" to 2.
+       (s_ltorg): Align the pool using value of "alignment"
+       (parse_big_immediate): New parameter "in_exp". Return
+       parsed expression if "in_exp" is not null.
+       (parse_address_main): Invoke "parse_big_immediate" for
+       constant parameter.
+       (add_to_lit_pool): Add one parameter 'nbytes'.
+       Split 8 byte entry into two 4 byte entry.
+       Add padding to align 8 byte entry to 8 byte boundary.
+       (encode_arm_cp_address): Generate literal pool entry if possible.
+       (move_or_literal_pool): Generate entry for vldr case.
+       (enum lit_type): New enum type.
+       (do_ldst): Use new enum type.
+       (do_ldstv4): Likewise.
+       (do_t_ldst): Likewise.
+       (neon_write_immbits): Support Thumb-2 mode.
+
+2014-07-07  Barney Stratford  <barney_stratford@fastmail.fm>
+
+       * config/tc-avr.c (avr_operand): Permit referring to r26-r31 by
+       name as [xyz][hl].  Permit using a symbol whoes name begins with
+       â€˜r’ to refer to a register.
+       Allow arbitrary expressions for the P and p operators.
+       (md_apply_fix): Check the BFD_RELOC_AVR_PORT5 and
+       BFD_RELOC_AVR_PORT6 relocations.
+
+2014-07-04  Alan Modra  <amodra@gmail.com>
+
+       * doc/internals.texi: Update "configure.in" comments.
+       * acinclude.m4: Likewise.
+       * config/tc-sparc.c: Likewise.
+
+2014-07-04  Alan Modra  <amodra@gmail.com>
+
+       * configure.ac: Rename from configure.in.
+       * Makefile.in: Regenerate.
+       * config.in: Regenerate.
+       * doc/Makefile.in: Regenerate.
+
+2014-07-04  Alan Modra  <amodra@gmail.com>
+
+       * doc/Makefile.am (CONFIG_STATUS_DEPENDENCIES): Delete.
+       * doc/Makefile.in: Regenerate.
+
+2014-07-04  Alan Modra  <amodra@gmail.com>
+
+       * configure.in: Include bfd/version.m4.
+       (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
+       (BFD_VERSION): Delete.
+       * configure.com: Get bfd version from bfd/version.m4.
+       * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
+       * configure: Regenerate.
+       * Makefile.in: Regenerate.
+       * doc/Makefile.in: Regenerate.
+
+2014-07-01  Barney Stratford   <barney_stratford@fastmail.fm>
+            Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
+            Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
+            Soundararajan  <Sounderarajan.D@atmel.com>
+
+       * config/tc-avr.c (mcu_types): Add avrtiny arch.
+       Add avrtiny arch devices attiny4, attiny5, attiny9, attiny10, attiny20
+       and attiny40.
+       (md_show_usage): Add avrtiny arch in usage message.
+       (avr_operand): validate and issue error for invalid register for
+       avrtiny.
+       add new reloc exp for 16 bit lds/sts instruction.
+       (md_apply_fix): check 16 bit lds/sts operand for out of range and
+       encode.
+       (md_assemble): check ISA for arch and issue diagnostic.
+       * NEWS: Mention new support.
+       * doc/c-avr.texi: Document support for avrtiny architecture.
+
+2014-06-27  Alan Modra  <amodra@gmail.com>
+
+       * config/obj-macho.c (obj_mach_o_set_symbol_qualifier): Don't set
+       SYM_MACHO_FIELDS_NOT_VALIDATED after reporting an error.
+       (obj_mach_o_frob_label): Avoid cascading errors.
+       (obj_mach_o_frob_symbol): Don't set SYM_MACHO_FIELDS_NOT_VALIDATED.
+
+2014-06-18  DJ Delorie  <dj@redhat.com>
+
+       * config/rx-parse.y (BSET, BCLR, BTST, BNOT, BMCMD): Make .B
+       suffix optional.
+
+2014-06-17  Hans-Peter Nilsson  <hp@bitrange.com>
+
+       * config/tc-mmix.c (loc_assert_s): New member frag.
+       (s_loc): Set it.
+       (mmix_md_end): If an error is reported for a LOC expression, patch
+       up the related frag.
+
+2014-06-17  Chris Metcalf  <cmetcalf@tilera.com>
+
+       PR gas/16908
+       * macro.c (buffer_and_nest): Honour #line directives inside
+       macros.
+
+2014-06-17 Jiong Wang <jiong.wang@arm.com>
+
+       * config/tc-arm.c (depr_it_insns): New check for inc/dec sp.
+
+2014-06-17  Hans-Peter Nilsson  <hp@axis.com>
+
+       * config/tc-cris.c (cris_bad): New function.
+       (cris_process_instruction): Where applicable, use it instead of
+       as_bad.
+
+2014-06-16  Nick Clifton  <nickc@redhat.com>
+
+       * config/tc-aarch64.c (md_apply_fix): Ignore unused relocs.
+
+2014-06-16  Jiong Wang  <jiong.wang@arm.com>
+
+       * config/tc-aarch64.c (END_OF_INSN): New macro.
+       (parse_operands): Handle operand given and in wrong format when
+       operand is optional.
+
+2014-06-16  Alan Modra  <amodra@gmail.com>
+
+       * write.h (subsegs_finish): Delete declaration.
+       * write.c (subsegs_finish): Make static.
+       (write_object_file): Call subsegs_finish from here.  Don't print
+       warning and error count here..
+       * as.c (main): ..do so here instead.  Remove dead code for "no
+       object file generated".  Split out count strings to better support
+       internationalisation.  Don't call subsegs_finish. Tidy setting of
+       "keep_it".  Run write_object_file even after errors.
+       (keep_it): Make static.
+       * config/obj-elf.c (elf_frob_symbol): Remove assert.
+       (elf_frob_file_before_adjust): Likewise.
+
+2014-06-16  Alan Modra  <amodra@gmail.com>
+
+       * config/tc-dlx.c (machine_ip): Move initialisation of the_insn
+       earlier.
+
+2014-06-16  Alan Modra  <amodra@gmail.com>
+
+       * config/tc-i386.c (reloc): Don't avoid pcrel check for
+       BFD_RELOC_SIZE64.  Return NO_RELOC on failing pcrel check.
+
+2014-06-16  Alan Modra  <amodra@gmail.com>
+
+       * config/tc-tic6x.c (s_tic6x_ehtype): Clear after frag_more.
+       (tic6x_output_exidx_entry): Likewise.
+       (md_apply_fix): Simplify 1 byte md_number_to_chars.
+
+2014-06-16  Alan Modra  <amodra@gmail.com>
+
+       * config/tc-tic54x.c (tic54x_mlib): Don't write garbage past
+       end of archive to temp file.
+       (tic54x_start_line_hook): Start scan for parallel on next line,
+       not one char into next line (which may overrun the buffer).
+
+2014-06-16  Alan Modra  <amodra@gmail.com>
+
+       * config/tc-vax.c (md_apply_fix): Rewrite.
+       (tc_gen_reloc, vax_cons, vax_cons_fix_new): Style: Use NO_RELOC
+       define rather than the equivalent BFD_RELOC_NONE.
+
+2014-06-16  Alan Modra  <amodra@gmail.com>
+
+       * config/tc-arm.c (s_arm_elf_cons): Initialise after frag_more.
+       (md_apply_fix): Delete now unnecessary zeroing for BFD_RELOC_ARM_GOT*
+       and BFD_RELOC_ARM_TLS* relocs.  Simplify BFD_RELOC_8 case.
+
+2014-06-16  Alan Modra  <amodra@gmail.com>
+
+       * config/tc-cris.c (md_create_long_jump): Follow "short" jump
+       with a nop rather than leaving uninitialised.
+
+2014-06-13  Chen Gang  <gang.chen.5i5j@gmail.com>
+
+       * config/tc-score7.c: Replace sprintf with strcpy where
+       appropriate.
+       (s7_b32_relax_to_b16): Use symbol_get_frag() to access a symbol's
+       frag.
+       * config/tc-score.c (s3_relax_branch_inst16): Likewise.
+       (s3_relax_cmpbranch_inst32): Likewise.
+
+2014-06-07  Alan Modra  <amodra@gmail.com>
+
+       * config/tc-ppc.c (ppc_insert_operand): Handle PPC_OPERAND_SIGNOPT
+       on unsigned fields.  Comment on PPC_OPERAND_SIGNOPT signed fields
+       in 64-bit mode.
+
+2014-06-02  Martin Storsjo  <martin@martin.st>
+
+       * doc/c-aarch64.texi: Fix the documentation on :pg_hi21:.
+
+2014-06-05  Joel Brobecker  <brobecker@adacore.com>
+
+       * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
+       bfd's development.sh.
+       * Makefile.in, configure: Regenerate.
+
+2014-06-03  Nick Clifton  <nickc@redhat.com>
+
+       * config/tc-msp430.c (OPTION_WARN_INTR_NOPS): Use y instead of z.
+       (OPTION_NO_WARN_INTR_NOPS): Use Y instead of Z.
+       * doc/c-msp430.texi: Update command line option description.
+
+2014-05-22  Alan Modra  <amodra@gmail.com>
+
+       * listing.c (listing_warning, listing_error): Add space after colon.
+       * messages.c (as_warn_internal, as_bad_internal): Use the same
+       string as above.
+
+2014-05-20  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+       * config/tc-mips.c (file_mips_opts_checked): New static global.
+       (s_module): New static function.
+       (file_ase): Remove.
+       (mips_pseudo_table): Add .module handler.
+       (mips_set_ase): Add opts argument and use instead of mips_opts.
+       (md_assemble): Use file_mips_check_options.
+       (md_parse_option): Update to use file_mips_opts instead of mips_opts.
+       (mips_set_architecture): Delete function.  Moved to...
+       (mips_after_parse_args): Here.  All logic now applies to
+       file_mips_opts first and then copies the final state to mips_opts.
+       Move error checking and defaults inference to mips_check_options and
+       file_mips_check_options.
+       (mips_check_options): New static function.  Common option checking for
+       command line, .module and .set.  Use .module values in error messages
+       instead of refering to command line options.
+       (file_mips_check_options): New static function.  A wrapper for
+       mips_check_options with file_mips_opts.  Updates BFD arch based on
+       final options.
+       (s_mipsset): Split into s_mipsset and parse_code_option.  Settings
+       supported by both .set and .module are moved to parse_code_option.
+       Warnings and errors are kept in s_mipsset because when
+       parse_code_option is used with s_module the warnings are deferred
+       until code is generated.  Any setting supporting 'default' value is
+       kept in s_mipsset as it is not applicable to s_module. Inferred
+       settings are also kept in s_mipsset as s_module does not infer any
+       settings.  Use mips_check_options.
+       (parse_code_option): New static function derived from s_mipsset.
+       (s_module): New static function that implements .module.  Allows file
+       level settings to be changed until code is generated.
+       (s_cpload, s_cpsetup, s_cplocal): Use file_mips_check_options.
+       (s_cprestore, s_cpreturn, s_cpadd, mips_address_bytes): Likewise.
+       (mips_elf_final_processing): Update file_ase to file_mips_opts.ase.
+       (md_mips_end): Use file_mips_check_options.
+       * doc/c-mips.texi: Document .module.
+
+2014-05-20  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+       * messages.c (as_warn_internal): Remove extra whitespace from
+       warning messages.
+
+2014-05-20  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+       * config/tc-mips.c (FP64_ASES): Add ASE_MSA.
+       (mips_after_parse_args): Do not select ASE_MSA without -mfp64.
+
+2014-05-20  Mike Stump  <mikestump@comcast.net>
+
+       * messages.c (as_warn_internal): Ensure we don't interleave output
+       within a single line when make -j is used.
+       (as_bad_internal): Likewise.
+
+2014-05-20  Richard Sandiford  <rdsandiford@googlemail.com>
+
+       * config/obj-elf.h (obj_elf_seen_attribute): Declare.
+       * config/obj-elf.c (recorded_attribute_info): New structure.
+       (recorded_attributes): New variable.
+       (record_attribute, obj_elf_seen_attribute): New functions.
+       (obj_elf_vendor_attribute): Record which attributes have been seen.
+
+2014-05-20  Nick Clifton  <nickc@redhat.com>
+
+       * config/tc-msp430.c (CHECK_RELOC_MSP430): Add OP parameter.
+       Generate BFD_RELOC_MSP430_ABS_HI16 if vshift is 1.
+       (msp430_srcoperand): Store vshift value in operand.
+
+2014-05-19  Nick Clifton  <nickc@redhat.com>
+
+       PR gas/16858
+       * config/tc-i386.c (md_apply_fix): Improve the detection of code
+       symbols for 32-bit PE targets.
+
+2014-05-18  Richard Sandiford  <rdsandiford@googlemail.com>
+
+       * config/tc-mips.c (md_obj_begin): Delete.
+       (md_obj_end): Fold into...
+       (md_mips_end): ...here.  Move to end of file.
+
+2014-05-17  Nick Clifton  <nickc@redhat.com>
+
+       PR gas/16946
+       * config/tc-v850.c (handle_ctoff): Generate an error if called
+       when using the RH850 ABI.
+
+2014-05-16  Kaushik Phata  <Kaushik.Phatak@kpit.com>
+
+       * config/tc-rl78.c (enum options): Add OPTION_32BIT_DOUBLES
+       and OPTION_64BIT_DOUBLES.
+       (md_longopts): Add -m32bit-doubles and -m64bit-doubles.
+       (md_parse_option): Parse -m32bit-doubles and -m64bit-doubles.
+       (md_show_usage): Show all of the RL78 options.
+       (rl78_float_cons): New static functions.
+       (md_pseudo_table): Update handler for "double".
+       * doc/c-rl78.texi: Document new options.
+       * doc/as.texinfo: Likewise.
+
+2014-05-13  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+       * config/tc-mips.c (mips_set_options): Rename gp32 to gp throughout.
+       (HAVE_32BIT_GPRS, HAVE_64BIT_GPRS): Remove. Re-implement via GPR_SIZE.
+       (HAVE_32BIT_FPRS, HAVE_64BIT_FPRS): Remove. Re-implement via FPR_SIZE.
+       (GPR_SIZE, FPR_SIZE): New macros. Use throughout.
+
+2014-05-08  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+       * config/tc-mips.c (md_parse_option): Update missed file_mips_isa
+       references.
+
+2014-05-08  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+       * config/tc-mips.c (mips_set_options): Rename fp32 field to fp.
+       Update fp32 == 0 to fp == 64 and fp32 == 1 to fp != 64 throughout.
+       (file_mips_gp32, file_mips_fp32, file_mips_soft_float,
+       file_mips_single_float, file_mips_isa, file_mips_arch): Merge into
+       one struct...
+       (file_mips_opts): Here. New static global. Update throughout.
+       (mips_opts): Update defaults for gp32 and fp.
+
+2014-05-08  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+       * config/tc-mips.c (streq): Define.
+       (mips_convert_symbolic_attribute): New function.
+       * config/tc-mips.h (CONVERT_SYMBOLIC_ATTRIBUTE): Define.
+       (mips_convert_symbolic_attribute): New prototype.
+
+2014-05-02  Max Filippov  <jcmvbkbc@gmail.com>
+
+       * config/tc-xtensa.c (md_apply_fix): mark BFD_RELOC_XTENSA_DIFF*
+       fixups as signed.
+
+2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
+
+       * tc-mips.c (ISA_SUPPORTS_MIPS16E): Add mips32r3, mips32r5, mips64r3
+       and mips64r5.
+       (ISA_HAS_64BIT_FPRS): Likewise.
+       (ISA_HAS_ROR): Likewise.
+       (ISA_HAS_ODD_SINGLE_FPR): Likewise.
+       (ISA_HAS_MXHC1): Likewise.
+       (hilo_interlocks): Likewise.
+       (md_longopts): Likewise.
+       (ISA_HAS_64BIT_REGS): Add mips64r3 and mips64r5.
+       (ISA_HAS_DROR): Likewise.
+       (options): Add OPTION_MIPS32R3, OPTION_MIPS32R5, OPTION_MIPS64R3, and
+       OPTION_MIPS64R5.
+       (mips_isa_rev): Add support for mips32r3, mips32r5, mips64r3 and
+       mips64r5.
+       (md_parse_option): Likewise.
+       (s_mipsset): Likewise.
+       (mips_cpu_info_table): Add entries for mips32r3, mips32r5, mips64r3
+       and mips64r5.  Also change p5600 entry to be mips32r5.
+       * configure.in: Add support for mips32r3, mips32r5, mips64r3 and
+       mips64r5.
+       * configure: Regenerate.
+       * doc/c-mips.texi: Document the -mips32r3, -mips32r5, -mips64r3 and
+       -mips64r5 command line options.
+       * doc/as.texinfo: Likewise.
+
+2014-04-28  Nick Clifton  <nickc@redhat.com>
+
+       PR gas/16858
+       * config/tc-i386.c (md_apply_fix): Do not adjust value of
+       pc-relative fixes against weak symbols.
+
+2014-04-26  Alan Modra  <amodra@gmail.com>
+
+       * po/POTFILES.in: Regenerate.
+
+2014-04-24  Nick Clifton  <nickc@redhat.com>
+
+       * config/tc-arm.c (s_ltorg): Only create a mapping symbol for ELF
+       based targets.
+
+2014-04-23  Will Newton  <will.newton@linaro.org>
+
+       * config/tc-arm.c (s_ltorg): Call make_mapping_symbol
+       directly instead of mapping_state.
+
+2014-04-23  Andrew Bennett  <andrew.bennett@imgtec.com>
+
+       * config/tc-mips.c (options): Add OPTION_XPA and OPTION_NO_XPA.
+       (md_longopts): Add xpa and no-xpa command line options.
+       (mips_ases): Add MIPS XPA ASE.
+       (mips_cpu_info_table): Update p5600 entry to allow the XPA ASE.
+       * doc/as.texinfo: Document the MIPS XPA command line options.
+       * doc/c-mips.texi: Document the MIPS XPA command line options,
+       and assembler directives.
+
+2014-04-22  Sandra Loosemore  <sandra@codesourcery.com>
+
+       * config/tc-nios2.c (nios2_consume_arg): Add case for 'E' to
+       unbreak self-test mode.
+
+2014-04-22  Max Filippov  <jcmvbkbc@gmail.com>
+
+       * config/tc-xtensa.c (xtensa_handle_align): record alignment for the
+       first section frag.
+
+2014-04-22  Christian Svensson  <blue@cmd.nu>
+
+       * Makefile.am: Remove openrisc and or32 support.  Add support for or1k.
+       * configure.in: Likewise.
+       * configure.tgt: Likewise.
+       * doc/as.texinfo: Likewise.
+       * config/obj-coff.h: Likewise.
+       * config/tc-or1k.c: New file.
+       * config/tc-or1k.h: New file.
+       * config/tc-openrisc.c: Delete.
+       * config/tc-openrisc.h: Delete.
+       * config/tc-or32.c: Delete.
+       * config/tc-or32.h: Delete.
+       * Makefile.in: Regenerate.
+       * configure: Regenerate.
+
+2014-04-16  Alan Modra  <amodra@gmail.com>
+
+       * config/tc-tilegx.h (TC_CONS_FIX_NEW): Add RELOC arg.
+       * config/tc-tilepro.h (TC_CONS_FIX_NEW): Likewise.
+
+2014-04-10  Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
+
+       * config/tc-avr.c: Add new flag mlink-relax.
+       (md_show_usage): Add flag and help text.
+       (md_parse_option): Record whether link relax is turned on.
+       (relaxable_section): New.
+       (avr_validate_fix_sub): New.
+       (avr_force_relocation): New.
+       (md_apply_fix): Generate DIFF reloc.
+       (avr_allow_local_subtract): New.
+
+       * config/tc-avr.h (TC_LINKRELAX_FIXUP): Define to 0.
+       (TC_FORCE_RELOCATION): Define.
+       (TC_FORCE_RELOCATION_SUB_SAME): Define.
+       (TC_VALIDATE_FIX_SUB): Define.
+       (avr_force_relocation): Declare.
+       (avr_validate_fix_sub): Declare.
+       (md_allow_local_subtract): Define.
+       (avr_allow_local_subtract): Declare.
+
+2014-04-10  Andrew Bennett  <andrew.bennett@imgtec.com>
+
+       * config/tc-mips.c (mips_cpu_info_table): Add P5600
+       configuation.
+       * doc/c-mips.texi: Document p5600.
+
+2014-04-09  Nick Clifton  <nickc@redhat.com>
+
+       * config/tc-rl78.h (TC_CONS_FIX_NEW): Add RELOC parameter.
+       * config/tc-z80.h (TC_CONS_FIX_NEW): Discard RELOC parameter.
+       * config/tc-aarch64.h (TC_CONS_FIX_NEW): Discard RELOC parameter.
+       * read.c (emit_expr_fix): Mark the r parameter as potentially
+       unused.
+
+2014-04-09  Alan Modra  <amodra@gmail.com>
+
+       * config/tc-ppc.c (warn_476, last_insn, last_seg, last_subseg):
+       New static vars.
+       (md_longopts, md_parse_option, md_show_usage): Add --ppc476-workaround.
+       (ppc_elf_cons_fix_check): New function.
+       (md_assemble): Set last_insn, last_seg, last_subseg.
+       (ppc_byte, md_apply_fix): Handle warn_476.
+       * config/tc-ppc.h (TC_CONS_FIX_CHECK): Define.
+       (ppc_elf_cons_fix_check): Declare.
+       * read.c (cons_worker): Invoke TC_CONS_FIX_CHECK.
+
+2014-04-09  Alan Modra  <amodra@gmail.com>
+
+       * gas/config/tc-alpha.h (TC_CONS_FIX_NEW): Add RELOC parameter.
+       * gas/config/tc-arc.c (arc_cons_fix_new): Add reloc parameter.
+       * gas/config/tc-arc.h (arc_cons_fix_new): Update prototype.
+       (TC_CONS_FIX_NEW): Add RELOC parameter.
+       * gas/config/tc-arm.c (cons_fix_new_arm): Similarly
+       * gas/config/tc-arm.h (cons_fix_new_arm, TC_CONS_FIX_NEW): Similarly.
+       * gas/config/tc-cr16.c (cr16_cons_fix_new): Similarly.
+       * gas/config/tc-cr16.h (cr16_cons_fix_new, TC_CONS_FIX_NEW): Similarly.
+       * gas/config/tc-crx.h (TC_CONS_FIX_NEW): Similarly.
+       * gas/config/tc-m32c.c (m32c_cons_fix_new): Similarly.
+       * gas/config/tc-m32c.h (m32c_cons_fix_new, TC_CONS_FIX_NEW): Similarly.
+       * gas/config/tc-mn10300.c (mn10300_cons_fix_new): Similarly.
+       * gas/config/tc-mn10300.h (mn10300_cons_fix_new, TC_CONS_FIX_NEW):
+       Similarly.
+       * gas/config/tc-ns32k.c (cons_fix_new_ns32k): Similarly.
+       * gas/config/tc-ns32k.h (cons_fix_new_ns32k): Similarly.
+       * gas/config/tc-pj.c (pj_cons_fix_new_pj): Similarly.
+       * gas/config/tc-pj.h (pj_cons_fix_new_pj, TC_CONS_FIX_NEW): Similarly.
+       * gas/config/tc-rx.c (rx_cons_fix_new): Similarly.
+       * gas/config/tc-rx.h (rx_cons_fix_new, TC_CONS_FIX_NEW): Similarly.
+       * gas/config/tc-sh.c (sh_cons_fix_new): Similarly.
+       * gas/config/tc-sh.h (sh_cons_fix_new, TC_CONS_FIX_NEW): Similarly.
+       * gas/config/tc-tic54x.c (tic54x_cons_fix_new): Similarly.
+       * gas/config/tc-tic54x.h (tic54x_cons_fix_new, TC_CONS_FIX_NEW):
+       Similarly.
+       * gas/config/tc-tic6x.c (tic6x_cons_fix_new): Similarly.
+       * gas/config/tc-tic6x.h (tic6x_cons_fix_new, TC_CONS_FIX_NEW):
+       Similarly.
+       * gas/config/tc-arc.c (arc_parse_cons_expression): Return reloc.
+       * gas/config/tc-arc.h (arc_parse_cons_expression): Update proto.
+       * gas/config/tc-avr.c (exp_mod_data): Make global.
+       (pexp_mod_data): Delete.
+       (avr_parse_cons_expression): Return exp_mod_data pointer.
+       (avr_cons_fix_new): Add exp_mod_data_t pointer param.
+       (exp_mod_data_t): Move typedef..
+       * gas/config/tc-avr.h: ..to here.
+       (exp_mod_data): Declare.
+       (TC_PARSE_CONS_RETURN_TYPE, TC_PARSE_CONS_RETURN_NONE): Define.
+       (avr_parse_cons_expression, avr_cons_fix_new): Update prototype.
+       (TC_CONS_FIX_NEW): Update.
+       * gas/config/tc-hppa.c (hppa_field_selector): Delete static var.
+       (cons_fix_new_hppa): Add hppa_field_selector param.
+       (fix_new_hppa): Adjust.
+       (parse_cons_expression_hppa): Return field selector.
+       * gas/config/tc-hppa.h (parse_cons_expression_hppa): Update proto.
+       (cons_fix_new_hppa): Likewise.
+       (TC_PARSE_CONS_RETURN_TYPE, TC_PARSE_CONS_RETURN_NONE): Define.
+       * gas/config/tc-i386.c (got_reloc): Delete static var.
+       (x86_cons_fix_new): Add reloc param.
+       (x86_cons): Return got reloc.
+       * gas/config/tc-i386.h (x86_cons, x86_cons_fix_new): Update proto.
+       (TC_CONS_FIX_NEW): Add RELOC param.
+       * gas/config/tc-ia64.c (ia64_cons_fix_new): Add reloc param.  Adjust
+       calls.
+       * gas/config/tc-ia64.h (ia64_cons_fix_new): Update prototype.
+       (TC_CONS_FIX_NEW): Add reloc param.
+       * gas/config/tc-microblaze.c (parse_cons_expression_microblaze):
+       Return reloc.
+       (cons_fix_new_microblaze): Add reloc param.
+       * gas/config/tc-microblaze.h: Formatting.
+       (parse_cons_expression_microblaze): Update proto.
+       (cons_fix_new_microblaze): Likewise.
+       * gas/config/tc-nios2.c (nios2_tls_ldo_reloc): Delete static var.
+       (nios2_cons): Return ldo reloc.
+       (nios2_cons_fix_new): Delete.
+       * gas/config/tc-nios2.h (nios2_cons): Update prototype.
+       (nios2_cons_fix_new, TC_CONS_FIX_NEW): Delete.
+       * gas/config/tc-ppc.c (md_pseudo_table): Remove quad, long, word,
+       short.  Make llong use cons.
+       (ppc_elf_suffix): Return BFD_RELOC_NONE rather than BFD_RELOC_UNUSED.
+       (ppc_elf_cons): Delete.
+       (ppc_elf_parse_cons): New function.
+       (ppc_elf_validate_fix): Don't check for BFD_RELOC_UNUSED.
+       (md_assemble): Use BFD_RELOC_NONE rather than BFD_RELOC_UNUSED.
+       * gas/config/tc-ppc.h (TC_PARSE_CONS_EXPRESSION): Define
+       (ppc_elf_parse_cons): Declare.
+       * gas/config/tc-sparc.c (sparc_cons_special_reloc): Delete static var.
+       (sparc_cons): Return reloc specifier.
+       (cons_fix_new_sparc): Add reloc specifier param.
+       (sparc_cfi_emit_pcrel_expr): Use emit_expr_with_reloc.
+       * gas/config/tc-sparc.h (TC_PARSE_CONS_RETURN_TYPE): Define.
+       (TC_PARSE_CONS_RETURN_NONE): Define.
+       (sparc_cons, cons_fix_new_sparc): Update prototype.
+       * gas/config/tc-v850.c (hold_cons_reloc): Delete static var.
+       (v850_reloc_prefix): Use BFD_RELOC_NONE rather than BFD_RELOC_UNUSED.
+       (md_assemble): Likewise.
+       (parse_cons_expression_v850): Return reloc.
+       (cons_fix_new_v850): Add reloc parameter.
+       * gas/config/tc-v850.h (parse_cons_expression_v850): Update proto.
+       (cons_fix_new_v850): Likewise.
+       * gas/config/tc-vax.c (vax_cons_special_reloc): Delete static var.
+       (vax_cons): Return reloc.
+       (vax_cons_fix_new): Add reloc parameter.
+       * gas/config/tc-vax.h (vax_cons, vax_cons_fix_new): Update proto.
+       * gas/config/tc-xstormy16.c (xstormy16_cons_fix_new): Add reloc param.
+       * gas/config/tc-xstormy16.h (xstormy16_cons_fix_new): Update proto.
+       * gas/dwarf2dbg.c (TC_PARSE_CONS_RETURN_NONE): Provide default.
+       (emit_fixed_inc_line_addr): Adjust exmit_expr_fix calls.
+       * gas/read.c (TC_PARSE_CONS_EXPRESSION): Return value.
+       (do_parse_cons_expression): Adjust.
+       (cons_worker): Pass return value from TC_PARSE_CONS_EXPRESSION
+       to emit_expr_with_reloc.
+       (emit_expr_with_reloc): New function handling reloc, mostly
+       extracted from..
+       (emit_expr): ..here.
+       (emit_expr_fix): Add reloc param.  Adjust TC_CONS_FIX_NEW invocation.
+       Handle reloc.
+       (parse_mri_cons): Convert to ISO.
+       * gas/read.h (TC_PARSE_CONS_RETURN_TYPE): Define.
+       (TC_PARSE_CONS_RETURN_NONE): Define.
+       (emit_expr_with_reloc): Declare.
+       (emit_expr_fix): Update prototype.
+       * gas/write.c (write_object_file): Update TC_CONS_FIX_NEW invocation.
+
+2014-04-03  Ilya Tocar  <ilya.tocar@intel.com>
+
+       * config/tc-i386.c (cpu_arch): Add .se1.
+       * doc/c-i386.texi: Document .se1/se1.
+
+2014-04-02  DJ Delorie  <dj@redhat.com>
+
+       * config/tc-rl78.c (md_apply_fix): Add overflow warnings for
+       pc-relative branches.
+
+2014-04-02  Nick Clifton  <nickc@redhat.com>
+
+       PR gas/16765
+       * config/tc-arm.c (create_unwind_entry): Report an error if an
+       attempt to recreate an unwind directive is encountered.
+
+2014-03-27  Nick Clifton  <nickc@redhat.com>
+
+       * config/tc-score.c (s3_parse_pce_inst): Add "%s" parameter to
+       sprintf in order to avoid a compile time warning.
+
+2014-03-26  Nick Clifton  <nickc@redhat.com>
+
+       * config/tc-rl78.c (rl78_op): Issue an error message if a 16-bit
+       relocation is used on an 8-bit operand or vice versa.
+       (tc_gen_reloc): Use the RL78_16U relocation for RL78_CODE.
+       (md_apply_fix): Add support for RL78_HI8, RL78_HI16 and RL78_LO16.
+
+2014-03-25  Nick Clifton  <nickc@redhat.com>
+
+       * config/obj-coff-seh.c (obj_coff_seh_code): New function -
+       switches the current segment back to the code segment recorded
+       when seh_proc was last invoked.
+       * config/obj-coff-seh.h (SEH_CMDS): Add seh_code.
+
+2014-03-25  Alan Modra  <amodra@gmail.com>
+
+       * config/tc-ppc.c (ppc_is_toc_sym): Revert 2014-03-05.
+       (md_assemble): Likewise.  Warn.
+
+2014-03-21  David Weatherford <weath@cadence.com>
+            Max Filippov <jcmvbkbc@gmail.com>
+
+       * config/tc-xtensa.c (xtensa_check_frag_count)
+       xtensa_create_trampoline_frag,
+       xtensa_maybe_create_trampoline_frag, init_trampoline_frag,
+       find_trampoline_seg, search_trampolines, get_best_trampoline,
+       check_and_update_trampolines, add_jump_to_trampoline,
+       dump_trampolines): New functions.
+       (md_parse_option): Add cases for --[no-]trampolines options.
+       (md_assemble, finish_vinsn, xtensa_end): Add call to
+       xtensa_check_frag_count.
+       (xg_assemble_vliw_tokens): Add call to
+       xtensa_maybe_create_trampoline_frag.
+       (xtensa_relax_frag): Relax fragments with RELAX_TRAMPOLINE state.
+       (relax_frag_immed): Relax jump instructions that cannot reach its
+       target.
+       * config/tc-xtensa.h (xtensa_relax_statesE::RELAX_TRAMPOLINE): New
+       relax state.
+       * doc/as.texinfo: Document --[no-]trampolines command-line options.
+       * doc/c-xtensa.texi: Document trampolines relaxation and command
+       line options.
+       * frags.c (get_frag_count, clear_frag_count): New function.
+       (frag_alloc): Increment totalfrags counter.
+       * frags.h (get_frag_count, clear_frag_count): New function.
+
+2014-03-20  DJ Delorie  <dj@redhat.com>
+
+       * config/rl78-defs.h (RL78_RELAX_NONE, RL78_RELAX_BRANCH): Add.
+       * config/rl78-parse.y (BC, BNC, BZ, BNZ, BH, BHZ, bt_bf): Call
+       rl78_relax().
+       * config/tc-rl78.h (md_relax_frag): Define.
+       (rl78_relax_frag): Declare.
+       * config/tc-rl78.c (rl78_relax): Add.
+       (md_assemble): Set up the variable frags also when relaxing.
+       (op_type_T): New.
+       (rl78_opcode_type): New.
+       (rl78_frag_fix_value): New.
+       (md_estimate_size_before_relax): New-ish.
+       (rl78_relax_frag): New.
+       (md_convert_frag): New-ish.
+
+2014-03-20  Richard Sandiford  <rdsandiford@googlemail.com>
+
+       * config/tc-mips.h (DIFF_EXPR_OK, CFI_DIFF_EXPR_OK): Define.
+       * config/tc-mips.c (md_pcrel_from): Remove error message.
+       (md_apply_fix): Convert PC-relative BFD_RELOC_32s to
+       BFD_RELOC_32_PCREL.  Report a specific error message for unhandled
+       PC-relative expressions.  Handle BFD_RELOC_8.
+
+2014-03-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * config/tc-sparc.c (hpriv_reg_table): Added entries for
+       %hstick_offset and %hstick_enable.
+       * doc/c-sparc.texi (Sparc-Regs): Document the %hstick_offset and
+       %hstick_enable hyperprivileged registers.
+
+2014-03-19  Daniel Gutson <daniel.gutson@tallertechnologies.com>
+           Nick Clifton  <nickc@redhat.com>
+
+       * config/tc-arm.c (codecomposer_syntax): New flag that states whether the
+       CCS syntax compatibility mode is on or off.
+       (asmfunc_states): New enum to represent the asmfunc directive state.
+       (asmfunc_state): New variable holding the asmfunc directive state.
+       (comment_chars): Rename to arm_comment_chars.
+       (line_separator_chars): Rename to arm_line_separator_chars.
+       (s_ccs_ref): New function that handles the .ref directive.
+       (asmfunc_debug): New function.
+       (s_ccs_asmfunc): New function that handles the .asmfunc directive.
+       (s_ccs_endasmfunc): New function that handles the .endasmfunc directive.
+       (s_ccs_def): New function that handles the .def directive.
+       (tc_start_label_without_colon): New function.
+       (md_pseudo_table): Added new CCS directives.
+       (arm_ccs_mode): New function that handles the -mccs command line option.
+       (arm_long_opts): Added new -mccs command line option.
+       * config/tc-arm.h (LABELS_WITHOUT_COLONS): New macro.
+       (TC_START_LABEL_WITHOUT_COLON): New macro.
+       (tc_start_label_without_colon): Added extern function declaration.
+       (tc_comment_chars): Define.
+       (tc_line_separator_chars): Define.
+       * app.c (do_scrub_begin): Use tc_line_separator_chars, if defined.
+       * read.c (read_begin): Likewise.
+       * doc/as.texinfo: Add documentation for the -mccs command line
+       option.
+       * doc/c-arm.texi: Likewise.
+       * doc/internals.texi: Document tc_line_separator_chars.
+       * NEWS: Mention the new feature.
+
+2014-03-18  Jiong Wang  <jiong.wang@arm.com>
+
+       * config/tc-aarch64.c (aarch64_opts): Add new option
+       "mno-verbose-error".
+       (verbose_error_p): Initialize to 1.
+       * doc/c-aarch64.texi (AArch64 Options): Document -mverbose-error
+       and -mno-verbose-error.
+
+2014-03-17  Nick Clifton  <nickc@redhat.com>
+
+       PR gas/16694
+       * config/tc-arm.c (tc_arm_regname_to_dw2regnum): Parse VFP
+       registers as well.
+
+2014-03-13  Richard Earnshaw  <rearnsha@arm.com>
+           Jiong Wang  <Jiong.Wang@arm.com>
+
+       * doc/c-aarch64.texi: Clean up some formatting issues.
+       (AArch64 Options): Document -mcpu and -march.
+       (AArch64 Extensions): New node.
+
+2014-03-13  Tristan Gingold  <gingold@adacore.com>
+
+       * config/tc-i386.c (use_big_obj): Declare.
+       (OPTION_MBIG_OBJ): Define.
+       (md_longopts): Add -mbig-obj option.
+       (md_parse_option): Handle it.
+       (md_show_usage): Display help for this option.
+       (i386_target_format): Use bigobj for x86-64 if -mbig-obj.
+       * doc/c-i386.texi: Document the option.
+
+2014-03-12  Nick Clifton  <nickc@redhat.com>
+
+       PR gas/16688
+       * config/tc-aarch64.c (literal_expression): New structure.
+       (literal_pool): Replace exp array with literal_expression array.
+       (add_to_lit_pool): When adding a bignum cache the big value.
+       (s_ltorg): When emitting a bignum initialise the global bignum
+       array from the cached value.
+
+2014-03-12  Alan Modra  <amodra@gmail.com>
+
+       * Makefile.in: Regenerate.
+       * config.in: Regenerate.
+       * doc/Makefile.in: Regenerate.
+
+2014-03-06  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
+       Vishnu KS <Vishnu.k_s@atmel.com>
+       Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
+       Soundararajan <Soundararajan.dhakshinamoorthy@atmel.com>
+
+       * gas/tc-avr.c: Add new devices
+       avr25: ata5272, attiny828
+       avr35: ata5505, attiny1634
+       avr4: atmega8a, ata6285, ata6286, atmega48pa
+       avr5: at90pwm161, ata5790, ata5795, atmega164pa, atmega165pa,
+       atmega168pa, atmega32a, atmega64rfr2, atmega644rfr2, atmega64a,
+       atmega16hva2
+       avr51: atmega128a, atmega1284
+       avrxmega2: atxmega16a4u, atxmega16c4, atxmega32a4u, atxmega32c4,
+       atxmega32e5, atxmega16e5, atxmega8e5
+       avrxmega4: atxmega64a3u, atxmega64a4u, atxmega64b1, atxmega64b3,
+       atxmega64c3, atxmega64d4
+       avrxmega6: atxmega128a3u, atxmega128b3, atxmega128c3,
+       atxmega128d4, atxmega192a3u, atxmega192c3, atxmega256a3u,
+       atxmega256c3, atxmega384c3, atxmega384d3
+       avrxmega7: atxmega128a4u
+       * doc/c-avr.texi: Ditto.
+
+2014-03-05  Alan Modra  <amodra@gmail.com>
+
+       Update copyright years.
+
+2014-03-05  Alan Modra  <amodra@gmail.com>
+
+       * config/tc-ppc.c (ppc_elf_suffix): Support @localentry.
+       (md_apply_fix): Support R_PPC64_ADDR64_LOCAL.
+
+2014-03-05  Alan Modra  <amodra@gmail.com>
+
+       * config/tc-ppc.c (md_assemble): Move code adjusting reloc types
+       later.  Merge absolute and relative branch reloc selection.
+       Generate 16-bit relocs for most 16-bit insn fields given a
+       non-constant expression.
+
+2014-03-05  Alan Modra  <amodra@gmail.com>
+
+       * config/tc-ppc.c (ppc_is_toc_sym): Remove OBJ_ELF support.
+       (md_assemble): Don't call ppc_is_toc_sym for ELF.
+
+2014-03-04  Heiher  <r@hev.cc>
+
+       * config/tc-mips.c (mips_cpu_info_table): Use ISA_MIPS64R2 for
+       Loongson-3A.
+
+2014-03-03  Nick Clifton  <nickc@redhat.com>
+
+       * config/msp430/msp430.c: Replace known mcu array with known
+       msp430 ISA mcu name array.
+       Accept any name for -mmcu option.
+       Add -mz option to warn about missing NOP following an interrupt
+       status change.
+       (check_for_nop): New.
+       (msp430_operands): Emit a warning, if requested, when an interrupt
+       changing instruction is not followed by a NOP.
+       * doc/c-msp430.c: Document -mz option.
+
+2014-03-03  Alan Modra  <amodra@gmail.com>
+
+       * config/bfin-lex-wrapper.c: Correct copyright date.
+       * config/obj-fdpicelf.c: Likewise.
+       * config/obj-fdpicelf.h: Likewise.
+       * config/tc-frv.c: Correct copyright punctuation.
+       * config/tc-ip2k.c: Likewise.
+       * config/tc-iq2000.c: Likewise.
+       * config/tc-mep.c: Likewise.
+       * config/tc-tic4x.c: Likewise.
+       * config/tc-tic4x.h: Likewise.
+
+2014-03-01  Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
+
+       * config/tc-avr.c: Remove atxmega16x1.
+
+2014-02-28  Alan Modra  <amodra@gmail.com>
+
+       * dwarf2dbg.c (out_debug_line): Correct .debug_line header_length
+       field for 64-bit dwarf.
+
+2014-02-21  Ilya Tocar  <ilya.tocar@intel.com>
+
+       * config/tc-i386.c (cpu_arch): Add .prefetchwt1.
+       * doc/c-i386.texi: Document .prefetchwt1/prefetchwt1.
+
+2014-02-12  Ilya Tocar  <ilya.tocar@intel.com>
+
+       * config/tc-i386.c (cpu_arch): Add .clflushopt, .xsavec, .xsaves.
+       * doc/c-i386.texi: Document .xsavec/xsavec/.xsaves/xsaves/
+       clflushopt/.clfushopt.
+
+2014-02-10  Alan Modra  <amodra@gmail.com>
+
+       * po/POTFILES.in: Regenerate.
+       * po/gas.pot: Regenerate.
+
+2014-02-03  Sandra Loosemore  <sandra@codesourcery.com>
+
+       * config/tc-nios2.c (md_apply_fix): Test for new relocs.
+       (nios2_special_reloc): Add %call_lo, %call_hiadj, %got_lo,
+       %got_hiadj relocation operators.  Sort table and add comment
+       to explain ordering.
+       (nios2_fix_adjustable): Test for new relocs.
+       * doc/c-nios2.texi (Nios II Relocations): Document new relocation
+       operators.
+
+2014-01-30  Sandra Loosemore  <sandra@codesourcery.com>
+
+       * config/tc-nios2.c (md_apply_fix): Handle BFD_RELOC_NIOS2_CALL26_NOAT.
+       (nios2_assemble_args_m): Likewise.
+       (md_assemble): Likewise.
+
+2014-01-24  DJ Delorie  <dj@redhat.com>
+
+       * config/tc-msp430.c (msp430_section): Always flag data sections,
+       regardless of -md.
+       (msp430_frob_section): New.  Make sure all sections are noticed if
+       they have content.
+       (msp430_lcomm): New.  Flag bss if .lcomm is seen.
+       (msp430_comm): New.  Likewise.
+       (md_pseudo_table): Add them.
+       * config/tc-msp430.h (msp430_frob_section): Declare.
+       (tc_frob_section): Define.
+
+2014-01-23  Nick Clifton  <nickc@redhat.com>
+
+       * config/tc-msp430.c (show_mcu_list): Delete.
+       (md_parse_option): Accept any MCU name.  Accept several more
+       variants for the -mcpu option.
+       (md_show_usage): Do not call show_mcu_list.
+
+2014-01-22  DJ Delorie  <dj@redhat.com>
+
+       * config/tc-msp430.c (msp430_refsym): New: ".refsym <symbol>"
+       * doc/c-msp430.texi (MSP430 Directives): Document it.
+
+2014-01-22  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
+
+       * config/tc-i386.c (check_VecOperands): Remove regzmm from AVX2
+       gather assert.
+
+2014-01-22  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
+
+       PR gas/16489
+       * config/tc-i386.c (check_VecOperands): Add check for invalid
+       register set in AVX512 gathers.
+
+2014-01-22  Alan Modra  <amodra@gmail.com>
+
+       * config/tc-tic4x.c (md_shortopts): s/CONST/const/.
+
+2014-01-21  DJ Delorie  <dj@redhat.com>
+
+       * config/tc-rl78.c (require_end_of_expr): New.
+       (md_operand): Call it.
+       (rl78_cons_fix_new): Mark LO16, HI16, ahd HI8 internal relocations
+       as not overflowing.
+
+2014-01-17  Will Newton  <will.newton@linaro.org>
+
+       * config/tc-arm.c (do_vfp_nsyn_cvt_fpv8): Set OP to 1
+       for the s32.f64 flavours of VCVT.
+
+2014-01-14  Nick Clifton  <nickc@redhat.com>
+
+       PR gas/16434
+       * config/tc-z80.c (wrong_match): Provide format string to
+       as_warn.
+       (parse_exp_not_indexed): Delete unused variable dummy.
+       (emit_byte): Delete unused variable fixp.
+
+2014-01-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * config/tc-i386.c (regbnd): Removed.
+       (vec_disp8): Likewise.
+
+2014-01-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * as.c (parse_args): Update copyright year to 2014.
+
+2014-01-07  Tom Tromey  <tromey@redhat.com>
+
+       * config/tc-tic30.c (debug): Avoid old VA_* compatibility
+       wrappers.
+
+2014-01-07  Tom Tromey  <tromey@redhat.com>
+
+       * config/tc-microblaze.h (parse_cons_expression_microblaze): Don't
+       use PARAMS.
+
+2014-01-07  Tom Tromey  <tromey@redhat.com>
+
+       * config/tc-xc16x.h: Don't use ANSI_PROTOTYPES.
+
+2013-01-07  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
+
+       * config/tc-aarch64.c (aarch64_cpus): Add entry for "xgene-1"
+
+For older changes see ChangeLog-2013
 \f
 Copyright (C) 2014 Free Software Foundation, Inc.
 
diff --git a/gas/ChangeLog.linaro b/gas/ChangeLog.linaro
new file mode 100644 (file)
index 0000000..31754d9
--- /dev/null
@@ -0,0 +1,138 @@
+2016-10-20  Adhemerval Zanella  <adhemerval.zanella@linaro.org>
+
+       Backport from 2.25.
+
+       2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * config/tc-arm.c (arm_ext_v8_2): New.
+       (insns): Add "esb".
+       * testsuite/gas/arm/armv8_2-a.d: New.
+       * testsuite/gas/arm/armv8_2-a.s: New.
+
+       2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * config/tc-aarch64.c (aarch64_hint_opt_hsh): New.
+       (parse_barrier_psb): New.
+       (parse_operands): Add case for AARCH64_OPND_BARRIER_PSB.
+       (md_begin): Set up aarch64_hint_opt_hsh.
+
+       2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * config/tc-aarch64.c (aarch64_features): Add "profile".
+       * doc/c-aarch64.texi (AArch64 Extensions): Add "profile".
+
+       2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * config/tc-aarch64.c (parse_sys_ins_reg): Add check of
+       architectural support for system register.
+
+       2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * doc/c-aarch64.texi (AArch64 Extensions): Update entry for crc.
+
+       2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * config/tc-aarch64.c (aarch64_features): Add "fp16".
+       * doc/c-aarch64.texi (Architecture Extensions): Add "fp16".
+
+       2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * config/tc-arm.c (arm_archs): Add "armv8.2-a".
+       * doc/c-arm.texi (-march): Add "armv8.2-a".
+
+       2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * config/tc-aarch64.c (aarch64_archs): Add "armv8.2-a".
+       * doc/c-aarch64.texi (-march): Likewise.
+
+       2015-07-16  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * config/tc-arm.c (arm_fpus): Add crypto-neon-fp-armv8.1.
+       * doc/c-arm.texi (-mfpu=): Likewise.  Correct the entry for
+       neon-fp-armv8.1.
+
+       2015-06-04  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * NEWS: Mention ARMv8.1 support in the Aarch64 port.
+       * config/tc-aarch64.c (aarch64_arch_option_table): Add "armv8.1-a".
+       * doc/c-aarch64.texi (-march): Add "armv8.1-a".
+
+       2015-06-03  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * config/tc-arm.c (arm_archs): Add "armv8.1-a".
+       * doc/c-arm.texi (ARM Options, -march): Add "armv8.1-a".
+       * NEWS: Mention ARMv8.1 support.
+
+       2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * config/tc-arm.c (arm_ext_pan): New.
+       (do_setpan): New, encode an ARM SETPAN instruction.
+       (do_t_setpan): New, encode a Thumb SETPAN instruction.
+       (insns): Add "setpan".
+       (arm_extensions): Add "pan".
+       * doc/c-arm.texi (ARM Options): Add "pan" to list of -mcpu processor
+       extensions.
+
+       2015-03-24  Terry Guo  <terry.guo@arm.com>
+
+       * config/tc-arm.c (no_cpu_selected): Use new macro to compare
+       features.
+       (parse_psr): Likewise.
+       (do_t_mrs): Likewise.
+       (do_t_msr): Likewise.
+       (static const arm_feature_set arm_ext_*): Defined with new macros.
+       (static const arm_feature_set arm_cext_*): Likewise.
+       (static const arm_feature_set fpu_fpa_ext_*): Likewise.
+       (static const arm_feature_set fpu_vfp_ext_*): Likewise.
+       (deprecated_coproc_regs): Likewise.
+       (UL_BARRIER): Likewise.
+       (barrier_opt_names): Likewise.
+       (arm_cpus): Likewise.
+       (arm_extensions): Likewise.
+
+       2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * config/tc-aarch64.c (aarch64_features): Add "rdma".
+       * doc/c-aarch64.texi (AArch64 Extensions): Add "rdma".
+
+       2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * config/tc-aarch64.c (aarch64_features): Add "lor".
+       * doc/c-aarch64.c (Aarch64 Extensions): Add "lor" to list of
+       architecture extensions.
+
+       2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * config/tc-aarch64.c (parse_sys_reg): New parameter.  Check target
+       support.  Fix whitespace.
+       (parse_operands): Update for parse_sys_reg changes.
+       (aarch64_features): Add "pan".
+       * doc/c-aarch64.texi (Aarch64 Extensions): Add "pan".
+
+       2015-02-03  Renlin Li  <renlin.li@arm.com>
+
+       * doc/c-aarch64.texi (.arch): Document the directive.
+       (.arch_extension): Likewise.
+
+       2014-11-18  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-aarch64.c (s_aarch64_arch_extension): New.
+       (md_pseudo_table): Add arch_extension.
+       (aarch64_parse_features): New parameter "ext_only". Handle it.
+       (aarch64_parse_cpu, aarch64_parse_arch, s_aarch64_cpu,
+       s_aarch64_arch): Pass FALSE as new third argument of
+       aarch64_parse_features().
+
+       2015-01-07  Jan Beulich <jbeulich@suse.com>
+
+       * config/tc-arm.c (struct arm_option_extension_value_table):
+       Split field "value" into fields "merge_value" and "clear_value".
+       (arm_extensions): Adjust initializer accordingly.
+
+       2015-06-17  Nicolas Pitre <nico@linaro.org>
+
+       * as.c (show_usage): Document --sectname-subst.
+       (parse_args): Add --sectname-subst.
+       * as.h (flag_sectname_subst): New.
+       * config/obj-elf.c (obj_elf_section_name): Add %S substitution.
+       * doc/as.texinfo: Document it.
index 7fd7a63364c9bc0ea6301b8f11c03dc2a47c15d5..d53d5181e442214e340dd28b4160f83ae3caec19 100644 (file)
@@ -1,118 +1,3 @@
-2015-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
-
-       * gas/arm/armv8-a.d: <ldaexh>: Rename mismatched mnemonics ...
-       <ldah>: ... to this.
-
-2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * gas/aarch64/system-2.d: Enable the statistical profiling
-       extension.  Update the expected output.
-       * gas/aarch64/system-2.s: Add tests for PSB CSYNC.
-       * gas/aarch64/system.d: Update the expected output.
-
-2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * gas/aarch64/sysreg-2.s: Add tests for the statistical profiling
-       system registers.
-       * gas/aarch64/sysreg-2.d: Enable the statistical profiling
-       extension and update the expected output.
-
-2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * gas/aarch64/sysreg-2.d: Update for new tests for AT S1E1RP and
-       AT S1E1WP.
-       * gas/aarch64/sysreg-2.s: Add tests for AT S1E1RP and AT S1E1WP.
-
-2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * gas/aarch64/sysreg-2.d: Add tests for dc instruction.
-       * gas/aarch64/sysreg-2.s: Add uses of dc instruction.
-
-2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * gas/aarch64/uao-directive.d: New.
-       * gas/aarch64/uao.d: New.
-       * gas/aarch64/uao.s: New.
-
-2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * gas/aarch64/sysreg-2.d: Add tests for new registers.
-       * gas/aarch64/sysreg-2.s: Likewise.  Also replace some spaces with
-       tabs.
-
-2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * gas/aarch64/system-2.d: New.
-       * gas/aarch64/system-2.s: New.
-       * gas/aarch64/system.d: Adjust expected output for HINT 16.
-
-2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * gas/aarch64/float-fp16.d: New.
-       * gas/aarch64/float-fp16.s: New.
-
-2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * gas/aarch64/alias-2.d: Add tests for REV.
-       * gas/aarch64/alias-2.s: Likewise.
-
-2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * gas/aarch64/alias-2.d: New.
-       * gas/aarch64/alias-2.s: New.
-
-2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * gas/aarch64/sysreg-2.d: New.
-       * gas/aarch64/sysreg-2.s: New.
-
-2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * gas/aarch64/virthostext-directive.d: New.
-       * gas/aarch64/virthostext.d: New.
-       * gas/aarch64/virthostext.s: New.
-
-2015-06-03  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * gas/arm/armv8-a+rdma.d: New.
-       * gas/arm/armv8-a+rdma.s: New.
-
-2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * gas/arm/armv8-a+pan.d: New.
-       * gas/arm/armv8-a+pan.s: New.
-
-2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * gas/aarch64/rdma-directive.d: New.
-       * gas/aarch64/rdma.d: New.
-       * gas/aarch64/rdma.s: New.
-
-2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * gas/aarch64/lor-directive.d: New.
-       * gas/aarch64/lor.d: New.
-       * gas/aarch64/lor.s: New
-
-2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * gas/aarch64/pan-directive.d: New.
-       * gas/aarch64/pan.d: New.
-       * gas/aarch64/pan.s: New
-
-2014-11-18  Jan Beulich  <jbeulich@suse.com>
-
-       * gas/aarch64/crc32-directive.d: New.
-       * gas/aarch64/crypto-directive.d: New.
-       * gas/aarch64/crc32.s: Adjust to allow for directive use.
-       * gas/aarch64/crypto.s: Likewise.
-
-2015-03-10  Renlin Li  <renlin.li@arm.com>
-
-       * gas/aarch64/ldst-reg-uns-imm.d: Adjust expected output.
-       * gas/aarch64/ldst-reg-unscaled-imm.d: Likewise.
-       * gas/aarch64/reloc-insn.d: Likewise.2015-03-10  Matthew Wahab  <matthew.wahab@arm.com>
-
 2014-12-19  Matthew Fortune  <matthew.fortune@imgtec.com>
 
        * gas/mips/r6-64.s: Remove .align directives from LDPC
diff --git a/gas/testsuite/ChangeLog.linaro b/gas/testsuite/ChangeLog.linaro
new file mode 100644 (file)
index 0000000..da761c6
--- /dev/null
@@ -0,0 +1,118 @@
+2016-10-20  Adhemerval Zanella  <adhemerval.zanella@linaro.org>
+
+       Backport from 2.25
+
+       2015-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+       * gas/arm/armv8-a.d: <ldaexh>: Rename mismatched mnemonics ...
+       <ldah>: ... to this.
+
+       2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * gas/aarch64/system-2.d: Enable the statistical profiling
+       extension.  Update the expected output.
+       * gas/aarch64/system-2.s: Add tests for PSB CSYNC.
+       * gas/aarch64/system.d: Update the expected output.
+
+       2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * gas/aarch64/sysreg-2.s: Add tests for the statistical profiling
+       system registers.
+       * gas/aarch64/sysreg-2.d: Enable the statistical profiling
+       extension and update the expected output.
+
+       2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * gas/aarch64/sysreg-2.d: Update for new tests for AT S1E1RP and
+       AT S1E1WP.
+       * gas/aarch64/sysreg-2.s: Add tests for AT S1E1RP and AT S1E1WP.
+
+       2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * gas/aarch64/sysreg-2.d: Add tests for dc instruction.
+       * gas/aarch64/sysreg-2.s: Add uses of dc instruction.
+
+       2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * gas/aarch64/uao-directive.d: New.
+       * gas/aarch64/uao.d: New.
+       * gas/aarch64/uao.s: New.
+
+       2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * gas/aarch64/sysreg-2.d: Add tests for new registers.
+       * gas/aarch64/sysreg-2.s: Likewise.  Also replace some spaces with
+       tabs.
+
+       2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * gas/aarch64/system-2.d: New.
+       * gas/aarch64/system-2.s: New.
+       * gas/aarch64/system.d: Adjust expected output for HINT 16.
+
+       2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * gas/aarch64/float-fp16.d: New.
+       * gas/aarch64/float-fp16.s: New.
+
+       2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * gas/aarch64/alias-2.d: Add tests for REV.
+       * gas/aarch64/alias-2.s: Likewise.
+
+       2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * gas/aarch64/alias-2.d: New.
+       * gas/aarch64/alias-2.s: New.
+
+       2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * gas/aarch64/sysreg-2.d: New.
+       * gas/aarch64/sysreg-2.s: New.
+
+       2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * gas/aarch64/virthostext-directive.d: New.
+       * gas/aarch64/virthostext.d: New.
+       * gas/aarch64/virthostext.s: New.
+
+       2015-06-03  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * gas/arm/armv8-a+rdma.d: New.
+       * gas/arm/armv8-a+rdma.s: New.
+
+       2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * gas/arm/armv8-a+pan.d: New.
+       * gas/arm/armv8-a+pan.s: New.
+
+       2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * gas/aarch64/rdma-directive.d: New.
+       * gas/aarch64/rdma.d: New.
+       * gas/aarch64/rdma.s: New.
+
+       2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * gas/aarch64/lor-directive.d: New.
+       * gas/aarch64/lor.d: New.
+       * gas/aarch64/lor.s: New
+
+       2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * gas/aarch64/pan-directive.d: New.
+       * gas/aarch64/pan.d: New.
+       * gas/aarch64/pan.s: New
+
+       2014-11-18  Jan Beulich  <jbeulich@suse.com>
+
+       * gas/aarch64/crc32-directive.d: New.
+       * gas/aarch64/crypto-directive.d: New.
+       * gas/aarch64/crc32.s: Adjust to allow for directive use.
+       * gas/aarch64/crypto.s: Likewise.
+
+       2015-03-10  Renlin Li  <renlin.li@arm.com>
+
+       * gas/aarch64/ldst-reg-uns-imm.d: Adjust expected output.
+       * gas/aarch64/ldst-reg-unscaled-imm.d: Likewise.
+       * gas/aarch64/reloc-insn.d: Likewise.
index 4d94aa3f3e99a63b8fb291a4de15239497ac232a..d378910e4778dae7fc4ebb810a2bf90d041a9efc 100644 (file)
@@ -1,122 +1,3 @@
-2015-12-15  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * arm.h (ARM_ARCH_V8_1A): Add the CRC_EXT_ARMV8 co-processor
-       feature macro.
-       (ARM_ARCH_V8_2A): Likewise.
-
-2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB.
-       * aarch64-asm-2.c: Regenerate.
-       * aarch64-dis-2.c: Regenerate.
-       * aarch64-opc-2.c: Regenerate.
-       * aarch64-opc.c (aarch64_hint_options): Add "csync".
-       (aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB.
-       * aarch64-tbl.h (aarch64_feature_stat_profile): New.
-       (STAT_PROFILE): New.
-       (aarch64_opcode_table): Add "psb".
-       (AARCH64_OPERANDS): Add "BARRIER_PSB".
-
-2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64.h (aarch64_hint_options): Declare.
-       (aarch64_opnd_info): Add field hint_option.
-
-2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64.h (AARCH64_FEATURE_PROFILE): New.
-
-2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.
-
-2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
-       (aarch64_sys_ins_reg_has_xt): Declare.
-
-2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64.h (AARCH64_FEATURE_RAS): New.
-       (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.
-
-2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64.h (AARCH64_FEATURE_F16): Fix clash with
-       AARCH64_FEATURE_V8_1.
-       (AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
-       (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
-       AARCH64_FEATURE_V8_1.
-
-2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64.h (aarch64_op): Add OP_BFC.
-
-2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64.h (AARCH64_FEATURE_F16): New.
-       (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2
-       features.
-
-2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64.h (AARCH64_FEATURE_V8_1): New.
-       (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.
-
-2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * arm.h (ARM_EXT2_V8_2A): New.
-       (ARM_ARCH_V8_2A): New.
-
-2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64.h (AARCH64_FEATURE_V8_2): New.
-       (AARCH64_ARCH_V8_2): New.
-
-2015-06-04  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64.h (AARCH64_V8_1): New.
-
-2015-06-03  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
-       (ARM_ARCH_V8_1A): New.
-       (ARM_ARCH_V8_1A_FP): New.
-       (ARM_ARCH_V8_1A_SIMD): New.
-       (ARM_ARCH_V8_1A_CRYPTOV1): New.
-       (ARM_FEATURE_CORE): New.
-
-2015-03-24  Terry Guo  <terry.guo@arm.com>
-
-       * arm.h (arm_feature_set): Extended to provide more available bits.
-       (ARM_ANY): Updated to follow above new definition.
-       (ARM_CPU_HAS_FEATURE): Likewise.
-       (ARM_CPU_IS_ANY): Likewise.
-       (ARM_MERGE_FEATURE_SETS): Likewise.
-       (ARM_CLEAR_FEATURE): Likewise.
-       (ARM_FEATURE): Likewise.
-       (ARM_FEATURE_COPY): New macro.
-       (ARM_FEATURE_EQUAL): Likewise.
-       (ARM_FEATURE_ZERO): Likewise.
-       (ARM_FEATURE_CORE_EQUAL): Likewise.
-       (ARM_FEATURE_LOW): Likewise.
-       (ARM_FEATURE_CORE_LOW): Likewise.
-       (ARM_FEATURE_CORE_COPROC): Likewise.
-
-2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64.h (AARCH64_FEATURE_RDMA): New.
-
-2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64.h (AARCH64_FEATURE_LOR): New.
-
-2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64.h (AARCH64_FEATURE_PAN): New.
-       (aarch64_sys_reg_supported_p): Declare.
-       (aarch64_pstatefield_supported_p): Declare.
-
 2014-10-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 
        * sparc.h (sparc_opcode): new field `hwcaps2'.
diff --git a/include/opcode/ChangeLog.linaro b/include/opcode/ChangeLog.linaro
new file mode 100644 (file)
index 0000000..3251550
--- /dev/null
@@ -0,0 +1,122 @@
+2016-10-20  Adhemerval Zanella  <adhemerval.zanella@linaro.org>
+
+       Backport from 2.25.
+       
+       2015-12-15  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * arm.h (ARM_ARCH_V8_1A): Add the CRC_EXT_ARMV8 co-processor
+       feature macro.
+       (ARM_ARCH_V8_2A): Likewise.
+
+       2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB.
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-dis-2.c: Regenerate.
+       * aarch64-opc-2.c: Regenerate.
+       * aarch64-opc.c (aarch64_hint_options): Add "csync".
+       (aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB.
+       * aarch64-tbl.h (aarch64_feature_stat_profile): New.
+       (STAT_PROFILE): New.
+       (aarch64_opcode_table): Add "psb".
+       (AARCH64_OPERANDS): Add "BARRIER_PSB".
+
+       2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64.h (aarch64_hint_options): Declare.
+       (aarch64_opnd_info): Add field hint_option.
+
+       2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64.h (AARCH64_FEATURE_PROFILE): New.
+
+       2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.
+
+       2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
+       (aarch64_sys_ins_reg_has_xt): Declare.
+
+       2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64.h (AARCH64_FEATURE_RAS): New.
+       (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.
+
+       2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64.h (AARCH64_FEATURE_F16): Fix clash with
+       AARCH64_FEATURE_V8_1.
+       (AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
+       (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
+       AARCH64_FEATURE_V8_1.
+
+       2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64.h (aarch64_op): Add OP_BFC.
+
+       2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64.h (AARCH64_FEATURE_F16): New.
+       (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2
+       features.
+
+       2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64.h (AARCH64_FEATURE_V8_1): New.
+       (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.
+
+       2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * arm.h (ARM_EXT2_V8_2A): New.
+       (ARM_ARCH_V8_2A): New.
+
+       2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64.h (AARCH64_FEATURE_V8_2): New.
+       (AARCH64_ARCH_V8_2): New.
+
+       2015-06-04  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64.h (AARCH64_V8_1): New.
+
+       2015-06-03  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
+       (ARM_ARCH_V8_1A): New.
+       (ARM_ARCH_V8_1A_FP): New.
+       (ARM_ARCH_V8_1A_SIMD): New.
+       (ARM_ARCH_V8_1A_CRYPTOV1): New.
+       (ARM_FEATURE_CORE): New.
+
+       2015-03-24  Terry Guo  <terry.guo@arm.com>
+
+       * arm.h (arm_feature_set): Extended to provide more available bits.
+       (ARM_ANY): Updated to follow above new definition.
+       (ARM_CPU_HAS_FEATURE): Likewise.
+       (ARM_CPU_IS_ANY): Likewise.
+       (ARM_MERGE_FEATURE_SETS): Likewise.
+       (ARM_CLEAR_FEATURE): Likewise.
+       (ARM_FEATURE): Likewise.
+       (ARM_FEATURE_COPY): New macro.
+       (ARM_FEATURE_EQUAL): Likewise.
+       (ARM_FEATURE_ZERO): Likewise.
+       (ARM_FEATURE_CORE_EQUAL): Likewise.
+       (ARM_FEATURE_LOW): Likewise.
+       (ARM_FEATURE_CORE_LOW): Likewise.
+       (ARM_FEATURE_CORE_COPROC): Likewise.
+
+       2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64.h (AARCH64_FEATURE_RDMA): New.
+
+       2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64.h (AARCH64_FEATURE_LOR): New.
+
+       2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64.h (AARCH64_FEATURE_PAN): New.
+       (aarch64_sys_reg_supported_p): Declare.
+       (aarch64_pstatefield_supported_p): Declare.
index ae17f25021a08b908d152bd0d2e9c59f8580b6d8..3a6e3c3b0c0aee0ae7d19a868cab8bd9872c3b3f 100644 (file)
@@ -1,17 +1,3 @@
-2015-04-01  Tejas Belagod  <tejas.belagod@arm.com>
-
-       * emultempl/aarch64elf.em
-       (aarch64_elf_create_output_section_statements): Add parameter in
-       bfd_elf${ELFSIZE}_aarch64_set_options call.
-       (OPTION_FIX_ERRATUM_843419): Define.
-       (PARSE_AND_LIST_LONGOPTS): Add fix-cortex-a53-843419.
-       (PARSE_AND_LIST_ARGS_CASES): Add OPTION_FIX_ERRATUM_843419.
-
-2015-03-24  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-
-       * emultempl/aarch64elf.em (_aarch64_add_stub_section): Set section
-       alignment to 2.
-
 2014-12-23  Tristan Gingold  <gingold@adacore.com>
 
        * configure: Regenerate.
diff --git a/ld/ChangeLog.linaro b/ld/ChangeLog.linaro
new file mode 100644 (file)
index 0000000..6092fd6
--- /dev/null
@@ -0,0 +1,17 @@
+2016-10-20  Adhemerval Zanella  <adhemerval.zanella@linaro.org>
+
+       Backport from 2.25.
+
+       2015-04-01  Tejas Belagod  <tejas.belagod@arm.com>
+
+       * emultempl/aarch64elf.em
+       (aarch64_elf_create_output_section_statements): Add parameter in
+       bfd_elf${ELFSIZE}_aarch64_set_options call.
+       (OPTION_FIX_ERRATUM_843419): Define.
+       (PARSE_AND_LIST_LONGOPTS): Add fix-cortex-a53-843419.
+       (PARSE_AND_LIST_ARGS_CASES): Add OPTION_FIX_ERRATUM_843419.
+
+       2015-03-24  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+       * emultempl/aarch64elf.em (_aarch64_add_stub_section): Set section
+       alignment to 2.
index a957236d315c69bec82809edfdd455e1f041681a..3c2df32fa6e549cbb0844b7101052ce994a5050f 100644 (file)
@@ -1,34 +1,3 @@
-2015-01-13  Thomas Preud'homme <thomas.preudhomme@arm.com>
-
-       * ld-aarch64/aarch64-elf.exp: Added relocs-257-symbolic-func test.
-       * ld-aarch64/relocs-257-symbolic-func.d: New file.
-       * ld-aarch64/relocs-257-symbolic-func.s: Likewise.
-
-2015-07-25  Alan Modra  <amodra@gmail.com>
-
-       * ld-elf/symbolic-func.s,
-       * ld-elf/symbolic-func.r: New test.
-       * ld-elf/elf.exp: Run it.
-
-2015-04-01  Tejas Belagod  <tejas.belagod@arm.com>
-
-       * ld-aarch64/aarch64-elf.exp: Add erratum843419 test.
-       * ld-aarch64/erratum843419.d: New.
-       * ld-aarch64/erratum843419.s: New.
-
-2015-03-25  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-
-       * ld-aarch64/erratum835769.d: Adjust for initial branch over stub
-       section.
-       * ld-aarch64/farcall-b.d: Likewise.
-       * ld-aarch64/farcall-bl.d: Likewise.
-       * ld-aarch64/farcall-back.d: Likewise.
-
-2015-03-25  Marcus Shawcroft  <marcus.shawcroft@arm.com>
-
-       * ld-aarch64/erratum835769.d: Adjust for removal of padding before
-       835769 workaround stubs.
-
 2015-01-05  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR ld/17773
diff --git a/ld/testsuite/ChangeLog.linaro b/ld/testsuite/ChangeLog.linaro
new file mode 100644 (file)
index 0000000..7cdadcd
--- /dev/null
@@ -0,0 +1,34 @@
+2016-10-20  Adhemerval Zanella  <adhemerval.zanella@linaro.org>
+
+       Backport from 2.25.
+
+       2015-01-13  Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+       * ld-aarch64/aarch64-elf.exp: Added relocs-257-symbolic-func test.
+       * ld-aarch64/relocs-257-symbolic-func.d: New file.
+       * ld-aarch64/relocs-257-symbolic-func.s: Likewise.
+
+       2015-07-25  Alan Modra  <amodra@gmail.com>
+
+       * ld-elf/symbolic-func.s,
+       * ld-elf/symbolic-func.r: New test.
+       * ld-elf/elf.exp: Run it.
+
+       2015-04-01  Tejas Belagod  <tejas.belagod@arm.com>
+
+       * ld-aarch64/aarch64-elf.exp: Add erratum843419 test.
+       * ld-aarch64/erratum843419.d: New.
+       * ld-aarch64/erratum843419.s: New.
+
+       2015-03-25  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+       * ld-aarch64/erratum835769.d: Adjust for initial branch over stub
+       section.
+       * ld-aarch64/farcall-b.d: Likewise.
+       * ld-aarch64/farcall-bl.d: Likewise.
+       * ld-aarch64/farcall-back.d: Likewise.
+
+       2015-03-25  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+       * ld-aarch64/erratum835769.d: Adjust for removal of padding before
+       835769 workaround stubs.
index 9abd886c4d30d1eba81acdea15bf1749620f2da4..e19e382524e9ae78b4bb857469b23fc350e394ae 100644 (file)
@@ -1,211 +1,3 @@
-2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * arm-dis.c (arm_opcodes): Add "esb".
-       (thumb_opcodes): Likewise.
-
-2015-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
-
-       * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
-       <ldah>: ... to this.
-
-2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
-
-       * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
-
-2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64-asm.c (aarch64_ins_hint): New.
-       * aarch64-asm.h (aarch64_ins_hint): Declare.
-       * aarch64-dis.c (aarch64_ext_hint): New.
-       * aarch64-dis.h (aarch64_ext_hint): Declare.
-       * aarch64-opc-2.c: Regenerate.
-       * aarch64-opc.c (aarch64_hint_options): New.
-       * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
-
-2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
-
-2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
-       pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
-       pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
-       pmscr_el2.
-       (aarch64_sys_reg_supported_p): Add architecture feature tests for
-       the new registers.
-
-2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
-       (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
-       feature test for "s1e1rp" and "s1e1wp".
-
-2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
-       (aarch64_sys_ins_reg_supported_p): New.
-
-2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
-       with aarch64_sys_ins_reg_has_xt.
-       (aarch64_ext_sysins_op): Likewise.
-       * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
-       (F_HASXT): New.
-       (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
-       (aarch64_sys_regs_dc): Likewise.
-       (aarch64_sys_regs_at): Likewise.
-       (aarch64_sys_regs_tlbi): Likewise.
-       (aarch64_sys_ins_reg_has_xt): New.
-
-2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64-opc.c (aarch64_sys_regs): Add "uao".
-       (aarch64_sys_reg_supported_p): Add comment.  Add checks for "uao".
-       (aarch64_pstatefields): Add "uao".
-       (aarch64_pstatefield_supported_p): Add checks for "uao".
-
-2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
-       "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
-       "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
-       (aarch64_sys_reg_supported_p): Add architecture feature tests for
-       new registers.
-
-2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64-asm-2.c: Regenerate.
-       * aarch64-dis-2.c: Regenerate.
-       * aarch64-tbl.h (aarch64_feature_ras): New.
-       (RAS): New.
-       (aarch64_opcode_table): Add "esb".
-
-2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64-opc.c (half_conv_t): New.
-        (expand_fp_imm): Replace is_dp flag with the parameter size to
-       specify the number of bytes for the required expansion.  Treat
-       a 16-bit expansion like a 32-bit expansion.  Add check for an
-       unsupported size request.  Update comment.
-       (aarch64_print_operand): Update to support 16-bit floating point
-       values.  Update for changes to expand_fp_imm.
-
-2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64-tbl.h (aarch64_feature_fp_f16): New.
-       (FP_F16): New.
-
-2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64-asm-2.c: Regenerate.
-       * aarch64-dis-2.c: Regenerate.
-       * aarch64-opc-2.c: Regenerate.
-       * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
-       "rev64".
-
-2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64-asm-2.c: Regenerate.
-       * aarch64-asm.c (convert_bfc_to_bfm): New.
-       (convert_to_real): Add case for OP_BFC.
-       * aarch64-dis-2.c: Regenerate.
-       * aarch64-dis.c: (convert_bfm_to_bfc): New.
-       (convert_to_alias): Add case for OP_BFC.
-       * aarch64-opc-2.c: Regenerate.
-       * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
-       to allow width operand in three-operand instructions.
-       * aarch64-tbl.h (QL_BF1): New.
-       (aarch64_feature_v8_2): New.
-       (ARMV8_2): New.
-       (aarch64_opcode_table): Add "bfc".
-
-2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64-asm-2.c: Regenerate.
-       * aarch64-dis-2.c: Regenerate.
-       * aarch64-dis.c: Weaken assert.
-       * aarch64-gen.c: Include the instruction in the list of its
-       possible aliases.
-
-2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
-       (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
-       feature test.
-
-2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
-       sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
-       tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
-       amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
-       cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
-       cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
-       cnthv_ctl_el2, cnthv_cval_el2.
-       (aarch64_sys_reg_supported_p): Update for the new system
-       registers.
-
-2015-03-24  Terry Guo  <terry.guo@arm.com>
-
-       * arm-dis.c (opcode32): Updated to use new arm feature struct.
-       (opcode16): Likewise.
-       (coprocessor_opcodes): Replace bit with feature struct.
-       (neon_opcodes): Likewise.
-       (arm_opcodes): Likewise.
-       (thumb_opcodes): Likewise.
-       (thumb32_opcodes): Likewise.
-       (print_insn_coprocessor): Likewise.
-       (print_insn_arm): Likewise.
-       (select_arm_features): Follow new feature struct.
-
-2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * arm-dis.c (arm_opcodes): Add "setpan".
-       (thumb_opcodes): Add "setpan".
-
-2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * arm-dis.c (select_arm_features): Rework to avoid used of redefined
-       macros.
-
-2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64-tbl.h (aarch64_feature_rdma): New.
-       (RDMA): New.
-       (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
-       * aarch64-asm-2.c: Regenerate.
-       * aarch64-dis-2.c: Regenerate.
-       * aarch64-opc-2.c: Regenerate.
-
-2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64-tbl.h (aarch64_feature_lor): New.
-       (LOR): New.
-       (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
-       "stllrb", "stllrh".
-       * aarch64-asm-2.c: Regenerate.
-       * aarch64-dis-2.c: Regenerate.
-       * aarch64-opc-2.c: Regenerate.
-
-2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
-
-       * aarch64-opc.c (F_ARCHEXT): New.
-       (aarch64_sys_regs): Add "pan".
-       (aarch64_sys_reg_supported_p): New.
-       (aarch64_pstatefields): Add "pan".
-       (aarch64_pstatefield_supported_p): New.
-
-2015-03-10  Renlin Li  <renlin.li@arm.com>
-
-       * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
-       stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
-       related alias.
-       * aarch64-asm-2.c: Regenerate.
-       * aarch64-dis-2.c: Likewise.
-       * aarch64-opc-2.c: Likewise.
-
 2014-12-23  Tristan Gingold  <gingold@adacore.com>
 
        * configure: Regenerate.
diff --git a/opcodes/ChangeLog.linaro b/opcodes/ChangeLog.linaro
new file mode 100644 (file)
index 0000000..94a5057
--- /dev/null
@@ -0,0 +1,211 @@
+2016-10-20  Adhemerval Zanella  <adhemerval.zanella@linaro.org>
+
+       Backport from 2.25
+
+       2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * arm-dis.c (arm_opcodes): Add "esb".
+       (thumb_opcodes): Likewise.
+
+       2015-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+       * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
+       <ldah>: ... to this.
+
+       2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+       * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
+
+       2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-asm.c (aarch64_ins_hint): New.
+       * aarch64-asm.h (aarch64_ins_hint): Declare.
+       * aarch64-dis.c (aarch64_ext_hint): New.
+       * aarch64-dis.h (aarch64_ext_hint): Declare.
+       * aarch64-opc-2.c: Regenerate.
+       * aarch64-opc.c (aarch64_hint_options): New.
+       * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
+
+       2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
+
+       2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
+       pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
+       pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
+       pmscr_el2.
+       (aarch64_sys_reg_supported_p): Add architecture feature tests for
+       the new registers.
+
+       2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
+       (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
+       feature test for "s1e1rp" and "s1e1wp".
+
+       2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
+       (aarch64_sys_ins_reg_supported_p): New.
+
+       2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
+       with aarch64_sys_ins_reg_has_xt.
+       (aarch64_ext_sysins_op): Likewise.
+       * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
+       (F_HASXT): New.
+       (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
+       (aarch64_sys_regs_dc): Likewise.
+       (aarch64_sys_regs_at): Likewise.
+       (aarch64_sys_regs_tlbi): Likewise.
+       (aarch64_sys_ins_reg_has_xt): New.
+
+       2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_regs): Add "uao".
+       (aarch64_sys_reg_supported_p): Add comment.  Add checks for "uao".
+       (aarch64_pstatefields): Add "uao".
+       (aarch64_pstatefield_supported_p): Add checks for "uao".
+
+       2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
+       "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
+       "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
+       (aarch64_sys_reg_supported_p): Add architecture feature tests for
+       new registers.
+
+       2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-dis-2.c: Regenerate.
+       * aarch64-tbl.h (aarch64_feature_ras): New.
+       (RAS): New.
+       (aarch64_opcode_table): Add "esb".
+
+       2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-opc.c (half_conv_t): New.
+       (expand_fp_imm): Replace is_dp flag with the parameter size to
+       specify the number of bytes for the required expansion.  Treat
+       a 16-bit expansion like a 32-bit expansion.  Add check for an
+       unsupported size request.  Update comment.
+       (aarch64_print_operand): Update to support 16-bit floating point
+       values.  Update for changes to expand_fp_imm.
+
+       2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-tbl.h (aarch64_feature_fp_f16): New.
+       (FP_F16): New.
+
+       2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-dis-2.c: Regenerate.
+       * aarch64-opc-2.c: Regenerate.
+       * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
+       "rev64".
+
+       2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-asm.c (convert_bfc_to_bfm): New.
+       (convert_to_real): Add case for OP_BFC.
+       * aarch64-dis-2.c: Regenerate.
+       * aarch64-dis.c: (convert_bfm_to_bfc): New.
+       (convert_to_alias): Add case for OP_BFC.
+       * aarch64-opc-2.c: Regenerate.
+       * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
+       to allow width operand in three-operand instructions.
+       * aarch64-tbl.h (QL_BF1): New.
+       (aarch64_feature_v8_2): New.
+       (ARMV8_2): New.
+       (aarch64_opcode_table): Add "bfc".
+
+       2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-dis-2.c: Regenerate.
+       * aarch64-dis.c: Weaken assert.
+       * aarch64-gen.c: Include the instruction in the list of its
+       possible aliases.
+
+       2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
+       (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
+       feature test.
+
+       2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
+       sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
+       tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
+       amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
+       cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
+       cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
+       cnthv_ctl_el2, cnthv_cval_el2.
+       (aarch64_sys_reg_supported_p): Update for the new system
+       registers.
+
+       2015-03-24  Terry Guo  <terry.guo@arm.com>
+
+       * arm-dis.c (opcode32): Updated to use new arm feature struct.
+       (opcode16): Likewise.
+       (coprocessor_opcodes): Replace bit with feature struct.
+       (neon_opcodes): Likewise.
+       (arm_opcodes): Likewise.
+       (thumb_opcodes): Likewise.
+       (thumb32_opcodes): Likewise.
+       (print_insn_coprocessor): Likewise.
+       (print_insn_arm): Likewise.
+       (select_arm_features): Follow new feature struct.
+
+       2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * arm-dis.c (arm_opcodes): Add "setpan".
+       (thumb_opcodes): Add "setpan".
+
+       2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * arm-dis.c (select_arm_features): Rework to avoid used of redefined
+       macros.
+
+       2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-tbl.h (aarch64_feature_rdma): New.
+       (RDMA): New.
+       (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-dis-2.c: Regenerate.
+       * aarch64-opc-2.c: Regenerate.
+
+       2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-tbl.h (aarch64_feature_lor): New.
+       (LOR): New.
+       (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
+       "stllrb", "stllrh".
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-dis-2.c: Regenerate.
+       * aarch64-opc-2.c: Regenerate.
+
+       2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-opc.c (F_ARCHEXT): New.
+       (aarch64_sys_regs): Add "pan".
+       (aarch64_sys_reg_supported_p): New.
+       (aarch64_pstatefields): Add "pan".
+       (aarch64_pstatefield_supported_p): New.
+
+       2015-03-10  Renlin Li  <renlin.li@arm.com>
+
+       * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
+       stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
+       related alias.
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-dis-2.c: Likewise.
+       * aarch64-opc-2.c: Likewise.