--- /dev/null
+From 4405dde4e76715854529b8a445d23d49dd904e43 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 3 Jan 2023 17:45:30 +0100
+Subject: clk: microchip: mpfs-ccc: Use devm_kasprintf() for allocating
+ formatted strings
+
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+
+[ Upstream commit 86d884f5287f4369c198811aaa4931a3a11f36d2 ]
+
+In various places, string buffers of a fixed size are allocated, and
+filled using snprintf() with the same fixed size, which is error-prone.
+
+Replace this by calling devm_kasprintf() instead, which always uses the
+appropriate size.
+
+While at it, remove an unneeded intermediate variable, which allows us
+to drop a cast as a bonus.
+
+With the initial behavior it would have been possible to have a device tree
+with a node address that would make "ccc<node_address>_pll<N>" exceed
+18 characters. If that happened, the <N> would be cut off & both
+pll 0 & 1 would be named identically. If that happens, pll1 would fail
+to register. Thus, the fixes tag has been added to this commit.
+
+Fixes: d39fb172760e ("clk: microchip: add PolarFire SoC fabric clock support")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
+Tested-by: Conor Dooley <conor.dooley@microchip.com>
+[claudiu.beznea: added the rationale behind fixes tag]
+Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
+Link: https://lore.kernel.org/r/f904fd28b2087d1463ea65f059924e3b1acc193c.1672764239.git.geert+renesas@glider.be
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/microchip/clk-mpfs-ccc.c | 10 ++++------
+ 1 file changed, 4 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/clk/microchip/clk-mpfs-ccc.c b/drivers/clk/microchip/clk-mpfs-ccc.c
+index 32aae880a14f3..0ddc73e07be42 100644
+--- a/drivers/clk/microchip/clk-mpfs-ccc.c
++++ b/drivers/clk/microchip/clk-mpfs-ccc.c
+@@ -164,12 +164,11 @@ static int mpfs_ccc_register_outputs(struct device *dev, struct mpfs_ccc_out_hw_
+
+ for (unsigned int i = 0; i < num_clks; i++) {
+ struct mpfs_ccc_out_hw_clock *out_hw = &out_hws[i];
+- char *name = devm_kzalloc(dev, 23, GFP_KERNEL);
++ char *name = devm_kasprintf(dev, GFP_KERNEL, "%s_out%u", parent->name, i);
+
+ if (!name)
+ return -ENOMEM;
+
+- snprintf(name, 23, "%s_out%u", parent->name, i);
+ out_hw->divider.hw.init = CLK_HW_INIT_HW(name, &parent->hw, &clk_divider_ops, 0);
+ out_hw->divider.reg = data->pll_base[i / MPFS_CCC_OUTPUTS_PER_PLL] +
+ out_hw->reg_offset;
+@@ -201,14 +200,13 @@ static int mpfs_ccc_register_plls(struct device *dev, struct mpfs_ccc_pll_hw_clo
+
+ for (unsigned int i = 0; i < num_clks; i++) {
+ struct mpfs_ccc_pll_hw_clock *pll_hw = &pll_hws[i];
+- char *name = devm_kzalloc(dev, 18, GFP_KERNEL);
+
+- if (!name)
++ pll_hw->name = devm_kasprintf(dev, GFP_KERNEL, "ccc%s_pll%u",
++ strchrnul(dev->of_node->full_name, '@'), i);
++ if (!pll_hw->name)
+ return -ENOMEM;
+
+ pll_hw->base = data->pll_base[i];
+- snprintf(name, 18, "ccc%s_pll%u", strchrnul(dev->of_node->full_name, '@'), i);
+- pll_hw->name = (const char *)name;
+ pll_hw->hw.init = CLK_HW_INIT_PARENTS_DATA_FIXED_SIZE(pll_hw->name,
+ pll_hw->parents,
+ &mpfs_ccc_pll_ops, 0);
+--
+2.39.0
+
--- /dev/null
+From d743196620dda5edb095d27ffc7acf6b79a1d32f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 20 Jan 2023 09:48:56 +1030
+Subject: pinctrl: aspeed: Fix confusing types in return value
+
+From: Joel Stanley <joel@jms.id.au>
+
+[ Upstream commit 287a344a11f1ebd31055cf9b22c88d7005f108d7 ]
+
+The function signature is int, but we return a bool. Instead return a
+negative errno as the kerneldoc suggests.
+
+Fixes: 4d3d0e4272d8 ("pinctrl: Add core support for Aspeed SoCs")
+Signed-off-by: Joel Stanley <joel@jms.id.au>
+Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
+Link: https://lore.kernel.org/r/20230119231856.52014-1-joel@jms.id.au
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pinctrl/aspeed/pinctrl-aspeed.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
+index a30912a92f057..f93d6959cee94 100644
+--- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c
++++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
+@@ -113,7 +113,7 @@ static int aspeed_disable_sig(struct aspeed_pinmux_data *ctx,
+ int ret = 0;
+
+ if (!exprs)
+- return true;
++ return -EINVAL;
+
+ while (*exprs && !ret) {
+ ret = aspeed_sig_expr_disable(ctx, *exprs);
+--
+2.39.0
+
--- /dev/null
+From 4c3e209f99cc5cefc4a706306a4f0602f97fa9d8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 31 Jan 2023 08:38:45 +1030
+Subject: pinctrl: aspeed: Revert "Force to disable the function's signal"
+
+From: Joel Stanley <joel@jms.id.au>
+
+[ Upstream commit 606d4ef4922662ded34aa7218288c3043ce0a41a ]
+
+This reverts commit cf517fef601b9dde151f0afc27164d13bf1fd907.
+
+The commit cf517fef601b ("pinctrl: aspeed: Force to disable the
+function's signal") exposed a problem with fetching the regmap for
+reading the GFX register.
+
+The Romulus machine the device tree contains a gpio hog for GPIO S7.
+With the patch applied:
+
+ Muxing pin 151 for GPIO
+ Disabling signal VPOB9 for VPO
+ aspeed-g5-pinctrl 1e6e2080.pinctrl: Failed to acquire regmap for IP block 1
+ aspeed-g5-pinctrl 1e6e2080.pinctrl: request() failed for pin 151
+
+The code path is aspeed-gpio -> pinmux-g5 -> regmap -> clk, and the
+of_clock code returns an error as it doesn't have a valid struct clk_hw
+pointer. The regmap call happens because pinmux wants to check the GFX
+node (IP block 1) to query bits there.
+
+For reference, before the offending patch:
+
+ Muxing pin 151 for GPIO
+ Disabling signal VPOB9 for VPO
+ Want SCU8C[0x00000080]=0x1, got 0x0 from 0x00000000
+ Disabling signal VPOB9 for VPOOFF1
+ Want SCU8C[0x00000080]=0x1, got 0x0 from 0x00000000
+ Disabling signal VPOB9 for VPOOFF2
+ Want SCU8C[0x00000080]=0x1, got 0x0 from 0x00000000
+ Enabling signal GPIOS7 for GPIOS7
+ Muxed pin 151 as GPIOS7
+ gpio-943 (seq_cont): hogged as output/low
+
+We can't skip the clock check to allow pinmux to proceed, because the
+write to disable VPOB9 will try to set a bit in the GFX register space
+which will not stick when the IP is in reset. However, we do not want to
+enable the IP just so pinmux can do a disable-enable dance for the pin.
+
+For now, revert the offending patch while a correct solution is found.
+
+Fixes: cf517fef601b ("pinctrl: aspeed: Force to disable the function's signal")
+Link: https://github.com/openbmc/linux/issues/218
+Signed-off-by: Joel Stanley <joel@jms.id.au>
+Link: https://lore.kernel.org/r/20230130220845.917985-1-joel@jms.id.au
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pinctrl/aspeed/pinctrl-aspeed.c | 11 ++++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
+index f93d6959cee94..5a12fc7cf91fb 100644
+--- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c
++++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
+@@ -92,10 +92,19 @@ static int aspeed_sig_expr_enable(struct aspeed_pinmux_data *ctx,
+ static int aspeed_sig_expr_disable(struct aspeed_pinmux_data *ctx,
+ const struct aspeed_sig_expr *expr)
+ {
++ int ret;
++
+ pr_debug("Disabling signal %s for %s\n", expr->signal,
+ expr->function);
+
+- return aspeed_sig_expr_set(ctx, expr, false);
++ ret = aspeed_sig_expr_eval(ctx, expr, true);
++ if (ret < 0)
++ return ret;
++
++ if (ret)
++ return aspeed_sig_expr_set(ctx, expr, false);
++
++ return 0;
+ }
+
+ /**
+--
+2.39.0
+
--- /dev/null
+From ceebf8e532b719ee8d89224d0ae0c98254262c38 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 6 Feb 2023 16:15:59 +0200
+Subject: pinctrl: intel: Restore the pins that used to be in Direct IRQ mode
+
+From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+
+[ Upstream commit a8520be3ffef3d25b53bf171a7ebe17ee0154175 ]
+
+If the firmware mangled the register contents too much,
+check the saved value for the Direct IRQ mode. If it
+matches, we will restore the pin state.
+
+Reported-by: Jim Minter <jimminter@microsoft.com>
+Fixes: 6989ea4881c8 ("pinctrl: intel: Save and restore pins in "direct IRQ" mode")
+Tested-by: Jim Minter <jimminter@microsoft.com>
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
+Link: https://lore.kernel.org/r/20230206141558.20916-1-andriy.shevchenko@linux.intel.com
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pinctrl/intel/pinctrl-intel.c | 16 +++++++++++++---
+ 1 file changed, 13 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
+index 047a8374b4fdc..954a412267402 100644
+--- a/drivers/pinctrl/intel/pinctrl-intel.c
++++ b/drivers/pinctrl/intel/pinctrl-intel.c
+@@ -1676,6 +1676,12 @@ const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_
+ EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data);
+
+ #ifdef CONFIG_PM_SLEEP
++static bool __intel_gpio_is_direct_irq(u32 value)
++{
++ return (value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) &&
++ (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO);
++}
++
+ static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
+ {
+ const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
+@@ -1709,8 +1715,7 @@ static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int
+ * See https://bugzilla.kernel.org/show_bug.cgi?id=214749.
+ */
+ value = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
+- if ((value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) &&
+- (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO))
++ if (__intel_gpio_is_direct_irq(value))
+ return true;
+
+ return false;
+@@ -1840,7 +1845,12 @@ int intel_pinctrl_resume_noirq(struct device *dev)
+ for (i = 0; i < pctrl->soc->npins; i++) {
+ const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
+
+- if (!intel_pinctrl_should_save(pctrl, desc->number))
++ if (!(intel_pinctrl_should_save(pctrl, desc->number) ||
++ /*
++ * If the firmware mangled the register contents too much,
++ * check the saved value for the Direct IRQ mode.
++ */
++ __intel_gpio_is_direct_irq(pads[i].padcfg0)))
+ continue;
+
+ intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0);
+--
+2.39.0
+
--- /dev/null
+From dd34ba549cab5cad3ed553cb9cc0498bf19c098a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 18 Jan 2023 14:21:16 +0800
+Subject: pinctrl: mediatek: Fix the drive register definition of some Pins
+
+From: Guodong Liu <Guodong.Liu@mediatek.com>
+
+[ Upstream commit 5754a1c98b18009cb3030dc391aa37b77428a0bd ]
+
+The drive adjustment register definition of gpio13 and gpio81 is wrong:
+"the start address for the range" of gpio18 is corrected to 0x000,
+"the start bit for the first register within the range" of gpio81 is
+corrected to 24.
+
+Fixes: 6cf5e9ef362a ("pinctrl: add pinctrl driver on mt8195")
+Signed-off-by: Guodong Liu <Guodong.Liu@mediatek.com>
+Link: https://lore.kernel.org/r/20230118062116.26315-1-Guodong.Liu@mediatek.com
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pinctrl/mediatek/pinctrl-mt8195.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8195.c b/drivers/pinctrl/mediatek/pinctrl-mt8195.c
+index 89557c7ed2ab0..09c4dcef93383 100644
+--- a/drivers/pinctrl/mediatek/pinctrl-mt8195.c
++++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c
+@@ -659,7 +659,7 @@ static const struct mtk_pin_field_calc mt8195_pin_drv_range[] = {
+ PIN_FIELD_BASE(10, 10, 4, 0x010, 0x10, 9, 3),
+ PIN_FIELD_BASE(11, 11, 4, 0x000, 0x10, 24, 3),
+ PIN_FIELD_BASE(12, 12, 4, 0x010, 0x10, 12, 3),
+- PIN_FIELD_BASE(13, 13, 4, 0x010, 0x10, 27, 3),
++ PIN_FIELD_BASE(13, 13, 4, 0x000, 0x10, 27, 3),
+ PIN_FIELD_BASE(14, 14, 4, 0x010, 0x10, 15, 3),
+ PIN_FIELD_BASE(15, 15, 4, 0x010, 0x10, 0, 3),
+ PIN_FIELD_BASE(16, 16, 4, 0x010, 0x10, 18, 3),
+@@ -708,7 +708,7 @@ static const struct mtk_pin_field_calc mt8195_pin_drv_range[] = {
+ PIN_FIELD_BASE(78, 78, 3, 0x000, 0x10, 15, 3),
+ PIN_FIELD_BASE(79, 79, 3, 0x000, 0x10, 18, 3),
+ PIN_FIELD_BASE(80, 80, 3, 0x000, 0x10, 21, 3),
+- PIN_FIELD_BASE(81, 81, 3, 0x000, 0x10, 28, 3),
++ PIN_FIELD_BASE(81, 81, 3, 0x000, 0x10, 24, 3),
+ PIN_FIELD_BASE(82, 82, 3, 0x000, 0x10, 27, 3),
+ PIN_FIELD_BASE(83, 83, 3, 0x010, 0x10, 0, 3),
+ PIN_FIELD_BASE(84, 84, 3, 0x010, 0x10, 3, 3),
+--
+2.39.0
+
--- /dev/null
+From 227ddc84f0afbd963ad3e677092f643520cae054 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 18 Nov 2022 13:43:32 +0300
+Subject: pinctrl: single: fix potential NULL dereference
+
+From: Maxim Korotkov <korotkov.maxim.s@gmail.com>
+
+[ Upstream commit d2d73e6d4822140445ad4a7b1c6091e0f5fe703b ]
+
+Added checking of pointer "function" in pcs_set_mux().
+pinmux_generic_get_function() can return NULL and the pointer
+"function" was dereferenced without checking against NULL.
+
+Found by Linux Verification Center (linuxtesting.org) with SVACE.
+
+Fixes: 571aec4df5b7 ("pinctrl: single: Use generic pinmux helpers for managing functions")
+Signed-off-by: Maxim Korotkov <korotkov.maxim.s@gmail.com>
+Reviewed-by: Tony Lindgren <tony@atomide.com>
+Link: https://lore.kernel.org/r/20221118104332.943-1-korotkov.maxim.s@gmail.com
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pinctrl/pinctrl-single.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
+index 414ee6bb8ac98..9ad8f70206142 100644
+--- a/drivers/pinctrl/pinctrl-single.c
++++ b/drivers/pinctrl/pinctrl-single.c
+@@ -372,6 +372,8 @@ static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
+ if (!pcs->fmask)
+ return 0;
+ function = pinmux_generic_get_function(pctldev, fselector);
++ if (!function)
++ return -EINVAL;
+ func = function->data;
+ if (!func)
+ return -EINVAL;
+--
+2.39.0
+
asoc-tas5805m-add-missing-page-switch.patch
asoc-fsl_sai-fix-getting-version-from-verid.patch
asoc-topology-return-enomem-on-memory-allocation-fai.patch
+clk-microchip-mpfs-ccc-use-devm_kasprintf-for-alloca.patch
+pinctrl-mediatek-fix-the-drive-register-definition-o.patch
+pinctrl-aspeed-fix-confusing-types-in-return-value.patch
+pinctrl-single-fix-potential-null-dereference.patch
+spi-dw-fix-wrong-fifo-level-setting-for-long-xfers.patch
+pinctrl-aspeed-revert-force-to-disable-the-function-.patch
+pinctrl-intel-restore-the-pins-that-used-to-be-in-di.patch
--- /dev/null
+From 0912aec78122854cc1bd19cb8c09fc5c81ac9faf Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 13 Jan 2023 21:59:42 +0300
+Subject: spi: dw: Fix wrong FIFO level setting for long xfers
+
+From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+
+[ Upstream commit c63b8fd14a7db719f8252038a790638728c4eb66 ]
+
+Due to using the u16 type in the min_t() macros the SPI transfer length
+will be cast to word before participating in the conditional statement
+implied by the macro. Thus if the transfer length is greater than 64KB the
+Tx/Rx FIFO threshold level value will be determined by the leftover of the
+truncated after the type-case length. In the worst case it will cause the
+dramatical performance drop due to the "Tx FIFO Empty" or "Rx FIFO Full"
+interrupts triggered on each xfer word sent/received to/from the bus.
+
+The problem can be easily fixed by specifying the unsigned int type in the
+min_t() macros thus preventing the possible data loss.
+
+Fixes: ea11370fffdf ("spi: dw: get TX level without an additional variable")
+Reported-by: Sergey Nazarov <Sergey.Nazarov@baikalelectronics.ru>
+Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Link: https://lore.kernel.org/r/20230113185942.2516-1-Sergey.Semin@baikalelectronics.ru
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/spi/spi-dw-core.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
+index 99edddf9958b9..c3bfb6c84cab2 100644
+--- a/drivers/spi/spi-dw-core.c
++++ b/drivers/spi/spi-dw-core.c
+@@ -366,7 +366,7 @@ static void dw_spi_irq_setup(struct dw_spi *dws)
+ * will be adjusted at the final stage of the IRQ-based SPI transfer
+ * execution so not to lose the leftover of the incoming data.
+ */
+- level = min_t(u16, dws->fifo_len / 2, dws->tx_len);
++ level = min_t(unsigned int, dws->fifo_len / 2, dws->tx_len);
+ dw_writel(dws, DW_SPI_TXFTLR, level);
+ dw_writel(dws, DW_SPI_RXFTLR, level - 1);
+
+--
+2.39.0
+
projects / thirdparty / kernel / stable-queue.git / commitdiff
