Heh, couldn't resist bringing it back from the dead...

Revert "Revert "Add fix for early stepping EM64T which advertise 40bit yet have only 36bit""

This reverts d4a8ddb7448b3396eee195965ecf953cd9f04fde commit.

diff --git a/queue/4GB-memory-intel-dual-core.patch b/queue/4GB-memory-intel-dual-core.patch
new file mode 100644 (file)
index 0000000..1096653
--- /dev/null
+++ b/queue/4GB-memory-intel-dual-core.patch
@@ -0,0 +1,66 @@
+From stable-bounces@linux.kernel.org  Sat Oct 29 23:50:10 2005
+Date: Sun, 30 Oct 2005 01:49:38 -0500
+From: Dave Jones <davej@redhat.com>
+To: Marcel Holtmann <marcel@holtmann.org>
+Cc: discuss@x86-64.org, linux-kernel@vger.kernel.org,
+       Lukas Hejtmanek <xhejtman@mail.muni.cz>, torvalds@osdl.org,
+       Shaohua Li <shaohua.li@intel.com>, stable@kernel.org, ak@suse.de
+Subject: [PATCH] x86_64/i386: Compute correct MTRR mask on early Noconas
+
+From: Andi Kleen <ak@suse.de>
+
+Force correct address space size for MTRR on some 64bit Intel Xeons
+
+They report 40bit, but only have 36bits of physical address space.
+This caused problems with setting up the correct masks for MTRR,
+resulting in incorrect MTRRs.
+
+CPUID workaround for steppings 0F33h(supporting x86) and 0F34h(supporting x86
+and EM64T). Detail info can be found at:
+http://download.intel.com/design/Xeon/specupdt/30240216.pdf
+http://download.intel.com/design/Pentium4/specupdt/30235221.pdf
+
+Signed-off-by: Shaohua Li<shaohua.li@intel.com>
+Signed-off-by: Andi Kleen <ak@suse.de>
+Signed-off-by: Chris Wright <chrisw@osdl.org>
+---
+
+ arch/i386/kernel/cpu/mtrr/main.c |    8 ++++++++
+ arch/x86_64/kernel/setup.c       |    5 +++++
+ 2 files changed, 13 insertions(+)
+
+Index: linux-2.6.14.y/arch/i386/kernel/cpu/mtrr/main.c
+===================================================================
+--- linux-2.6.14.y.orig/arch/i386/kernel/cpu/mtrr/main.c
++++ linux-2.6.14.y/arch/i386/kernel/cpu/mtrr/main.c
+@@ -626,6 +626,14 @@ void __init mtrr_bp_init(void)
+               if (cpuid_eax(0x80000000) >= 0x80000008) {
+                       u32 phys_addr;
+                       phys_addr = cpuid_eax(0x80000008) & 0xff;
++                      /* CPUID workaround for Intel 0F33/0F34 CPU */
++                      if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
++                          boot_cpu_data.x86 == 0xF &&
++                          boot_cpu_data.x86_model == 0x3 &&
++                          (boot_cpu_data.x86_mask == 0x3 ||
++                           boot_cpu_data.x86_mask == 0x4))
++                              phys_addr = 36;
++
+                       size_or_mask = ~((1 << (phys_addr - PAGE_SHIFT)) - 1);
+                       size_and_mask = ~size_or_mask & 0xfff00000;
+               } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR &&
+Index: linux-2.6.14.y/arch/x86_64/kernel/setup.c
+===================================================================
+--- linux-2.6.14.y.orig/arch/x86_64/kernel/setup.c
++++ linux-2.6.14.y/arch/x86_64/kernel/setup.c
+@@ -993,6 +993,11 @@ static void __cpuinit init_intel(struct 
+               unsigned eax = cpuid_eax(0x80000008);
+               c->x86_virt_bits = (eax >> 8) & 0xff;
+               c->x86_phys_bits = eax & 0xff;
++              /* CPUID workaround for Intel 0F34 CPU */
++              if (c->x86_vendor == X86_VENDOR_INTEL &&
++                  c->x86 == 0xF && c->x86_model == 0x3 &&
++                  c->x86_mask == 0x4)
++                      c->x86_phys_bits = 36;
+       }
+ 
+       if (c->x86 == 15)

diff --git a/queue/series b/queue/series
index d1c854416453448369396f80d93c510e1e235c97..3b3e7d82f6e4eef40a9d6385b51da03e0f502a22 100644 (file)
--- a/queue/series
+++ b/queue/series
@@ -16,3 +16,4 @@ ip_conntrack-fix-ftp-irc-tftp-helpers-on-large-ports.patch
 fix-memory-management-error-during.patch
 fix-calculation-of-ah-length-during.patch
 fix-sending-extension-headers-before.patch
+4GB-memory-intel-dual-core.patch