arm64: dts: nuvoton: add refclk and update peripheral clocks for NPCM845

Add a 25 MHz fixed-clock node (refclk) in the NPCM845-EVB board device
tree to represent the external reference clock used by the NPCM845 reset
and clock controller.

Update peripherals (timer0, watchdog0-2) in the NPCM845 device tree to
reference this refclk directly instead of the previous clock controller
output (NPCM8XX_CLK_REFCLK).

Depends-on: arm64: dts: nuvoton: Combine NPCM845 reset and clk nodes

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Link: https://patch.msgid.link/20250706134207.2168184-3-tmaimon77@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
index 400d5c5b71ac0971995e40009d877008fc5083f6..24133528b8e93b64e4c59144de7b423a62531f8c 100644 (file)
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
@@ -47,6 +47,7 @@
                        reg = <0x0 0xf0801000 0x0 0xC4>;
                        nuvoton,sysgcr = <&gcr>;
                        #reset-cells = <2>;
+                       clocks = <&refclk>;
                        #clock-cells = <1>;
                };
 
@@ -71,7 +72,7 @@
                                compatible = "nuvoton,npcm845-timer";
                                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
                                reg = <0x8000 0x1C>;
-                               clocks = <&clk NPCM8XX_CLK_REFCLK>;
+                               clocks = <&refclk>;
                                clock-names = "refclk";
                        };
 
@@ -143,7 +144,7 @@
                                interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
                                reg = <0x801c 0x4>;
                                status = "disabled";
-                               clocks = <&clk NPCM8XX_CLK_REFCLK>;
+                               clocks = <&refclk>;
                                syscon = <&gcr>;
                        };
 
@@ -152,7 +153,7 @@
                                interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
                                reg = <0x901c 0x4>;
                                status = "disabled";
-                               clocks = <&clk NPCM8XX_CLK_REFCLK>;
+                               clocks = <&refclk>;
                                syscon = <&gcr>;
                        };
 
@@ -161,7 +162,7 @@
                                interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
                                reg = <0xa01c 0x4>;
                                status = "disabled";
-                               clocks = <&clk NPCM8XX_CLK_REFCLK>;
+                               clocks = <&refclk>;
                                syscon = <&gcr>;
                        };
                };

diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
index eeceb5b292a8ff1959b7e4c88f772d3202f82a7b..2638ee1c3846d18eaf132347f6dad94eed3f6d94 100644 (file)
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
@@ -19,6 +19,12 @@
        memory@0 {
                reg = <0x0 0x0 0x0 0x40000000>;
        };
+
+       refclk: refclk-25mhz {
+               compatible = "fixed-clock";
+               clock-frequency = <25000000>;
+               #clock-cells = <0>;
+       };
 };
 
 &serial0 {