drop i915 patch

diff --git a/queue-5.3/drm-i915-use-maximum-write-flush-for-pwrite_gtt.patch b/queue-5.3/drm-i915-use-maximum-write-flush-for-pwrite_gtt.patch
deleted file mode 100644 (file)
index 6cbb4e6..0000000
--- a/queue-5.3/drm-i915-use-maximum-write-flush-for-pwrite_gtt.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From bdae33b8b82bb379a5b11040b0b37df25c7871c9 Mon Sep 17 00:00:00 2001
-From: Chris Wilson <chris@chris-wilson.co.uk>
-Date: Thu, 18 Jul 2019 15:54:05 +0100
-Subject: drm/i915: Use maximum write flush for pwrite_gtt
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-From: Chris Wilson <chris@chris-wilson.co.uk>
-
-commit bdae33b8b82bb379a5b11040b0b37df25c7871c9 upstream.
-
-As recently disovered by forcing big-core (!llc) machines to use the GTT
-paths, we need our full GTT write flush before manipulating the GTT PTE
-or else the writes may be directed to the wrong page.
-
-Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
-Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
-Cc: Matthew Auld <matthew.william.auld@gmail.com>
-Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
-Cc: stable@vger.kernel.org
-Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
-Link: https://patchwork.freedesktop.org/patch/msgid/20190718145407.21352-2-chris@chris-wilson.co.uk
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-
----
- drivers/gpu/drm/i915/i915_gem.c |    5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/gpu/drm/i915/i915_gem.c
-+++ b/drivers/gpu/drm/i915/i915_gem.c
-@@ -648,7 +648,8 @@ i915_gem_gtt_pwrite_fast(struct drm_i915
-               unsigned int page_length = PAGE_SIZE - page_offset;
-               page_length = remain < page_length ? remain : page_length;
-               if (node.allocated) {
--                      wmb(); /* flush the write before we modify the GGTT */
-+                      /* flush the write before we modify the GGTT */
-+                      intel_gt_flush_ggtt_writes(ggtt->vm.gt);
-                       ggtt->vm.insert_page(&ggtt->vm,
-                                            i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
-                                            node.start, I915_CACHE_NONE, 0);
-@@ -677,8 +678,8 @@ i915_gem_gtt_pwrite_fast(struct drm_i915
-       i915_gem_object_unlock_fence(obj, fence);
- out_unpin:
-       mutex_lock(&i915->drm.struct_mutex);
-+      intel_gt_flush_ggtt_writes(ggtt->vm.gt);
-       if (node.allocated) {
--              wmb();
-               ggtt->vm.clear_range(&ggtt->vm, node.start, node.size);
-               remove_mappable_node(&node);
-       } else {

diff --git a/queue-5.3/series b/queue-5.3/series
index 9be44aec9deacb673aef6378210dbac6794bf746..4e0feeb33297b08abeaf803ad510c503da8b5c5a 100644 (file)
--- a/queue-5.3/series
+++ b/queue-5.3/series
@@ -69,7 +69,6 @@ drm-nouveau-kms-nv50-don-t-create-mstms-for-edp-connectors.patch
 drm-amd-powerplay-change-metrics-update-period-from-1ms-to-100ms.patch
 drm-i915-gvt-update-vgpu-workload-head-pointer-correctly.patch
 drm-i915-userptr-acquire-the-page-lock-around-set_page_dirty.patch
-drm-i915-use-maximum-write-flush-for-pwrite_gtt.patch
 drm-i915-flush-extra-hard-after-writing-relocations-through-the-gtt.patch
 drm-i915-to-make-vgpu-ppgtt-notificaiton-as-atomic-operation.patch
 mac80211-keep-bhs-disabled-while-calling-drv_tx_wake_queue.patch