--- /dev/null
+From bad720ff3e8e47a04bd88d9bbc8317e7d7e049d3 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Thu, 22 Oct 2009 16:11:14 -0700
+Subject: drm/i915: Add initial bits for VGA modesetting bringup on Sandybridge.
+
+From: Eric Anholt <eric@anholt.net>
+
+commit bad720ff3e8e47a04bd88d9bbc8317e7d7e049d3 upstream.
+
+[needed for stable as it's just a bunch of macros that other drm patches
+need, it changes no code functionality besides adding support for a new
+device type. - gregkh]
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_debugfs.c | 2 -
+ drivers/gpu/drm/i915/i915_dma.c | 16 ++++++---
+ drivers/gpu/drm/i915/i915_drv.h | 26 ++++++++++++++-
+ drivers/gpu/drm/i915/i915_gem.c | 2 -
+ drivers/gpu/drm/i915/i915_gem_tiling.c | 2 -
+ drivers/gpu/drm/i915/i915_irq.c | 18 +++++-----
+ drivers/gpu/drm/i915/intel_bios.c | 3 +
+ drivers/gpu/drm/i915/intel_crt.c | 14 ++++----
+ drivers/gpu/drm/i915/intel_display.c | 56 ++++++++++++++++-----------------
+ drivers/gpu/drm/i915/intel_lvds.c | 2 -
+ drivers/gpu/drm/i915/intel_overlay.c | 2 -
+ include/drm/drm_pciids.h | 1
+ 12 files changed, 88 insertions(+), 56 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_debugfs.c
++++ b/drivers/gpu/drm/i915/i915_debugfs.c
+@@ -162,7 +162,7 @@ static int i915_interrupt_info(struct se
+ struct drm_device *dev = node->minor->dev;
+ drm_i915_private_t *dev_priv = dev->dev_private;
+
+- if (!IS_IRONLAKE(dev)) {
++ if (!HAS_PCH_SPLIT(dev)) {
+ seq_printf(m, "Interrupt enable: %08x\n",
+ I915_READ(IER));
+ seq_printf(m, "Interrupt identity: %08x\n",
+--- a/drivers/gpu/drm/i915/i915_dma.c
++++ b/drivers/gpu/drm/i915/i915_dma.c
+@@ -978,15 +978,21 @@ static int i915_probe_agp(struct drm_dev
+ * Some of the preallocated space is taken by the GTT
+ * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
+ */
+- if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev))
++ if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))
+ overhead = 4096;
+ else
+ overhead = (*aperture_size / 1024) + 4096;
+
+ switch (tmp & INTEL_GMCH_GMS_MASK) {
+ case INTEL_855_GMCH_GMS_DISABLED:
+- DRM_ERROR("video memory is disabled\n");
+- return -1;
++ /* XXX: This is what my A1 silicon has. */
++ if (IS_GEN6(dev)) {
++ stolen = 64 * 1024 * 1024;
++ } else {
++ DRM_ERROR("video memory is disabled\n");
++ return -1;
++ }
++ break;
+ case INTEL_855_GMCH_GMS_STOLEN_1M:
+ stolen = 1 * 1024 * 1024;
+ break;
+@@ -1064,7 +1070,7 @@ static unsigned long i915_gtt_to_phys(st
+ int gtt_offset, gtt_size;
+
+ if (IS_I965G(dev)) {
+- if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
++ if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
+ gtt_offset = 2*1024*1024;
+ gtt_size = 2*1024*1024;
+ } else {
+@@ -1445,7 +1451,7 @@ int i915_driver_load(struct drm_device *
+
+ dev->driver->get_vblank_counter = i915_get_vblank_counter;
+ dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
+- if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
++ if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
+ dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
+ dev->driver->get_vblank_counter = gm45_get_vblank_counter;
+ }
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -1026,7 +1026,7 @@ extern int i915_wait_ring(struct drm_dev
+ #define IS_845G(dev) ((dev)->pci_device == 0x2562)
+ #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
+ #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
+-#define IS_I8XX(dev) (INTEL_INFO(dev)->is_i8xx)
++#define IS_GEN2(dev) (INTEL_INFO(dev)->is_i8xx)
+ #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
+ #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
+ #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
+@@ -1045,8 +1045,29 @@ extern int i915_wait_ring(struct drm_dev
+ #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
+ #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
+
++#define IS_GEN3(dev) (IS_I915G(dev) || \
++ IS_I915GM(dev) || \
++ IS_I945G(dev) || \
++ IS_I945GM(dev) || \
++ IS_G33(dev) || \
++ IS_PINEVIEW(dev))
++#define IS_GEN4(dev) ((dev)->pci_device == 0x2972 || \
++ (dev)->pci_device == 0x2982 || \
++ (dev)->pci_device == 0x2992 || \
++ (dev)->pci_device == 0x29A2 || \
++ (dev)->pci_device == 0x2A02 || \
++ (dev)->pci_device == 0x2A12 || \
++ (dev)->pci_device == 0x2E02 || \
++ (dev)->pci_device == 0x2E12 || \
++ (dev)->pci_device == 0x2E22 || \
++ (dev)->pci_device == 0x2E32 || \
++ (dev)->pci_device == 0x2A42 || \
++ (dev)->pci_device == 0x2E42)
++
+ #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
+
++#define IS_GEN6(dev) ((dev)->pci_device == 0x0102)
++
+ /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
+ * rows, which changed the alignment requirements and fence programming.
+ */
+@@ -1067,6 +1088,9 @@ extern int i915_wait_ring(struct drm_dev
+ #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
+ #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
+
++#define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \
++ IS_GEN6(dev))
++
+ #define PRIMARY_RINGBUFFER_SIZE (128*1024)
+
+ #endif
+--- a/drivers/gpu/drm/i915/i915_gem.c
++++ b/drivers/gpu/drm/i915/i915_gem.c
+@@ -1819,7 +1819,7 @@ i915_do_wait_request(struct drm_device *
+ return -EIO;
+
+ if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
+- if (IS_IRONLAKE(dev))
++ if (HAS_PCH_SPLIT(dev))
+ ier = I915_READ(DEIER) | I915_READ(GTIER);
+ else
+ ier = I915_READ(IER);
+--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
++++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
+@@ -209,7 +209,7 @@ i915_gem_detect_bit_6_swizzle(struct drm
+ uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
+ bool need_disable;
+
+- if (IS_IRONLAKE(dev)) {
++ if (IS_IRONLAKE(dev) || IS_GEN6(dev)) {
+ /* On Ironlake whatever DRAM config, GPU always do
+ * same swizzling setup.
+ */
+--- a/drivers/gpu/drm/i915/i915_irq.c
++++ b/drivers/gpu/drm/i915/i915_irq.c
+@@ -576,7 +576,7 @@ irqreturn_t i915_driver_irq_handler(DRM_
+
+ atomic_inc(&dev_priv->irq_received);
+
+- if (IS_IRONLAKE(dev))
++ if (HAS_PCH_SPLIT(dev))
+ return ironlake_irq_handler(dev);
+
+ iir = I915_READ(IIR);
+@@ -737,7 +737,7 @@ void i915_user_irq_get(struct drm_device
+
+ spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
+ if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
+- if (IS_IRONLAKE(dev))
++ if (HAS_PCH_SPLIT(dev))
+ ironlake_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
+ else
+ i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
+@@ -753,7 +753,7 @@ void i915_user_irq_put(struct drm_device
+ spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
+ BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
+ if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
+- if (IS_IRONLAKE(dev))
++ if (HAS_PCH_SPLIT(dev))
+ ironlake_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
+ else
+ i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
+@@ -861,7 +861,7 @@ int i915_enable_vblank(struct drm_device
+ return -EINVAL;
+
+ spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
+- if (IS_IRONLAKE(dev))
++ if (HAS_PCH_SPLIT(dev))
+ ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
+ DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
+ else if (IS_I965G(dev))
+@@ -883,7 +883,7 @@ void i915_disable_vblank(struct drm_devi
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
+- if (IS_IRONLAKE(dev))
++ if (HAS_PCH_SPLIT(dev))
+ ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
+ DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
+ else
+@@ -897,7 +897,7 @@ void i915_enable_interrupt (struct drm_d
+ {
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+- if (!IS_IRONLAKE(dev))
++ if (!HAS_PCH_SPLIT(dev))
+ opregion_enable_asle(dev);
+ dev_priv->irq_enabled = 1;
+ }
+@@ -1076,7 +1076,7 @@ void i915_driver_irq_preinstall(struct d
+ INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
+ INIT_WORK(&dev_priv->error_work, i915_error_work_func);
+
+- if (IS_IRONLAKE(dev)) {
++ if (HAS_PCH_SPLIT(dev)) {
+ ironlake_irq_preinstall(dev);
+ return;
+ }
+@@ -1108,7 +1108,7 @@ int i915_driver_irq_postinstall(struct d
+
+ dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
+
+- if (IS_IRONLAKE(dev))
++ if (HAS_PCH_SPLIT(dev))
+ return ironlake_irq_postinstall(dev);
+
+ /* Unmask the interrupts that we always want on. */
+@@ -1196,7 +1196,7 @@ void i915_driver_irq_uninstall(struct dr
+
+ dev_priv->vblank_pipe = 0;
+
+- if (IS_IRONLAKE(dev)) {
++ if (HAS_PCH_SPLIT(dev)) {
+ ironlake_irq_uninstall(dev);
+ return;
+ }
+--- a/drivers/gpu/drm/i915/intel_bios.c
++++ b/drivers/gpu/drm/i915/intel_bios.c
+@@ -247,6 +247,7 @@ static void
+ parse_general_features(struct drm_i915_private *dev_priv,
+ struct bdb_header *bdb)
+ {
++ struct drm_device *dev = dev_priv->dev;
+ struct bdb_general_features *general;
+
+ /* Set sensible defaults in case we can't find the general block */
+@@ -263,7 +264,7 @@ parse_general_features(struct drm_i915_p
+ if (IS_I85X(dev_priv->dev))
+ dev_priv->lvds_ssc_freq =
+ general->ssc_freq ? 66 : 48;
+- else if (IS_IRONLAKE(dev_priv->dev))
++ else if (IS_IRONLAKE(dev_priv->dev) || IS_GEN6(dev))
+ dev_priv->lvds_ssc_freq =
+ general->ssc_freq ? 100 : 120;
+ else
+--- a/drivers/gpu/drm/i915/intel_crt.c
++++ b/drivers/gpu/drm/i915/intel_crt.c
+@@ -39,7 +39,7 @@ static void intel_crt_dpms(struct drm_en
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 temp, reg;
+
+- if (IS_IRONLAKE(dev))
++ if (HAS_PCH_SPLIT(dev))
+ reg = PCH_ADPA;
+ else
+ reg = ADPA;
+@@ -113,7 +113,7 @@ static void intel_crt_mode_set(struct dr
+ else
+ dpll_md_reg = DPLL_B_MD;
+
+- if (IS_IRONLAKE(dev))
++ if (HAS_PCH_SPLIT(dev))
+ adpa_reg = PCH_ADPA;
+ else
+ adpa_reg = ADPA;
+@@ -122,7 +122,7 @@ static void intel_crt_mode_set(struct dr
+ * Disable separate mode multiplier used when cloning SDVO to CRT
+ * XXX this needs to be adjusted when we really are cloning
+ */
+- if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
++ if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
+ dpll_md = I915_READ(dpll_md_reg);
+ I915_WRITE(dpll_md_reg,
+ dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
+@@ -136,11 +136,11 @@ static void intel_crt_mode_set(struct dr
+
+ if (intel_crtc->pipe == 0) {
+ adpa |= ADPA_PIPE_A_SELECT;
+- if (!IS_IRONLAKE(dev))
++ if (!HAS_PCH_SPLIT(dev))
+ I915_WRITE(BCLRPAT_A, 0);
+ } else {
+ adpa |= ADPA_PIPE_B_SELECT;
+- if (!IS_IRONLAKE(dev))
++ if (!HAS_PCH_SPLIT(dev))
+ I915_WRITE(BCLRPAT_B, 0);
+ }
+
+@@ -202,7 +202,7 @@ static bool intel_crt_detect_hotplug(str
+ u32 hotplug_en;
+ int i, tries = 0;
+
+- if (IS_IRONLAKE(dev))
++ if (HAS_PCH_SPLIT(dev))
+ return intel_ironlake_crt_detect_hotplug(connector);
+
+ /*
+@@ -524,7 +524,7 @@ void intel_crt_init(struct drm_device *d
+ &intel_output->enc);
+
+ /* Set up the DDC bus. */
+- if (IS_IRONLAKE(dev))
++ if (HAS_PCH_SPLIT(dev))
+ i2c_reg = PCH_GPIOA;
+ else {
+ i2c_reg = GPIOA;
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -232,7 +232,7 @@ struct intel_limit {
+ #define G4X_P2_DISPLAY_PORT_FAST 10
+ #define G4X_P2_DISPLAY_PORT_LIMIT 0
+
+-/* Ironlake */
++/* Ironlake / Sandybridge */
+ /* as we calculate clock using (register_value + 2) for
+ N/M1/M2, so here the range value for them is (actual_value-2).
+ */
+@@ -690,7 +690,7 @@ static const intel_limit_t *intel_limit(
+ struct drm_device *dev = crtc->dev;
+ const intel_limit_t *limit;
+
+- if (IS_IRONLAKE(dev))
++ if (HAS_PCH_SPLIT(dev))
+ limit = intel_ironlake_limit(crtc);
+ else if (IS_G4X(dev)) {
+ limit = intel_g4x_limit(crtc);
+@@ -1366,7 +1366,7 @@ intel_pipe_set_base(struct drm_crtc *crt
+ dspcntr &= ~DISPPLANE_TILED;
+ }
+
+- if (IS_IRONLAKE(dev))
++ if (HAS_PCH_SPLIT(dev))
+ /* must disable */
+ dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
+
+@@ -1427,7 +1427,7 @@ static void i915_disable_vga (struct drm
+ u8 sr1;
+ u32 vga_reg;
+
+- if (IS_IRONLAKE(dev))
++ if (HAS_PCH_SPLIT(dev))
+ vga_reg = CPU_VGACNTRL;
+ else
+ vga_reg = VGACNTRL;
+@@ -2111,7 +2111,7 @@ static bool intel_crtc_mode_fixup(struct
+ struct drm_display_mode *adjusted_mode)
+ {
+ struct drm_device *dev = crtc->dev;
+- if (IS_IRONLAKE(dev)) {
++ if (HAS_PCH_SPLIT(dev)) {
+ /* FDI link clock is fixed at 2.7G */
+ if (mode->clock * 3 > 27000 * 4)
+ return MODE_CLOCK_HIGH;
+@@ -2967,7 +2967,7 @@ static int intel_crtc_mode_set(struct dr
+ refclk / 1000);
+ } else if (IS_I9XX(dev)) {
+ refclk = 96000;
+- if (IS_IRONLAKE(dev))
++ if (HAS_PCH_SPLIT(dev))
+ refclk = 120000; /* 120Mhz refclk */
+ } else {
+ refclk = 48000;
+@@ -3025,7 +3025,7 @@ static int intel_crtc_mode_set(struct dr
+ }
+
+ /* FDI link */
+- if (IS_IRONLAKE(dev)) {
++ if (HAS_PCH_SPLIT(dev)) {
+ int lane, link_bw, bpp;
+ /* eDP doesn't require FDI link, so just set DP M/N
+ according to current link config */
+@@ -3102,7 +3102,7 @@ static int intel_crtc_mode_set(struct dr
+ * PCH B stepping, previous chipset stepping should be
+ * ignoring this setting.
+ */
+- if (IS_IRONLAKE(dev)) {
++ if (HAS_PCH_SPLIT(dev)) {
+ temp = I915_READ(PCH_DREF_CONTROL);
+ /* Always enable nonspread source */
+ temp &= ~DREF_NONSPREAD_SOURCE_MASK;
+@@ -3149,7 +3149,7 @@ static int intel_crtc_mode_set(struct dr
+ reduced_clock.m2;
+ }
+
+- if (!IS_IRONLAKE(dev))
++ if (!HAS_PCH_SPLIT(dev))
+ dpll = DPLL_VGA_MODE_DIS;
+
+ if (IS_I9XX(dev)) {
+@@ -3162,7 +3162,7 @@ static int intel_crtc_mode_set(struct dr
+ sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
+ if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
+ dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
+- else if (IS_IRONLAKE(dev))
++ else if (HAS_PCH_SPLIT(dev))
+ dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
+ }
+ if (is_dp)
+@@ -3174,7 +3174,7 @@ static int intel_crtc_mode_set(struct dr
+ else {
+ dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
+ /* also FPA1 */
+- if (IS_IRONLAKE(dev))
++ if (HAS_PCH_SPLIT(dev))
+ dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
+ if (IS_G4X(dev) && has_reduced_clock)
+ dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
+@@ -3193,7 +3193,7 @@ static int intel_crtc_mode_set(struct dr
+ dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
+ break;
+ }
+- if (IS_I965G(dev) && !IS_IRONLAKE(dev))
++ if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
+ dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
+ } else {
+ if (is_lvds) {
+@@ -3227,7 +3227,7 @@ static int intel_crtc_mode_set(struct dr
+
+ /* Ironlake's plane is forced to pipe, bit 24 is to
+ enable color space conversion */
+- if (!IS_IRONLAKE(dev)) {
++ if (!HAS_PCH_SPLIT(dev)) {
+ if (pipe == 0)
+ dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
+ else
+@@ -3254,14 +3254,14 @@ static int intel_crtc_mode_set(struct dr
+
+
+ /* Disable the panel fitter if it was on our pipe */
+- if (!IS_IRONLAKE(dev) && intel_panel_fitter_pipe(dev) == pipe)
++ if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
+ I915_WRITE(PFIT_CONTROL, 0);
+
+ DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
+ drm_mode_debug_printmodeline(mode);
+
+ /* assign to Ironlake registers */
+- if (IS_IRONLAKE(dev)) {
++ if (HAS_PCH_SPLIT(dev)) {
+ fp_reg = pch_fp_reg;
+ dpll_reg = pch_dpll_reg;
+ }
+@@ -3282,7 +3282,7 @@ static int intel_crtc_mode_set(struct dr
+ if (is_lvds) {
+ u32 lvds;
+
+- if (IS_IRONLAKE(dev))
++ if (HAS_PCH_SPLIT(dev))
+ lvds_reg = PCH_LVDS;
+
+ lvds = I915_READ(lvds_reg);
+@@ -3328,7 +3328,7 @@ static int intel_crtc_mode_set(struct dr
+ /* Wait for the clocks to stabilize. */
+ udelay(150);
+
+- if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
++ if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
+ if (is_sdvo) {
+ sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
+ I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
+@@ -3375,14 +3375,14 @@ static int intel_crtc_mode_set(struct dr
+ /* pipesrc and dspsize control the size that is scaled from, which should
+ * always be the user's requested size.
+ */
+- if (!IS_IRONLAKE(dev)) {
++ if (!HAS_PCH_SPLIT(dev)) {
+ I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
+ (mode->hdisplay - 1));
+ I915_WRITE(dsppos_reg, 0);
+ }
+ I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
+
+- if (IS_IRONLAKE(dev)) {
++ if (HAS_PCH_SPLIT(dev)) {
+ I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
+ I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
+ I915_WRITE(link_m1_reg, m_n.link_m);
+@@ -3403,7 +3403,7 @@ static int intel_crtc_mode_set(struct dr
+
+ intel_wait_for_vblank(dev);
+
+- if (IS_IRONLAKE(dev)) {
++ if (HAS_PCH_SPLIT(dev)) {
+ /* enable address swizzle for tiling buffer */
+ temp = I915_READ(DISP_ARB_CTL);
+ I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
+@@ -3438,7 +3438,7 @@ void intel_crtc_load_lut(struct drm_crtc
+ return;
+
+ /* use legacy palette for Ironlake */
+- if (IS_IRONLAKE(dev))
++ if (HAS_PCH_SPLIT(dev))
+ palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
+ LGC_PALETTE_B;
+
+@@ -3922,7 +3922,7 @@ static void intel_increase_pllclock(stru
+ int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
+ int dpll = I915_READ(dpll_reg);
+
+- if (IS_IRONLAKE(dev))
++ if (HAS_PCH_SPLIT(dev))
+ return;
+
+ if (!dev_priv->lvds_downclock_avail)
+@@ -3961,7 +3961,7 @@ static void intel_decrease_pllclock(stru
+ int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
+ int dpll = I915_READ(dpll_reg);
+
+- if (IS_IRONLAKE(dev))
++ if (HAS_PCH_SPLIT(dev))
+ return;
+
+ if (!dev_priv->lvds_downclock_avail)
+@@ -4382,7 +4382,7 @@ static void intel_setup_outputs(struct d
+ if (IS_MOBILE(dev) && !IS_I830(dev))
+ intel_lvds_init(dev);
+
+- if (IS_IRONLAKE(dev)) {
++ if (HAS_PCH_SPLIT(dev)) {
+ int found;
+
+ if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
+@@ -4451,7 +4451,7 @@ static void intel_setup_outputs(struct d
+ DRM_DEBUG_KMS("probing DP_D\n");
+ intel_dp_init(dev, DP_D);
+ }
+- } else if (IS_I8XX(dev))
++ } else if (IS_GEN2(dev))
+ intel_dvo_init(dev);
+
+ if (SUPPORTS_TV(dev))
+@@ -4599,7 +4599,7 @@ void intel_init_clock_gating(struct drm_
+ * Disable clock gating reported to work incorrectly according to the
+ * specs, but enable as much else as we can.
+ */
+- if (IS_IRONLAKE(dev)) {
++ if (HAS_PCH_SPLIT(dev)) {
+ return;
+ } else if (IS_G4X(dev)) {
+ uint32_t dspclk_gate;
+@@ -4672,7 +4672,7 @@ static void intel_init_display(struct dr
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ /* We always want a DPMS function */
+- if (IS_IRONLAKE(dev))
++ if (HAS_PCH_SPLIT(dev))
+ dev_priv->display.dpms = ironlake_crtc_dpms;
+ else
+ dev_priv->display.dpms = i9xx_crtc_dpms;
+@@ -4715,7 +4715,7 @@ static void intel_init_display(struct dr
+ i830_get_display_clock_speed;
+
+ /* For FIFO watermark updates */
+- if (IS_IRONLAKE(dev))
++ if (HAS_PCH_SPLIT(dev))
+ dev_priv->display.update_wm = NULL;
+ else if (IS_G4X(dev))
+ dev_priv->display.update_wm = g4x_update_wm;
+--- a/drivers/gpu/drm/i915/intel_lvds.c
++++ b/drivers/gpu/drm/i915/intel_lvds.c
+@@ -661,7 +661,7 @@ static enum drm_connector_status intel_l
+ /* ACPI lid methods were generally unreliable in this generation, so
+ * don't even bother.
+ */
+- if (IS_I8XX(dev))
++ if (IS_GEN2(dev))
+ return connector_status_connected;
+
+ if (!dmi_check_system(bad_lid_status) && !acpi_lid_open())
+--- a/drivers/gpu/drm/i915/intel_overlay.c
++++ b/drivers/gpu/drm/i915/intel_overlay.c
+@@ -172,7 +172,7 @@ struct overlay_registers {
+ #define OFC_UPDATE 0x1
+
+ #define OVERLAY_NONPHYSICAL(dev) (IS_G33(dev) || IS_I965G(dev))
+-#define OVERLAY_EXISTS(dev) (!IS_G4X(dev) && !IS_IRONLAKE(dev))
++#define OVERLAY_EXISTS(dev) (!IS_G4X(dev) && !IS_IRONLAKE(dev) && !IS_GEN6(dev))
+
+
+ static struct overlay_registers *intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
+--- a/include/drm/drm_pciids.h
++++ b/include/drm/drm_pciids.h
+@@ -560,4 +560,5 @@
+ {0x8086, 0x35e8, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+ {0x8086, 0x0042, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+ {0x8086, 0x0046, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
++ {0x8086, 0x0102, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+ {0, 0, 0}
projects / thirdparty / kernel / stable-queue.git / commitdiff
