xtensa: Revert "xtensa: Eliminate unwanted reg-reg moves during DFmode input reloads"

Since there are no unwanted reg-reg moves during DFmode input reloads in
recent GCCs, the previously committed patch
"xtensa: eliminate unwanted reg-reg moves during DFmode input reloads"
(commit cfad4856fa46abc878934a9433d0bfc2482ccf00) is no longer necessary
and is therefore being reverted.

gcc/ChangeLog:

	* config/xtensa/predicates.md (reload_operand):
	Remove.
	* config/xtensa/xtensa.md:
	Remove the peephole2 pattern that was previously added.

diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md
index aad4146074af036944f7e17f1ceb29bb8e7a55f8..9aeaba6ad723611b0e0d660c18f0e6302fe01de0 100644 (file)
--- a/gcc/config/xtensa/predicates.md
+++ b/gcc/config/xtensa/predicates.md
@@ -183,19 +183,6 @@
   (and (match_code "const_int")
        (match_test "xtensa_mem_offset (INTVAL (op), SFmode)")))
 
-(define_predicate "reload_operand"
-  (match_code "mem")
-{
-  const_rtx addr = XEXP (op, 0);
-  if (REG_P (addr))
-    return REGNO (addr) == A1_REG;
-  if (GET_CODE (addr) == PLUS)
-    return REG_P (XEXP (addr, 0))
-          && REGNO (XEXP (addr, 0)) == A1_REG
-          && CONST_INT_P (XEXP (addr, 1));
-  return false;
-})
-
 (define_predicate "branch_operator"
   (match_code "eq,ne,lt,ge"))
 

diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index 3064a44f9b552b02e2c5c7e6de25d548f6ce9781..4c4270ae8bcb700850a791c0b1e7295d9bccd439 100644 (file)
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -3345,36 +3345,6 @@
                                    (const_int 8)
                                    (const_int 9))))])
 
-(define_peephole2
-  [(set (match_operand:SI 0 "register_operand")
-       (match_operand:SI 6 "reload_operand"))
-   (set (match_operand:SI 1 "register_operand")
-       (match_operand:SI 7 "reload_operand"))
-   (set (match_operand:SF 2 "register_operand")
-       (match_operand:SF 4 "register_operand"))
-   (set (match_operand:SF 3 "register_operand")
-       (match_operand:SF 5 "register_operand"))]
-  "REGNO (operands[0]) == REGNO (operands[4])
-   && REGNO (operands[1]) == REGNO (operands[5])
-   && peep2_reg_dead_p (4, operands[0])
-   && peep2_reg_dead_p (4, operands[1])"
-  [(set (match_dup 2)
-       (match_dup 6))
-   (set (match_dup 3)
-       (match_dup 7))]
-{
-  HARD_REG_SET regs;
-  int i;
-  CLEAR_HARD_REG_SET (regs);
-  for (i = 0; i <= 3; ++i)
-    if (TEST_HARD_REG_BIT (regs, REGNO (operands[i])))
-      FAIL;
-    else
-      SET_HARD_REG_BIT (regs, REGNO (operands[i]));
-  operands[6] = gen_rtx_MEM (SFmode, XEXP (operands[6], 0));
-  operands[7] = gen_rtx_MEM (SFmode, XEXP (operands[7], 0));
-})
-
 (define_split
   [(clobber (match_operand 0 "register_operand"))]
   "HARD_REGISTER_P (operands[0])