ARM: dts: socfpga: Add basic support for Terrasic's de10-nano

This dts is enough to make the board boot to Linux with the rootfs on
a micro SD card.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/intel/socfpga/Makefile
index c467828aeb4b0a78c409c41d8656f291c3ab54f4..7f69a0355ea50959758a40edbff4de281bf5e52b 100644 (file)
--- a/arch/arm/boot/dts/intel/socfpga/Makefile
+++ b/arch/arm/boot/dts/intel/socfpga/Makefile
@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
        socfpga_cyclone5_mcvevk.dtb \
        socfpga_cyclone5_socdk.dtb \
        socfpga_cyclone5_de0_nano_soc.dtb \
+       socfpga_cyclone5_de10nano.dtb \
        socfpga_cyclone5_sockit.dtb \
        socfpga_cyclone5_socrates.dtb \
        socfpga_cyclone5_sodia.dtb \

diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts
new file mode 100644 (file)
index 0000000..ec25106
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017, Intel Corporation
+ *
+ * based on socfpga_cyclone5_de0_nano_soc.dts
+ */
+/dts-v1/;
+
+#include "socfpga_cyclone5.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+       model = "Terasic DE10-Nano";
+       compatible = "terasic,de10-nano", "altr,socfpga-cyclone5", "altr,socfpga";
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory@0 {
+               /* 1 GiB */
+               device_type = "memory";
+               reg = <0x0 0x40000000>;
+       };
+
+       soc {
+               fpga: bus@ff200000 {
+                       compatible = "simple-bus";
+                       reg = <0xff200000 0x00200000>;
+                       ranges = <0x00000000 0xff200000 0x00200000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       /*
+                        * Here the devices will appear if an FPGA image is
+                        * loaded. Their description is expected to be added
+                        * using a device tree overlay that matches the image.
+                        */
+               };
+       };
+};
+
+&gmac1 {
+       /* Uses a KSZ9031RNX phy */
+       phy-mode = "rgmii-id";
+       rxd0-skew-ps = <420>;
+       rxd1-skew-ps = <420>;
+       rxd2-skew-ps = <420>;
+       rxd3-skew-ps = <420>;
+       txen-skew-ps = <0>;
+       rxdv-skew-ps = <420>;
+       status = "okay";
+};
+
+&gpio0 {
+       status = "okay";
+};
+
+&gpio1 {
+       status = "okay";
+};
+
+&gpio2 {
+       status = "okay";
+};
+
+&i2c0 {
+       clock-frequency = <100000>;
+       status = "okay";
+
+       accelerometer@53 {
+               compatible = "adi,adxl345";
+               reg = <0x53>;
+               /* HPS_GSENSOR_INT is routed to UART0_RX/CAN0_RX/SPIM0_SS1/HPS_GPIO61 */
+               interrupt-parent = <&portc>;
+               interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "INT1";
+       };
+};
+
+&mmc0 {
+       /* micro SD card socket J11 */
+       status = "okay";
+};
+
+&uart0 {
+       /*
+        * Accessible via USB (FT232R) on Mini-USB plug J4
+        * RX = TRACE_D0/SPIS0_CLK/UART0_RX/HPS_GPIO49
+        * TX = TRACE_D1/SPIS0_MOSI/UART0_TX/HPS_GPIO50
+        * no handshaking lines
+        */
+       clock-frequency = <100000000>;
+};