--- /dev/null
+From 6f94b6dd006909a5ef6435cc0af557e945240f48 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Fri, 15 Jan 2016 20:46:53 +0200
+Subject: drm/i915: Don't reject primary plane windowing with color keying enabled on SKL+
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+commit 6f94b6dd006909a5ef6435cc0af557e945240f48 upstream.
+
+On SKL+ plane scaling is mutually exclusive with color keying. The code
+check for this, but during some refactoring the code got changed to
+also reject primary plane windowing when color keying is used. There is
+no such restriction in the hardware, so restore the original logic.
+
+Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
+Fixes: 061e4b8d650a ("drm/i915: clean up atomic plane check functions, v2.")
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: http://patchwork.freedesktop.org/patch/msgid/1452883613-28549-1-git-send-email-ville.syrjala@linux.intel.com
+Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
+Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
+(cherry picked from commit 693bdc28a733dba68b86af295e7509812fec35d9)
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/intel_display.c | 11 ++++++-----
+ 1 file changed, 6 insertions(+), 5 deletions(-)
+
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -13547,11 +13547,12 @@ intel_check_primary_plane(struct drm_pla
+ int max_scale = DRM_PLANE_HELPER_NO_SCALING;
+ bool can_position = false;
+
+- /* use scaler when colorkey is not required */
+- if (INTEL_INFO(plane->dev)->gen >= 9 &&
+- state->ckey.flags == I915_SET_COLORKEY_NONE) {
+- min_scale = 1;
+- max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
++ if (INTEL_INFO(plane->dev)->gen >= 9) {
++ /* use scaler when colorkey is not required */
++ if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
++ min_scale = 1;
++ max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
++ }
+ can_position = true;
+ }
+
--- /dev/null
+From 5efd407674068dede403551bea3b0b134c32513a Mon Sep 17 00:00:00 2001
+From: Jani Nikula <jani.nikula@intel.com>
+Date: Wed, 13 Jan 2016 16:35:20 +0200
+Subject: drm/i915/dp: fall back to 18 bpp when sink capability is unknown
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Jani Nikula <jani.nikula@intel.com>
+
+commit 5efd407674068dede403551bea3b0b134c32513a upstream.
+
+Per DP spec, the source device should fall back to 18 bpp, VESA range
+RGB when the sink capability is unknown. Fix the color depth
+clamping. 18 bpp color depth should ensure full color range in automatic
+mode.
+
+The clamping has been HDMI specific since its introduction in
+
+commit 996a2239f93b03c5972923f04b097f65565c5bed
+Author: Daniel Vetter <daniel.vetter@ffwll.ch>
+Date: Fri Apr 19 11:24:34 2013 +0200
+
+ drm/i915: Disable high-bpc on pre-1.4 EDID screens
+
+Reported-and-tested-by: Dihan Wickremasuriya <nayomal@gmail.com>
+Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=105331
+Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Link: http://patchwork.freedesktop.org/patch/msgid/1452695720-7076-1-git-send-email-jani.nikula@intel.com
+(cherry picked from commit 013dd9e038723bbd2aa67be51847384b75be8253)
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/intel_display.c | 20 +++++++++++++++-----
+ 1 file changed, 15 insertions(+), 5 deletions(-)
+
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -11930,11 +11930,21 @@ connected_sink_compute_bpp(struct intel_
+ pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
+ }
+
+- /* Clamp bpp to 8 on screens without EDID 1.4 */
+- if (connector->base.display_info.bpc == 0 && bpp > 24) {
+- DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
+- bpp);
+- pipe_config->pipe_bpp = 24;
++ /* Clamp bpp to default limit on screens without EDID 1.4 */
++ if (connector->base.display_info.bpc == 0) {
++ int type = connector->base.connector_type;
++ int clamp_bpp = 24;
++
++ /* Fall back to 18 bpp when DP sink capability is unknown. */
++ if (type == DRM_MODE_CONNECTOR_DisplayPort ||
++ type == DRM_MODE_CONNECTOR_eDP)
++ clamp_bpp = 18;
++
++ if (bpp > clamp_bpp) {
++ DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
++ bpp, clamp_bpp);
++ pipe_config->pipe_bpp = clamp_bpp;
++ }
+ }
+ }
+
--- /dev/null
+From 4db3a2448ec8902310acb78de39b6227a9a56ac8 Mon Sep 17 00:00:00 2001
+From: Jani Nikula <jani.nikula@intel.com>
+Date: Thu, 4 Feb 2016 12:50:49 +0200
+Subject: drm/i915/dsi: defend gpio table against out of bounds access
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Jani Nikula <jani.nikula@intel.com>
+
+commit 4db3a2448ec8902310acb78de39b6227a9a56ac8 upstream.
+
+Do not blindly trust the VBT data used for indexing.
+
+Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Link: http://patchwork.freedesktop.org/patch/msgid/cc32d40c2b47f2d2151811855ac2c3dabab1d57d.1454582914.git.jani.nikula@intel.com
+(cherry picked from commit 5d2d0a12d3d08bf50434f0b5947bb73bac04b941)
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
++++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+@@ -209,6 +209,11 @@ static const u8 *mipi_exec_gpio(struct i
+ /* pull up/down */
+ action = *data++;
+
++ if (gpio >= ARRAY_SIZE(gtable)) {
++ DRM_DEBUG_KMS("unknown gpio %u\n", gpio);
++ goto out;
++ }
++
+ function = gtable[gpio].function_reg;
+ pad = gtable[gpio].pad_reg;
+
+@@ -226,6 +231,7 @@ static const u8 *mipi_exec_gpio(struct i
+ vlv_gpio_nc_write(dev_priv, pad, val);
+ mutex_unlock(&dev_priv->sb_lock);
+
++out:
+ return data;
+ }
+
--- /dev/null
+From 26f6f2d301c1fb46acb1138ee155125815239b0d Mon Sep 17 00:00:00 2001
+From: Jani Nikula <jani.nikula@intel.com>
+Date: Thu, 4 Feb 2016 12:50:50 +0200
+Subject: drm/i915/dsi: don't pass arbitrary data to sideband
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Jani Nikula <jani.nikula@intel.com>
+
+commit 26f6f2d301c1fb46acb1138ee155125815239b0d upstream.
+
+Since sequence block v2 the second byte contains flags other than just
+pull up/down. Don't pass arbitrary data to the sideband interface.
+
+The rest may or may not work for sequence block v2, but there should be
+no harm done.
+
+Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Link: http://patchwork.freedesktop.org/patch/msgid/ebe3c2eee623afc4b3a134533b01f8d591d13f32.1454582914.git.jani.nikula@intel.com
+(cherry picked from commit 4e1c63e3761b84ec7d87c75b58bbc8bcf18e98ee)
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
++++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+@@ -207,7 +207,7 @@ static const u8 *mipi_exec_gpio(struct i
+ gpio = *data++;
+
+ /* pull up/down */
+- action = *data++;
++ action = *data++ & 1;
+
+ if (gpio >= ARRAY_SIZE(gtable)) {
+ DRM_DEBUG_KMS("unknown gpio %u\n", gpio);
--- /dev/null
+From ed3f9fd1e865975ceefdb2a43b453e090b1fd787 Mon Sep 17 00:00:00 2001
+From: Rasmus Villemoes <linux@rasmusvillemoes.dk>
+Date: Tue, 9 Feb 2016 21:11:13 +0100
+Subject: drm/i915: fix error path in intel_setup_gmbus()
+
+From: Rasmus Villemoes <linux@rasmusvillemoes.dk>
+
+commit ed3f9fd1e865975ceefdb2a43b453e090b1fd787 upstream.
+
+This fails to undo the setup for pin==0; moreover, something
+interesting happens if the setup failed already at pin==0.
+
+Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
+Fixes: f899fc64cda8 ("drm/i915: use GMBUS to manage i2c links")
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Link: http://patchwork.freedesktop.org/patch/msgid/1455048677-19882-3-git-send-email-linux@rasmusvillemoes.dk
+(cherry picked from commit 2417c8c03f508841b85bf61acc91836b7b0e2560)
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/intel_i2c.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/intel_i2c.c
++++ b/drivers/gpu/drm/i915/intel_i2c.c
+@@ -675,7 +675,7 @@ int intel_setup_gmbus(struct drm_device
+ return 0;
+
+ err:
+- while (--pin) {
++ while (pin--) {
+ if (!intel_gmbus_is_valid_pin(dev_priv, pin))
+ continue;
+
--- /dev/null
+From f5949141a21ee16edf1beaf95cbae7e419171ab5 Mon Sep 17 00:00:00 2001
+From: Daniel Vetter <daniel.vetter@ffwll.ch>
+Date: Wed, 13 Jan 2016 11:55:28 +0100
+Subject: drm/i915: Init power domains early in driver load
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Daniel Vetter <daniel.vetter@ffwll.ch>
+
+commit f5949141a21ee16edf1beaf95cbae7e419171ab5 upstream.
+
+Since
+
+commit ac9b8236551d1177fd07b56aef9b565d1864420d
+Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Date: Fri Nov 27 18:55:26 2015 +0200
+
+ drm/i915: Introduce a gmbus power domain
+
+gmbus also needs the power domain infrastructure right from the start,
+since as soon as we register the i2c controllers someone can use them.
+
+v2: Adjust cleanup paths too (Chris).
+
+v3: Rebase onto -nightly (totally bogus tree I had lying around) and
+also move dpio init head (Ville).
+
+v4: Ville instead suggested to move gmbus setup later in the sequence,
+since it's only needed by the modeset code.
+
+v5: Move even close to the actual user, right next to the comment that
+states where we really need gmbus (and interrupts!).
+
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Cc: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
+Cc: Imre Deak <imre.deak@intel.com>
+Cc: Jani Nikula <jani.nikula@intel.com>
+Cc: Meelis Roos <mroos@linux.ee>
+Cc: Chris Wilson <chris@chris-wilson.co.uk>
+Fixes: ac9b8236551d ("drm/i915: Introduce a gmbus power domain")
+References: http://www.spinics.net/lists/intel-gfx/msg83075.html
+Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
+Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: http://patchwork.freedesktop.org/patch/msgid/1452682528-19437-1-git-send-email-daniel.vetter@ffwll.ch
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/i915_dma.c | 6 +++---
+ drivers/gpu/drm/i915/intel_display.c | 2 ++
+ 2 files changed, 5 insertions(+), 3 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_dma.c
++++ b/drivers/gpu/drm/i915/i915_dma.c
+@@ -402,6 +402,8 @@ static int i915_load_modeset_init(struct
+ if (ret)
+ goto cleanup_gem_stolen;
+
++ intel_setup_gmbus(dev);
++
+ /* Important: The output setup functions called by modeset_init need
+ * working irqs for e.g. gmbus and dp aux transfers. */
+ intel_modeset_init(dev);
+@@ -451,6 +453,7 @@ cleanup_gem:
+ cleanup_irq:
+ intel_guc_ucode_fini(dev);
+ drm_irq_uninstall(dev);
++ intel_teardown_gmbus(dev);
+ cleanup_gem_stolen:
+ i915_gem_cleanup_stolen(dev);
+ cleanup_vga_switcheroo:
+@@ -1028,7 +1031,6 @@ int i915_driver_load(struct drm_device *
+
+ /* Try to make sure MCHBAR is enabled before poking at it */
+ intel_setup_mchbar(dev);
+- intel_setup_gmbus(dev);
+ intel_opregion_setup(dev);
+
+ i915_gem_load(dev);
+@@ -1099,7 +1101,6 @@ out_gem_unload:
+ if (dev->pdev->msi_enabled)
+ pci_disable_msi(dev->pdev);
+
+- intel_teardown_gmbus(dev);
+ intel_teardown_mchbar(dev);
+ pm_qos_remove_request(&dev_priv->pm_qos);
+ destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
+@@ -1198,7 +1199,6 @@ int i915_driver_unload(struct drm_device
+
+ intel_csr_ucode_fini(dev);
+
+- intel_teardown_gmbus(dev);
+ intel_teardown_mchbar(dev);
+
+ destroy_workqueue(dev_priv->hotplug.dp_wq);
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -15565,6 +15565,8 @@ void intel_modeset_cleanup(struct drm_de
+ mutex_lock(&dev->struct_mutex);
+ intel_cleanup_gt_powersave(dev);
+ mutex_unlock(&dev->struct_mutex);
++
++ intel_teardown_gmbus(dev);
+ }
+
+ /*
--- /dev/null
+From 2dc2f761dea65069485110d24eaa5b0d5d808b07 Mon Sep 17 00:00:00 2001
+From: Lyude <cpaul@redhat.com>
+Date: Thu, 7 Jan 2016 10:43:28 -0500
+Subject: drm/i915: intel_hpd_init(): Fix suspend/resume reprobing
+
+From: Lyude <cpaul@redhat.com>
+
+commit 2dc2f761dea65069485110d24eaa5b0d5d808b07 upstream.
+
+This fixes reprobing of display connectors on resume. After some
+talking with danvet on IRC, I learned that calling
+drm_helper_hpd_irq_event() does actually trigger a full reprobe of each
+connector's status. It turns out this is the actual reason reprobing on
+resume hasn't been working (this was observed on a T440s):
+
+ - We call hpd_init()
+ - We check each connector for a couple of things before marking
+ connector->polled with DRM_CONNECTOR_POLL_HPD, one of which is an
+ active encoder. Of course, a disconnected port won't have an
+ active encoder, so we don't add the flag to any of the
+ connectors.
+ - We call drm_helper_hpd_irq_event()
+ - drm_helper_irq_event() checks each connector for the
+ DRM_CONNECTOR_POLL_HPD flag. The only one that has it is eDP-1,
+ so we skip reprobing each connector except that one.
+
+In addition, we also now avoid setting connector->polled to
+DRM_CONNECTOR_POLL_HPD for MST connectors, since their reprobing is
+handled by the mst helpers. This is probably what was originally
+intended to happen here.
+
+Changes since V1:
+* Use the explanation of the issue as the commit message instead
+* Change the title of the commit, since this does more then just stop a
+ check for an encoder now
+* Add "Fixes" line for the patch that introduced this regression
+* Don't enable DRM_CONNECTOR_POLL_HPD for mst connectors
+
+Changes since V2:
+* Put patch changelog above Signed-off-by
+* Follow Daniel Vetter's suggestion for making the code here a bit more
+ legible
+
+Fixes: 0e32b39ceed6 ("drm/i915: add DP 1.2 MST support (v0.7)")
+Signed-off-by: Lyude <cpaul@redhat.com>
+Link: http://patchwork.freedesktop.org/patch/msgid/1452181408-14777-1-git-send-email-cpaul@redhat.com
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+(cherry picked from commit 07c519134417d92c2e1a536e2b66d4ffff4b3be0)
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/intel_hotplug.c | 9 +++++++--
+ 1 file changed, 7 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/i915/intel_hotplug.c
++++ b/drivers/gpu/drm/i915/intel_hotplug.c
+@@ -468,9 +468,14 @@ void intel_hpd_init(struct drm_i915_priv
+ list_for_each_entry(connector, &mode_config->connector_list, head) {
+ struct intel_connector *intel_connector = to_intel_connector(connector);
+ connector->polled = intel_connector->polled;
+- if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
+- connector->polled = DRM_CONNECTOR_POLL_HPD;
++
++ /* MST has a dynamic intel_connector->encoder and it's reprobing
++ * is all handled by the MST helpers. */
+ if (intel_connector->mst_port)
++ continue;
++
++ if (!connector->polled && I915_HAS_HOTPLUG(dev) &&
++ intel_connector->encoder->hpd_pin > HPD_NONE)
+ connector->polled = DRM_CONNECTOR_POLL_HPD;
+ }
+
--- /dev/null
+From 935a0ff0e1ea62a116848c0a187b13838f7b9cee Mon Sep 17 00:00:00 2001
+From: Francisco Jerez <currojerez@riseup.net>
+Date: Wed, 13 Jan 2016 18:59:39 -0800
+Subject: drm/i915: Make sure DC writes are coherent on flush.
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Francisco Jerez <currojerez@riseup.net>
+
+commit 935a0ff0e1ea62a116848c0a187b13838f7b9cee upstream.
+
+We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee
+that writes performed via the HDC are visible in memory. Fixes an
+intermittent failure in a Piglit test that writes to a BO from a
+shader using GL atomic counters (implemented as HDC untyped atomics)
+and then expects the memory to read back the same value after mapping
+it on the CPU.
+
+Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91298
+Tested-by: Mark Janes <mark.a.janes@intel.com>
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Francisco Jerez <currojerez@riseup.net>
+Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: http://patchwork.freedesktop.org/patch/msgid/1452740379-3194-1-git-send-email-currojerez@riseup.net
+(cherry picked from commit 965fd602a6436f689f4f2fe40a6789582778ccd5)
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/intel_lrc.c | 1 +
+ drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
+ 2 files changed, 3 insertions(+)
+
+--- a/drivers/gpu/drm/i915/intel_lrc.c
++++ b/drivers/gpu/drm/i915/intel_lrc.c
+@@ -1706,6 +1706,7 @@ static int gen8_emit_flush_render(struct
+ if (flush_domains) {
+ flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
+ flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
++ flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
+ flags |= PIPE_CONTROL_FLUSH_ENABLE;
+ }
+
+--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
++++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
+@@ -347,6 +347,7 @@ gen7_render_ring_flush(struct drm_i915_g
+ if (flush_domains) {
+ flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
+ flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
++ flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
+ flags |= PIPE_CONTROL_FLUSH_ENABLE;
+ }
+ if (invalidate_domains) {
+@@ -419,6 +420,7 @@ gen8_render_ring_flush(struct drm_i915_g
+ if (flush_domains) {
+ flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
+ flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
++ flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
+ flags |= PIPE_CONTROL_FLUSH_ENABLE;
+ }
+ if (invalidate_domains) {
--- /dev/null
+From 06ef83a705a98da63797a5a570220b6ca36febd4 Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Fri, 27 Nov 2015 13:28:55 +0000
+Subject: drm/i915: Restore inhibiting the load of the default context
+
+From: Chris Wilson <chris@chris-wilson.co.uk>
+
+commit 06ef83a705a98da63797a5a570220b6ca36febd4 upstream.
+
+Following a GPU reset, we may leave the context in a poorly defined
+state, and reloading from that context will leave the GPU flummoxed. For
+secondary contexts, this will lead to that context being banned - but
+currently it is also causing the default context to become banned,
+leading to turmoil in the shared state.
+
+This is a regression from
+
+commit 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b [v4.1]
+Author: Ben Widawsky <benjamin.widawsky@intel.com>
+Date: Mon Mar 16 16:00:58 2015 +0000
+
+ drm/i915: Initialize all contexts
+
+which quietly introduced the removal of the MI_RESTORE_INHIBIT on the
+default context.
+
+v2: Mark the global default context as uninitialized on GPU reset so
+that the context-local workarounds are reloaded upon re-enabling.
+
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Michel Thierry <michel.thierry@intel.com>
+Cc: Mika Kuoppala <mika.kuoppala@intel.com>
+Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
+Link: http://patchwork.freedesktop.org/patch/msgid/1448630935-27377-1-git-send-email-chris@chris-wilson.co.uk
+Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
+[danvet: This seems to fix a gpu hand on after the first resume,
+resulting in any future suspend operation failing with -EIO because
+the gpu seems to be in a funky state. Somehow this patch fixes that.]
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+(cherry picked from commit 42f1cae8c079bcceb3cff079fddc3ff8852c788f)
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/i915_gem_context.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/i915_gem_context.c
++++ b/drivers/gpu/drm/i915/i915_gem_context.c
+@@ -340,6 +340,10 @@ void i915_gem_context_reset(struct drm_d
+ i915_gem_context_unreference(lctx);
+ ring->last_context = NULL;
+ }
++
++ /* Force the GPU state to be reinitialised on enabling */
++ if (ring->default_context)
++ ring->default_context->legacy_hw_ctx.initialized = false;
+ }
+ }
+
+@@ -708,7 +712,7 @@ static int do_switch(struct drm_i915_gem
+ if (ret)
+ goto unpin_out;
+
+- if (!to->legacy_hw_ctx.initialized) {
++ if (!to->legacy_hw_ctx.initialized || i915_gem_context_is_default(to)) {
+ hw_flags |= MI_RESTORE_INHIBIT;
+ /* NB: If we inhibit the restore, the context is not allowed to
+ * die because future work may end up depending on valid address
--- /dev/null
+From 3d849b02336be103d312c1574d6f7314d5c0bc9f Mon Sep 17 00:00:00 2001
+From: Lyude <cpaul@redhat.com>
+Date: Tue, 2 Feb 2016 10:49:43 -0500
+Subject: drm/i915/skl: Don't skip mst encoders in skl_ddi_pll_select()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Lyude <cpaul@redhat.com>
+
+commit 3d849b02336be103d312c1574d6f7314d5c0bc9f upstream.
+
+We don't actually check for INTEL_OUTPUT_DP_MST at all in here, as a
+result we skip assigning a DPLL to any DP MST ports, which makes link
+training fail:
+
+[ 1442.933896] [drm:intel_power_well_enable] enabling DDI D power well
+[ 1442.933905] [drm:skl_set_power_well] Enabling DDI D power well
+[ 1442.933957] [drm:intel_mst_pre_enable_dp] 0
+[ 1442.935474] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
+[ 1442.935477] [drm:intel_dp_set_signal_levels] Using vswing level 0
+[ 1442.935480] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
+[ 1442.936190] [drm:intel_dp_set_signal_levels] Using signal levels 05000000
+[ 1442.936193] [drm:intel_dp_set_signal_levels] Using vswing level 1
+[ 1442.936195] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
+[ 1442.936858] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
+[ 1442.936862] [drm:intel_dp_set_signal_levels] Using vswing level 2
+…
+[ 1442.998253] [drm:intel_dp_link_training_clock_recovery [i915]] *ERROR* too many full retries, give up
+[ 1442.998512] [drm:intel_dp_start_link_train [i915]] *ERROR* failed to train DP, aborting
+
+After which the pipe state goes completely out of sync:
+
+[ 70.075596] [drm:check_crtc_state] [CRTC:25]
+[ 70.075696] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in ddi_pll_sel (expected 0x00000000, found 0x00000001)
+[ 70.075747] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in shared_dpll (expected -1, found 0)
+[ 70.075798] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.ctrl1 (expected 0x00000000, found 0x00000021)
+[ 70.075840] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.cfgcr1 (expected 0x00000000, found 0x80400173)
+[ 70.075884] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.cfgcr2 (expected 0x00000000, found 0x000003a5)
+[ 70.075954] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 262750, found 72256)
+[ 70.075999] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in port_clock (expected 540000, found 148500)
+
+And if you're especially lucky, it keeps going downhill:
+
+[ 83.309256] Kernel panic - not syncing: Timeout: Not all CPUs entered broadcast exception handler
+[ 83.309265]
+[ 83.309265] =================================
+[ 83.309266] [ INFO: inconsistent lock state ]
+[ 83.309267] 4.5.0-rc1Lyude-Test #265 Not tainted
+[ 83.309267] ---------------------------------
+[ 83.309268] inconsistent {IN-HARDIRQ-W} -> {HARDIRQ-ON-W} usage.
+[ 83.309270] Xorg/1194 [HC0[1]:SC0[0]:HE1:SE1] takes:
+[ 83.309293] (&(&dev_priv->uncore.lock)->rlock){?.-...}, at: [<ffffffffa02a6073>] gen9_write32+0x63/0x400 [i915]
+[ 83.309293] {IN-HARDIRQ-W} state was registered at:
+[ 83.309297] [<ffffffff810e84f4>] __lock_acquire+0x9c4/0x1d00
+[ 83.309299] [<ffffffff810ea1be>] lock_acquire+0xce/0x1c0
+[ 83.309302] [<ffffffff8177d936>] _raw_spin_lock_irqsave+0x56/0x90
+[ 83.309321] [<ffffffffa02a5492>] gen9_read32+0x52/0x3d0 [i915]
+[ 83.309332] [<ffffffffa024beea>] gen8_irq_handler+0x27a/0x6a0 [i915]
+[ 83.309337] [<ffffffff810fdbc1>] handle_irq_event_percpu+0x41/0x300
+[ 83.309339] [<ffffffff810fdeb9>] handle_irq_event+0x39/0x60
+[ 83.309341] [<ffffffff811010b4>] handle_edge_irq+0x74/0x130
+[ 83.309344] [<ffffffff81009073>] handle_irq+0x73/0x120
+[ 83.309346] [<ffffffff817805f1>] do_IRQ+0x61/0x120
+[ 83.309348] [<ffffffff8177e6d6>] ret_from_intr+0x0/0x20
+[ 83.309351] [<ffffffff815f5105>] cpuidle_enter_state+0x105/0x330
+[ 83.309353] [<ffffffff815f5367>] cpuidle_enter+0x17/0x20
+[ 83.309356] [<ffffffff810dbe1a>] call_cpuidle+0x2a/0x50
+[ 83.309358] [<ffffffff810dc1dd>] cpu_startup_entry+0x26d/0x3a0
+[ 83.309360] [<ffffffff817701da>] rest_init+0x13a/0x140
+[ 83.309363] [<ffffffff81f2af8e>] start_kernel+0x475/0x482
+[ 83.309365] [<ffffffff81f2a315>] x86_64_start_reservations+0x2a/0x2c
+[ 83.309367] [<ffffffff81f2a452>] x86_64_start_kernel+0x13b/0x14a
+
+Fixes: 82d354370189 ("drm/i915/skl: Implementation of SKL DPLL programming")
+Signed-off-by: Lyude <cpaul@redhat.com>
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Link: http://patchwork.freedesktop.org/patch/msgid/1454428183-994-1-git-send-email-cpaul@redhat.com
+(cherry picked from commit 78385cb398748debb7ea2e36d6d2001830c172bc)
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/intel_ddi.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/intel_ddi.c
++++ b/drivers/gpu/drm/i915/intel_ddi.c
+@@ -1582,7 +1582,8 @@ skl_ddi_pll_select(struct intel_crtc *in
+ DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
+ DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
+ wrpll_params.central_freq;
+- } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
++ } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
++ intel_encoder->type == INTEL_OUTPUT_DP_MST) {
+ switch (crtc_state->port_clock / 2) {
+ case 81000:
+ ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
drm-radeon-mask-out-wc-from-bo-on-unsupported-arches.patch
drm-radeon-hold-reference-to-fences-in-radeon_sa_bo_new.patch
drm-fix-missing-reference-counting-decrease.patch
+drm-i915-restore-inhibiting-the-load-of-the-default-context.patch
+drm-i915-intel_hpd_init-fix-suspend-resume-reprobing.patch
+drm-i915-init-power-domains-early-in-driver-load.patch
+drm-i915-make-sure-dc-writes-are-coherent-on-flush.patch
+drm-i915-dp-fall-back-to-18-bpp-when-sink-capability-is-unknown.patch
+drm-i915-don-t-reject-primary-plane-windowing-with-color-keying-enabled-on-skl.patch
+drm-i915-skl-don-t-skip-mst-encoders-in-skl_ddi_pll_select.patch
+drm-i915-dsi-defend-gpio-table-against-out-of-bounds-access.patch
+drm-i915-dsi-don-t-pass-arbitrary-data-to-sideband.patch
+drm-i915-fix-error-path-in-intel_setup_gmbus.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
