mips-cpus.def (octeon+): New CPU.

2011-12-08  Andrew Pinski  <apinski@cavium.com>

	* config/mips/mips-cpus.def (octeon+): New CPU.
	* config/mips/mips-tables.opt: Regenerate.
	* config/mips/mips.h (MIPS_CPP_SET_PROCESSOR): Emit '+' as 'P'.

2011-12-08  Andrew Pinski  <apinski@cavium.com>

	* cc.target/mips/mult-1.c: Forbid all Octeon processors.
	* gcc.target/mips/dmult-1.c: Likewise.
	* gcc.target/mips/branch-1.c: Likewise.
	* gcc.target/mips/extend-1.c: Likewise.

From-SVN: r182152

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e6e29e53a4f011aa9d160b5155f8804e87cadf29..43027e0c351ea5cd9e4e047cc384804640d992cb 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2011-12-08  Andrew Pinski  <apinski@cavium.com>
+
+       * config/mips/mips-cpus.def (octeon+): New CPU.
+       * config/mips/mips-tables.opt: Regenerate.
+       * config/mips/mips.h (MIPS_CPP_SET_PROCESSOR): Emit '+' as 'P'.
+
 2011-12-08  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
 
        PR middle-end/39976

diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def
index 35fd51691670296bc29c77da65d146ac7c6e9c5b..39f46ab4bbe89995322b24c977de184c1c18a08c 100644 (file)
--- a/gcc/config/mips/mips-cpus.def
+++ b/gcc/config/mips/mips-cpus.def
@@ -145,3 +145,4 @@ MIPS_CPU ("loongson3a", PROCESSOR_LOONGSON_3A, 64, PTF_AVOID_BRANCHLIKELY)
 
 /* MIPS64 Release 2 processors.  */
 MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY)
+MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY)

diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt
index 4e410f0f010ed555152499d524224210e496049a..bd885261690604d6ef64190269ead4810a3b78f6 100644 (file)
--- a/gcc/config/mips/mips-tables.opt
+++ b/gcc/config/mips/mips-tables.opt
@@ -603,3 +603,6 @@ Enum(mips_arch_opt_value) String(loongson3a) Value(79) Canonical
 EnumValue
 Enum(mips_arch_opt_value) String(octeon) Value(80) Canonical
 
+EnumValue
+Enum(mips_arch_opt_value) String(octeon+) Value(81) Canonical
+

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 236afbb4a34cfd3e3f02020e0012c06a94f93c53..ee40cfabc9a5d9b7c570f6327efdc2f189c648d8 100644 (file)
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -329,7 +329,10 @@ struct mips_cpu_info {
                                                                \
       macro = concat ((PREFIX), "_", (INFO)->name, NULL);      \
       for (p = macro; *p != 0; p++)                            \
-       *p = TOUPPER (*p);                                      \
+        if (*p == '+')                                          \
+          *p = 'P';                                             \
+        else                                                    \
+          *p = TOUPPER (*p);                                    \
                                                                \
       builtin_define (macro);                                  \
       builtin_define_with_value ((PREFIX), (INFO)->name, 1);   \

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 9d4f286418eb8302ae9596b9eb0f590d374a113b..8ad5ffec9c8818b76126a26b89e57fd79a56730b 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2011-12-08  Andrew Pinski  <apinski@cavium.com>
+
+       * cc.target/mips/mult-1.c: Forbid all Octeon processors.
+       * gcc.target/mips/dmult-1.c: Likewise.
+       * gcc.target/mips/branch-1.c: Likewise.
+       * gcc.target/mips/extend-1.c: Likewise.
+
 2011-12-08  Jason Merrill  <jason@redhat.com>
 
        PR c++/51318

diff --git a/gcc/testsuite/gcc.target/mips/branch-1.c b/gcc/testsuite/gcc.target/mips/branch-1.c
index 62d6bbb619a46fb56da8e849919b01c40b6e2aa1..2f4510f8dd67d79f9ea1c37c3c663d33626e17fb 100644 (file)
--- a/gcc/testsuite/gcc.target/mips/branch-1.c
+++ b/gcc/testsuite/gcc.target/mips/branch-1.c
@@ -2,7 +2,7 @@
    but we test for "bbit" elsewhere.  On other targets, we should implement
    the "if" statements using an "andi" instruction followed by a branch
    on zero.  */
-/* { dg-options "-O2 forbid_cpu=octeon" } */
+/* { dg-options "-O2 forbid_cpu=octeon.*" } */
 
 void bar (void);
 NOMIPS16 void f1 (int x) { if (x & 4) bar (); }

diff --git a/gcc/testsuite/gcc.target/mips/dmult-1.c b/gcc/testsuite/gcc.target/mips/dmult-1.c
index 517e43ed54b1bb8a5ae7130db160a9eff22642f4..f8c0b8b44f101961a902e748dec73ef0de5017f9 100644 (file)
--- a/gcc/testsuite/gcc.target/mips/dmult-1.c
+++ b/gcc/testsuite/gcc.target/mips/dmult-1.c
@@ -1,4 +1,4 @@
-/* { dg-options "forbid_cpu=octeon -mgp64" } */
+/* { dg-options "forbid_cpu=octeon.* -mgp64" } */
 /* { dg-final { scan-assembler "\tdmult\t" } } */
 /* { dg-final { scan-assembler "\tmflo\t" } } */
 /* { dg-final { scan-assembler-not "\tdmul\t" } } */

diff --git a/gcc/testsuite/gcc.target/mips/extend-1.c b/gcc/testsuite/gcc.target/mips/extend-1.c
index 4295106866b550f65b376b79ac497d9714a65d15..5e9389060c8c29b0fa0c31dda175046bfc3eb3cf 100644 (file)
--- a/gcc/testsuite/gcc.target/mips/extend-1.c
+++ b/gcc/testsuite/gcc.target/mips/extend-1.c
@@ -1,4 +1,4 @@
-/* { dg-options "-O -mgp64 forbid_cpu=octeon" } */
+/* { dg-options "-O -mgp64 forbid_cpu=octeon.*" } */
 /* { dg-final { scan-assembler-times "\tdsll\t" 5 } } */
 /* { dg-final { scan-assembler-times "\tdsra\t" 5 } } */
 /* { dg-final { scan-assembler-not "\tsll\t" } } */

diff --git a/gcc/testsuite/gcc.target/mips/mult-1.c b/gcc/testsuite/gcc.target/mips/mult-1.c
index 43dd08c0b52177f024d5a856a13bb901fe0174a3..96961b0d85ce3fc6bed8baa6d861a5e1b0f80485 100644 (file)
--- a/gcc/testsuite/gcc.target/mips/mult-1.c
+++ b/gcc/testsuite/gcc.target/mips/mult-1.c
@@ -1,6 +1,6 @@
 /* For SI->DI widening multiplication we should use DINS to combine the two
    halves.  For Octeon use DMUL with explicit widening.  */
-/* { dg-options "-O -mgp64 isa_rev>=2 forbid_cpu=octeon" } */
+/* { dg-options "-O -mgp64 isa_rev>=2 forbid_cpu=octeon.*" } */
 /* { dg-final { scan-assembler "\tdins\t" } } */
 /* { dg-final { scan-assembler-not "\tdsll\t" } } */
 /* { dg-final { scan-assembler-not "\tdsrl\t" } } */