--- /dev/null
+From f8b64d08dde2714c62751d18ba77f4aeceb161d3 Mon Sep 17 00:00:00 2001
+From: Borislav Petkov <bpetkov@suse.de>
+Date: Fri, 27 Apr 2018 16:34:34 -0500
+Subject: x86/CPU/AMD: Have smp_num_siblings and cpu_llc_id always be present
+
+From: Borislav Petkov <bpetkov@suse.de>
+
+commit f8b64d08dde2714c62751d18ba77f4aeceb161d3 upstream.
+
+Move smp_num_siblings and cpu_llc_id to cpu/common.c so that they're
+always present as symbols and not only in the CONFIG_SMP case. Then,
+other code using them doesn't need ugly ifdeffery anymore. Get rid of
+some ifdeffery.
+
+Signed-off-by: Borislav Petkov <bpetkov@suse.de>
+Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Link: http://lkml.kernel.org/r/1524864877-111962-2-git-send-email-suravee.suthikulpanit@amd.com
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/x86/include/asm/smp.h | 1 -
+ arch/x86/kernel/cpu/amd.c | 11 +----------
+ arch/x86/kernel/cpu/common.c | 7 +++++++
+ arch/x86/kernel/smpboot.c | 7 -------
+ 4 files changed, 8 insertions(+), 18 deletions(-)
+
+--- a/arch/x86/include/asm/smp.h
++++ b/arch/x86/include/asm/smp.h
+@@ -156,7 +156,6 @@ static inline int wbinvd_on_all_cpus(voi
+ wbinvd();
+ return 0;
+ }
+-#define smp_num_siblings 1
+ #endif /* CONFIG_SMP */
+
+ extern unsigned disabled_cpus;
+--- a/arch/x86/kernel/cpu/amd.c
++++ b/arch/x86/kernel/cpu/amd.c
+@@ -296,8 +296,6 @@ static int nearby_node(int apicid)
+ }
+ #endif
+
+-#ifdef CONFIG_SMP
+-
+ static void amd_get_topology_early(struct cpuinfo_x86 *c)
+ {
+ if (cpu_has(c, X86_FEATURE_TOPOEXT))
+@@ -380,7 +378,6 @@ static void amd_get_topology(struct cpui
+ legacy_fixup_core_id(c);
+ }
+ }
+-#endif
+
+ /*
+ * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
+@@ -388,7 +385,6 @@ static void amd_get_topology(struct cpui
+ */
+ static void amd_detect_cmp(struct cpuinfo_x86 *c)
+ {
+-#ifdef CONFIG_SMP
+ unsigned bits;
+ int cpu = smp_processor_id();
+
+@@ -400,16 +396,11 @@ static void amd_detect_cmp(struct cpuinf
+ /* use socket ID also for last level cache */
+ per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
+ amd_get_topology(c);
+-#endif
+ }
+
+ u16 amd_get_nb_id(int cpu)
+ {
+- u16 id = 0;
+-#ifdef CONFIG_SMP
+- id = per_cpu(cpu_llc_id, cpu);
+-#endif
+- return id;
++ return per_cpu(cpu_llc_id, cpu);
+ }
+ EXPORT_SYMBOL_GPL(amd_get_nb_id);
+
+--- a/arch/x86/kernel/cpu/common.c
++++ b/arch/x86/kernel/cpu/common.c
+@@ -61,6 +61,13 @@ cpumask_var_t cpu_callin_mask;
+ /* representing cpus for which sibling maps can be computed */
+ cpumask_var_t cpu_sibling_setup_mask;
+
++/* Number of siblings per CPU package */
++int smp_num_siblings = 1;
++EXPORT_SYMBOL(smp_num_siblings);
++
++/* Last level cache ID of each logical CPU */
++DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
++
+ /* correctly size the local cpu masks */
+ void __init setup_cpu_local_masks(void)
+ {
+--- a/arch/x86/kernel/smpboot.c
++++ b/arch/x86/kernel/smpboot.c
+@@ -78,13 +78,6 @@
+ #include <asm/spec-ctrl.h>
+ #include <asm/hw_irq.h>
+
+-/* Number of siblings per CPU package */
+-int smp_num_siblings = 1;
+-EXPORT_SYMBOL(smp_num_siblings);
+-
+-/* Last level cache ID of each logical CPU */
+-DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
+-
+ /* representing HT siblings of each logical CPU */
+ DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
+ EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
--- /dev/null
+From b89b41d0b8414690ec0030c134b8bde209e6d06c Mon Sep 17 00:00:00 2001
+From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
+Date: Mon, 31 Jul 2017 10:51:58 +0200
+Subject: x86/cpu/amd: Limit cpu_core_id fixup to families older than F17h
+
+From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
+
+commit b89b41d0b8414690ec0030c134b8bde209e6d06c upstream.
+
+Current cpu_core_id fixup causes downcored F17h configurations to be
+incorrect:
+
+ NODE: 0
+ processor 0 core id : 0
+ processor 1 core id : 1
+ processor 2 core id : 2
+ processor 3 core id : 4
+ processor 4 core id : 5
+ processor 5 core id : 0
+
+ NODE: 1
+ processor 6 core id : 2
+ processor 7 core id : 3
+ processor 8 core id : 4
+ processor 9 core id : 0
+ processor 10 core id : 1
+ processor 11 core id : 2
+
+Code that relies on the cpu_core_id, like match_smt(), for example,
+which builds the thread siblings masks used by the scheduler, is
+mislead.
+
+So, limit the fixup to pre-F17h machines. The new value for cpu_core_id
+for F17h and later will represent the CPUID_Fn8000001E_EBX[CoreId],
+which is guaranteed to be unique for each core within a socket.
+
+This way we have:
+
+ NODE: 0
+ processor 0 core id : 0
+ processor 1 core id : 1
+ processor 2 core id : 2
+ processor 3 core id : 4
+ processor 4 core id : 5
+ processor 5 core id : 6
+
+ NODE: 1
+ processor 6 core id : 8
+ processor 7 core id : 9
+ processor 8 core id : 10
+ processor 9 core id : 12
+ processor 10 core id : 13
+ processor 11 core id : 14
+
+Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
+[ Heavily massaged. ]
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: Linus Torvalds <torvalds@linux-foundation.org>
+Cc: Peter Zijlstra <peterz@infradead.org>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: Yazen Ghannam <Yazen.Ghannam@amd.com>
+Link: http://lkml.kernel.org/r/20170731085159.9455-2-bp@alien8.de
+Signed-off-by: Ingo Molnar <mingo@kernel.org>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/x86/kernel/cpu/amd.c | 24 +++++++++++++++++-------
+ 1 file changed, 17 insertions(+), 7 deletions(-)
+
+--- a/arch/x86/kernel/cpu/amd.c
++++ b/arch/x86/kernel/cpu/amd.c
+@@ -305,6 +305,22 @@ static void amd_get_topology_early(struc
+ }
+
+ /*
++ * Fix up cpu_core_id for pre-F17h systems to be in the
++ * [0 .. cores_per_node - 1] range. Not really needed but
++ * kept so as not to break existing setups.
++ */
++static void legacy_fixup_core_id(struct cpuinfo_x86 *c)
++{
++ u32 cus_per_node;
++
++ if (c->x86 >= 0x17)
++ return;
++
++ cus_per_node = c->x86_max_cores / nodes_per_socket;
++ c->cpu_core_id %= cus_per_node;
++}
++
++/*
+ * Fixup core topology information for
+ * (1) AMD multi-node processors
+ * Assumption: Number of cores in each internal node is the same.
+@@ -359,15 +375,9 @@ static void amd_get_topology(struct cpui
+ } else
+ return;
+
+- /* fixup multi-node processor information */
+ if (nodes_per_socket > 1) {
+- u32 cus_per_node;
+-
+ set_cpu_cap(c, X86_FEATURE_AMD_DCM);
+- cus_per_node = c->x86_max_cores / nodes_per_socket;
+-
+- /* core id has to be in the [0 .. cores_per_node - 1] range */
+- c->cpu_core_id %= cus_per_node;
++ legacy_fixup_core_id(c);
+ }
+ }
+ #endif
projects / thirdparty / kernel / stable-queue.git / commitdiff
