RISC-V: Use vector_length_operand instead of csr_operand in vsetvl patterns

This patch replaces csr_operand by vector_length_operand in the vsetvl
patterns.  This allows future changes in the vector code (i.e. in the
vector_length_operand predicate) without affecting scalar patterns that
use the csr_operand predicate.

gcc/ChangeLog:

	* config/riscv/vector.md:
	Use vector_length_operand for vsetvl patterns.

Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index caf1b88ba5e7e96fc9b7345949324b289506450d..24f91f058eff744092ca545f46a3f4f76de5c5a6 100644 (file)
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1513,7 +1513,7 @@
 
 (define_insn "@vsetvl<mode>"
   [(set (match_operand:P 0 "register_operand" "=r")
-       (unspec:P [(match_operand:P 1 "csr_operand" "rK")
+       (unspec:P [(match_operand:P 1 "vector_length_operand" "rK")
                   (match_operand 2 "const_int_operand" "i")
                   (match_operand 3 "const_int_operand" "i")
                   (match_operand 4 "const_int_operand" "i")
@@ -1559,7 +1559,7 @@
 ;; in vsetvl instruction pattern.
 (define_insn "@vsetvl_discard_result<mode>"
   [(set (reg:SI VL_REGNUM)
-       (unspec:SI [(match_operand:P 0 "csr_operand" "rK")
+       (unspec:SI [(match_operand:P 0 "vector_length_operand" "rK")
                    (match_operand 1 "const_int_operand" "i")
                    (match_operand 2 "const_int_operand" "i")] UNSPEC_VSETVL))
    (set (reg:SI VTYPE_REGNUM)
@@ -1581,7 +1581,7 @@
 ;; such pattern can allow us gain benefits of these optimizations.
 (define_insn_and_split "@vsetvl<mode>_no_side_effects"
   [(set (match_operand:P 0 "register_operand" "=r")
-       (unspec:P [(match_operand:P 1 "csr_operand" "rK")
+       (unspec:P [(match_operand:P 1 "vector_length_operand" "rK")
                   (match_operand 2 "const_int_operand" "i")
                   (match_operand 3 "const_int_operand" "i")
                   (match_operand 4 "const_int_operand" "i")
@@ -1625,7 +1625,7 @@
   [(set (match_operand:DI 0 "register_operand")
         (sign_extend:DI
           (subreg:SI
-           (unspec:DI [(match_operand:P 1 "csr_operand")
+           (unspec:DI [(match_operand:P 1 "vector_length_operand")
                        (match_operand 2 "const_int_operand")
                        (match_operand 3 "const_int_operand")
                        (match_operand 4 "const_int_operand")