arm64: dts: socfpga: stratix10: add L2 cache info

This removes cacheinfo warnings at boot, e.g.:
cacheinfo: Unable to detect cache hierarchy for CPU 0

Signed-off-by: Beniamin Sandu <beniaminsandu@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index cbbc53c4792180d7b8ee75e7d25d79fc1caca5aa..0def0b0daaf73101362eb13e0db5901c6ade06e1 100644 (file)
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -34,6 +34,7 @@
                        compatible = "arm,cortex-a53";
                        device_type = "cpu";
                        enable-method = "psci";
+                       next-level-cache = <&l2_shared>;
                        reg = <0x0>;
                };
 
@@ -41,6 +42,7 @@
                        compatible = "arm,cortex-a53";
                        device_type = "cpu";
                        enable-method = "psci";
+                       next-level-cache = <&l2_shared>;
                        reg = <0x1>;
                };
 
@@ -48,6 +50,7 @@
                        compatible = "arm,cortex-a53";
                        device_type = "cpu";
                        enable-method = "psci";
+                       next-level-cache = <&l2_shared>;
                        reg = <0x2>;
                };
 
@@ -55,8 +58,15 @@
                        compatible = "arm,cortex-a53";
                        device_type = "cpu";
                        enable-method = "psci";
+                       next-level-cache = <&l2_shared>;
                        reg = <0x3>;
                };
+
+               l2_shared: cache {
+                       compatible = "cache";
+                       cache-level = <2>;
+                       cache-unified;
+               };
        };
 
        firmware {