arm64: dts: qcom: sm4450: Add cpufreq support

Add a description of a SM4450 cpufreq-epss controller,add references to
it from CPU nodes and make EPSS a supplyer of clocks for the CPUs.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240424101503.635364-3-quic_tengfan@quicinc.com
Link: https://lore.kernel.org/r/20240424101503.635364-4-quic_tengfan@quicinc.com
[bjorn: Squashed the two changes, and updated commit message]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
index 603c962661ccfc86551504fa7b4b59e27ab7125f..8d75c4f9731ccafccb6f0b906af5da44491312ad 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
@@ -29,6 +29,14 @@
                        clock-frequency = <32000>;
                        #clock-cells = <0>;
                };
+
+               bi_tcxo_div2: bi-tcxo-div2-clk {
+                       #clock-cells = <0>;
+                       compatible = "fixed-factor-clock";
+                       clocks = <&rpmhcc RPMH_CXO_CLK>;
+                       clock-mult = <1>;
+                       clock-div = <2>;
+               };
        };
 
        cpus {
@@ -39,10 +47,12 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a55";
                        reg = <0x0 0x0>;
+                       clocks = <&cpufreq_hw 0>;
                        enable-method = "psci";
                        next-level-cache = <&L2_0>;
                        power-domains = <&CPU_PD0>;
                        power-domain-names = "psci";
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        #cooling-cells = <2>;
 
                        L2_0: l2-cache {
@@ -63,10 +73,12 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a55";
                        reg = <0x0 0x100>;
+                       clocks = <&cpufreq_hw 0>;
                        enable-method = "psci";
                        next-level-cache = <&L2_100>;
                        power-domains = <&CPU_PD0>;
                        power-domain-names = "psci";
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        #cooling-cells = <2>;
 
                        L2_100: l2-cache {
@@ -81,10 +93,12 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a55";
                        reg = <0x0 0x200>;
+                       clocks = <&cpufreq_hw 0>;
                        enable-method = "psci";
                        next-level-cache = <&L2_200>;
                        power-domains = <&CPU_PD0>;
                        power-domain-names = "psci";
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        #cooling-cells = <2>;
 
                        L2_200: l2-cache {
@@ -99,10 +113,12 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a55";
                        reg = <0x0 0x300>;
+                       clocks = <&cpufreq_hw 0>;
                        enable-method = "psci";
                        next-level-cache = <&L2_300>;
                        power-domains = <&CPU_PD0>;
                        power-domain-names = "psci";
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        #cooling-cells = <2>;
 
                        L2_300: l2-cache {
@@ -117,10 +133,12 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a55";
                        reg = <0x0 0x400>;
+                       clocks = <&cpufreq_hw 0>;
                        enable-method = "psci";
                        next-level-cache = <&L2_400>;
                        power-domains = <&CPU_PD0>;
                        power-domain-names = "psci";
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        #cooling-cells = <2>;
 
                        L2_400: l2-cache {
@@ -135,10 +153,12 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a55";
                        reg = <0x0 0x500>;
+                       clocks = <&cpufreq_hw 0>;
                        enable-method = "psci";
                        next-level-cache = <&L2_500>;
                        power-domains = <&CPU_PD0>;
                        power-domain-names = "psci";
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        #cooling-cells = <2>;
 
                        L2_500: l2-cache {
@@ -153,10 +173,12 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a78";
                        reg = <0x0 0x600>;
+                       clocks = <&cpufreq_hw 1>;
                        enable-method = "psci";
                        next-level-cache = <&L2_600>;
                        power-domains = <&CPU_PD0>;
                        power-domain-names = "psci";
+                       qcom,freq-domain = <&cpufreq_hw 1>;
                        #cooling-cells = <2>;
 
                        L2_600: l2-cache {
@@ -171,10 +193,12 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a78";
                        reg = <0x0 0x700>;
+                       clocks = <&cpufreq_hw 1>;
                        enable-method = "psci";
                        next-level-cache = <&L2_700>;
                        power-domains = <&CPU_PD0>;
                        power-domain-names = "psci";
+                       qcom,freq-domain = <&cpufreq_hw 1>;
                        #cooling-cells = <2>;
 
                        L2_700: l2-cache {
@@ -526,6 +550,19 @@
                        };
                };
 
+               cpufreq_hw: cpufreq@17d91000 {
+                       compatible = "qcom,sm4450-cpufreq-epss", "qcom,cpufreq-epss";
+                       reg = <0 0x17d91000 0 0x1000>,
+                             <0 0x17d92000 0 0x1000>;
+                       reg-names = "freq-domain0", "freq-domain1";
+                       clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
+                       clock-names = "xo", "alternate";
+                       interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
+                       #freq-domain-cells = <1>;
+                       #clock-cells = <1>;
+               };
        };
 
        timer {