drm/xe/xe3p_lpm: Handle MCR steering

Xe3p_LPM's MCR steering has the same ranges and behavior as Xe3_LPM.
However one register range that was reserved on Xe3_LPM has now become a
unicast range (0x384200-0x38427F), so we need to stop consolidating the
adjacent MCR ranges into a single table entry in the table.  With this
change to the Xe3_LPM table, we can continue to use the same table for
both IP families.

While we're touching this table, take the opportunity to fix a
whitespace mistake and clarify that one of the other consolidated range
entries includes a reserved range.

Bspec: 76445
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://lore.kernel.org/r/20251016-xe3p-v3-6-3dd173a3097a@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
index 8fb1cae9172443afafca987d18d7bedbfd851652..e1a2b38fc2a86e03debcc395da2500b6d9fa749c 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
@@ -236,12 +236,13 @@ static const struct xe_mmio_range xe2lpm_instance0_steering_table[] = {
 };
 
 static const struct xe_mmio_range xe3lpm_instance0_steering_table[] = {
-       { 0x384000, 0x3847DF },         /* GAM, rsvd, GAM */
+       { 0x384000, 0x3841FF },         /* GAM */
+       { 0x384400, 0x3847DF },         /* GAM */
        { 0x384900, 0x384AFF },         /* GAM */
        { 0x389560, 0x3895FF },         /* MEDIAINF */
        { 0x38B600, 0x38B8FF },         /* L3BANK */
        { 0x38C800, 0x38D07F },         /* GAM, MEDIAINF */
-       { 0x38D0D0, 0x38F0FF },         /* MEDIAINF, GAM */
+       { 0x38D0D0, 0x38F0FF },         /* MEDIAINF, rsvd, GAM */
        { 0x393C00, 0x393C7F },         /* MEDIAINF */
        {},
 };