clk/qcom: apq8096: fix set rate for the uart clock

The function should return a valid rate.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by:
Link: https://lore.kernel.org/r/20250407175617.3494506-2-jorge.ramirez@oss.qualcomm.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>

diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
index c77d69128b00ad5e2d926e61f50878c7164f2e3f..bc00826a5e8540b0257788d2af05602612423f49 100644 (file)
--- a/drivers/clk/qcom/clock-apq8096.c
+++ b/drivers/clk/qcom/clock-apq8096.c
@@ -87,7 +87,8 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate)
                return clk_init_sdc(priv, rate);
                break;
        case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/
-               return clk_init_uart(priv);
+               clk_init_uart(priv);
+               return 7372800;
        default:
                return 0;
        }