drm/amd/display: Use DPM table clk setting for dml2 soc dscclk

[WHY]
Not like dppclk/dispclk, dml2 will calculate the minimum required clocks.
For dscclk, it is used for pure comparision.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
index 2061d43b92e1b99467cd68700a4f1280f5c778e3..70c39df62533e55a67f4a1f5f231bc16938d7ffa 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
@@ -590,11 +590,11 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,
                        p->out_states->state_array[i].dtbclk_mhz = max_dtbclk_mhz;
                        p->out_states->state_array[i].phyclk_mhz = max_phyclk_mhz;
 
-                       p->out_states->state_array[i].dscclk_mhz = max_dispclk_mhz / 3.0;
                        p->out_states->state_array[i].phyclk_mhz = max_phyclk_mhz;
                        p->out_states->state_array[i].dtbclk_mhz = max_dtbclk_mhz;
 
                        /* Dependent states. */
+                       p->out_states->state_array[i].dscclk_mhz = p->in_states->state_array[i].dscclk_mhz;
                        p->out_states->state_array[i].dram_speed_mts = p->in_states->state_array[i].dram_speed_mts;
                        p->out_states->state_array[i].fabricclk_mhz = p->in_states->state_array[i].fabricclk_mhz;
                        p->out_states->state_array[i].socclk_mhz = p->in_states->state_array[i].socclk_mhz;