--- /dev/null
+From 36e8164882ca6d3c41cb91e6f09a3ed236841f80 Mon Sep 17 00:00:00 2001
+From: Myron Stowe <myron.stowe@redhat.com>
+Date: Thu, 30 Oct 2014 11:54:37 -0600
+Subject: PCI: Restore detection of read-only BARs
+
+From: Myron Stowe <myron.stowe@redhat.com>
+
+commit 36e8164882ca6d3c41cb91e6f09a3ed236841f80 upstream.
+
+Commit 6ac665c63dca ("PCI: rewrite PCI BAR reading code") masked off
+low-order bits from 'l', but not from 'sz'. Both are passed to pci_size(),
+which compares 'base == maxbase' to check for read-only BARs. The masking
+of 'l' means that comparison will never be 'true', so the check for
+read-only BARs no longer works.
+
+Resolve this by also masking off the low-order bits of 'sz' before passing
+it into pci_size() as 'maxbase'. With this change, pci_size() will once
+again catch the problems that have been encountered to date:
+
+ - AGP aperture BAR of AMD-7xx host bridges: if the AGP window is
+ disabled, this BAR is read-only and read as 0x00000008 [1]
+
+ - BARs 0-4 of ALi IDE controllers can be non-zero and read-only [1]
+
+ - Intel Sandy Bridge - Thermal Management Controller [8086:0103];
+ BAR 0 returning 0xfed98004 [2]
+
+ - Intel Xeon E5 v3/Core i7 Power Control Unit [8086:2fc0];
+ Bar 0 returning 0x00001a [3]
+
+Link: [1] https://git.kernel.org/cgit/linux/kernel/git/tglx/history.git/commit/drivers/pci/probe.c?id=1307ef6621991f1c4bc3cec1b5a4ebd6fd3d66b9 ("PCI: probing read-only BARs" (pre-git))
+Link: [2] https://bugzilla.kernel.org/show_bug.cgi?id=43331
+Link: [3] https://bugzilla.kernel.org/show_bug.cgi?id=85991
+Reported-by: William Unruh <unruh@physics.ubc.ca>
+Reported-by: Martin Lucina <martin@lucina.net>
+Signed-off-by: Myron Stowe <myron.stowe@redhat.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+CC: Matthew Wilcox <willy@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/probe.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/pci/probe.c
++++ b/drivers/pci/probe.c
+@@ -210,14 +210,17 @@ int __pci_read_base(struct pci_dev *dev,
+ res->flags |= IORESOURCE_SIZEALIGN;
+ if (res->flags & IORESOURCE_IO) {
+ l &= PCI_BASE_ADDRESS_IO_MASK;
++ sz &= PCI_BASE_ADDRESS_IO_MASK;
+ mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
+ } else {
+ l &= PCI_BASE_ADDRESS_MEM_MASK;
++ sz &= PCI_BASE_ADDRESS_MEM_MASK;
+ mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
+ }
+ } else {
+ res->flags |= (l & IORESOURCE_ROM_ENABLE);
+ l &= PCI_ROM_ADDRESS_MASK;
++ sz &= PCI_ROM_ADDRESS_MASK;
+ mask = (u32)PCI_ROM_ADDRESS_MASK;
+ }
+
--- /dev/null
+From 7c5c92ed56d932b2c19c3f8aea86369509407d33 Mon Sep 17 00:00:00 2001
+From: Anton Blanchard <anton@samba.org>
+Date: Tue, 9 Dec 2014 10:58:19 +1100
+Subject: powerpc: Secondary CPUs must set cpu_callin_map after setting active and online
+
+From: Anton Blanchard <anton@samba.org>
+
+commit 7c5c92ed56d932b2c19c3f8aea86369509407d33 upstream.
+
+I have a busy ppc64le KVM box where guests sometimes hit the infamous
+"kernel BUG at kernel/smpboot.c:134!" issue during boot:
+
+ BUG_ON(td->cpu != smp_processor_id());
+
+Basically a per CPU hotplug thread scheduled on the wrong CPU. The oops
+output confirms it:
+
+ CPU: 0
+ Comm: watchdog/130
+
+The problem is that we aren't ensuring the CPU active and online bits are set
+before allowing the master to continue on. The master unparks the secondary
+CPUs kthreads and the scheduler looks for a CPU to run on. It calls
+select_task_rq and realises the suggested CPU is not in the cpus_allowed
+mask. It then ends up in select_fallback_rq, and since the active and
+online bits aren't set we choose some other CPU to run on.
+
+Signed-off-by: Anton Blanchard <anton@samba.org>
+Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/powerpc/kernel/smp.c | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+--- a/arch/powerpc/kernel/smp.c
++++ b/arch/powerpc/kernel/smp.c
+@@ -622,7 +622,6 @@ __cpuinit void start_secondary(void *unu
+ smp_store_cpu_info(cpu);
+ set_dec(tb_ticks_per_jiffy);
+ preempt_disable();
+- cpu_callin_map[cpu] = 1;
+
+ if (smp_ops->setup_cpu)
+ smp_ops->setup_cpu(cpu);
+@@ -667,6 +666,14 @@ __cpuinit void start_secondary(void *unu
+ }
+ of_node_put(l2_cache);
+
++ /*
++ * CPU must be marked active and online before we signal back to the
++ * master, because the scheduler needs to see the cpu_online and
++ * cpu_active bits set.
++ */
++ smp_wmb();
++ cpu_callin_map[cpu] = 1;
++
+ local_irq_enable();
+
+ cpu_startup_entry(CPUHP_ONLINE);