KVM: arm64: nv: Honor MDCR_EL2.HLP

Counters that fall in the hypervisor range (i.e. N >= HPMN) have a
separate control for enabling 64 bit overflow. Take it into account.

Reviewed-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20241025182354.3364124-17-oliver.upton@linux.dev
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>

diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
index 349886f03fd542abaed2da8f575da7addcf72001..1e9cdbc235a844d86482a7dd6b8a83d8319ca975 100644 (file)
--- a/arch/arm64/kvm/pmu-emul.c
+++ b/arch/arm64/kvm/pmu-emul.c
@@ -89,7 +89,11 @@ static bool kvm_pmc_is_64bit(struct kvm_pmc *pmc)
 
 static bool kvm_pmc_has_64bit_overflow(struct kvm_pmc *pmc)
 {
-       u64 val = kvm_vcpu_read_pmcr(kvm_pmc_to_vcpu(pmc));
+       struct kvm_vcpu *vcpu = kvm_pmc_to_vcpu(pmc);
+       u64 val = kvm_vcpu_read_pmcr(vcpu);
+
+       if (kvm_pmu_counter_is_hyp(vcpu, pmc->idx))
+               return __vcpu_sys_reg(vcpu, MDCR_EL2) & MDCR_EL2_HLP;
 
        return (pmc->idx < ARMV8_PMU_CYCLE_IDX && (val & ARMV8_PMU_PMCR_LP)) ||
               (pmc->idx == ARMV8_PMU_CYCLE_IDX && (val & ARMV8_PMU_PMCR_LC));