]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
RISC-V: Remove unnecessary register class.
authorMonk Chiang <monk.chiang@sifive.com>
Fri, 3 Feb 2023 04:58:51 +0000 (12:58 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Fri, 3 Feb 2023 06:57:42 +0000 (14:57 +0800)
Avoid VL_REGS, VTYPE_REGS join register allocation.

gcc/ChangeLog:

* config/riscv/riscv.h: Remove VL_REGS, VTYPE_REGS class.
* config/riscv/riscv.cc: Ditto.

gcc/config/riscv/riscv.cc
gcc/config/riscv/riscv.h

index 209d9a53e7bd7b3a0d3885be04d02a01e9e3c6ae..3b7804b7501d4ed5a0114bceb20e34381d6cd913 100644 (file)
@@ -293,7 +293,7 @@ const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = {
   FP_REGS,     FP_REGS,        FP_REGS,        FP_REGS,
   FP_REGS,     FP_REGS,        FP_REGS,        FP_REGS,
   FP_REGS,     FP_REGS,        FP_REGS,        FP_REGS,
-  FRAME_REGS,  FRAME_REGS,     VL_REGS,        VTYPE_REGS,
+  FRAME_REGS,  FRAME_REGS,     NO_REGS,        NO_REGS,
   NO_REGS,     NO_REGS,        NO_REGS,        NO_REGS,
   NO_REGS,     NO_REGS,        NO_REGS,        NO_REGS,
   NO_REGS,     NO_REGS,        NO_REGS,        NO_REGS,
@@ -5831,12 +5831,6 @@ riscv_class_max_nregs (reg_class_t rclass, machine_mode mode)
   if (reg_class_subset_p (rclass, V_REGS))
     return riscv_hard_regno_nregs (V_REG_FIRST, mode);
 
-  if (reg_class_subset_p (rclass, VL_REGS))
-    return 1;
-
-  if (reg_class_subset_p (rclass, VTYPE_REGS))
-    return 1;
-
   return 0;
 }
 
index 0ab739bd6ebf5b594a403e46005a454d8e6cceb2..faffd5a77fe48550db2548afe7650762ac58dc40 100644 (file)
@@ -462,8 +462,6 @@ enum reg_class
   GR_REGS,                     /* integer registers */
   FP_REGS,                     /* floating-point registers */
   FRAME_REGS,                  /* arg pointer and frame pointer */
-  VL_REGS,                     /* vl register */
-  VTYPE_REGS,                  /* vtype register */
   VM_REGS,                     /* v0.t registers */
   VD_REGS,                     /* vector registers except v0.t */
   V_REGS,                      /* vector registers */
@@ -487,8 +485,6 @@ enum reg_class
   "GR_REGS",                                                           \
   "FP_REGS",                                                           \
   "FRAME_REGS",                                                                \
-  "VL_REGS",                                                           \
-  "VTYPE_REGS",                                                                \
   "VM_REGS",                                                           \
   "VD_REGS",                                                           \
   "V_REGS",                                                            \
@@ -514,12 +510,10 @@ enum reg_class
   { 0xffffffff, 0x00000000, 0x00000000, 0x00000000 },  /* GR_REGS */           \
   { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 },  /* FP_REGS */           \
   { 0x00000000, 0x00000000, 0x00000003, 0x00000000 },  /* FRAME_REGS */        \
-  { 0x00000000, 0x00000000, 0x00000004, 0x00000000 },  /* VL_REGS */           \
-  { 0x00000000, 0x00000000, 0x00000008, 0x00000000 },  /* VTYPE_REGS */        \
   { 0x00000000, 0x00000000, 0x00000000, 0x00000001 },  /* V0_REGS */           \
   { 0x00000000, 0x00000000, 0x00000000, 0xfffffffe },  /* VNoV0_REGS */        \
   { 0x00000000, 0x00000000, 0x00000000, 0xffffffff },  /* V_REGS */            \
-  { 0xffffffff, 0xffffffff, 0x0000000f, 0xffffffff }   /* ALL_REGS */          \
+  { 0xffffffff, 0xffffffff, 0x00000003, 0xffffffff }   /* ALL_REGS */          \
 }
 
 /* A C expression whose value is a register class containing hard