KVM: arm64: nv: Load timer before the GIC

In order for vgic_v3_load_nested to be able to observe which timer
interrupts have the HW bit set for the current context, the timers
must have been loaded in the new mode and the right timer mapped
to their corresponding HW IRQs.

At the moment, we load the GIC first, meaning that timer interrupts
injected to an L2 guest will never have the HW bit set (we see the
old configuration).

Swapping the two loads solves this particular problem.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250225172930.1850838-5-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>

diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index b8e55a441282f57cb2d4bc55a43b41d5b774dfdd..383aa48622344b571c6df135dabf911f6c22cd7c 100644 (file)
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -576,8 +576,12 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 nommu:
        vcpu->cpu = cpu;
 
-       kvm_vgic_load(vcpu);
+       /*
+        * The timer must be loaded before the vgic to correctly set up physical
+        * interrupt deactivation in nested state (e.g. timer interrupt).
+        */
        kvm_timer_vcpu_load(vcpu);
+       kvm_vgic_load(vcpu);
        kvm_vcpu_load_debug(vcpu);
        if (has_vhe())
                kvm_vcpu_load_vhe(vcpu);