pinctrl: tegra: Set SFIO mode to Mux Register

Tegra devices have an 'sfsel' bit field that determines whether a pin
operates in SFIO (Special Function I/O) or GPIO mode. Currently,
tegra_pinctrl_gpio_disable_free() sets this bit when releasing a GPIO.

However, tegra_pinctrl_set_mux() can be called independently in certain
code paths where gpio_disable_free() is not invoked. In such cases, failing
to set the SFIO mode could lead to incorrect pin configurations, resulting
in functional issues for peripherals relying on SFIO.

This patch ensures that whenever set_mux() is called, the SFIO mode is
correctly set in the Mux Register if the 'sfsel' bit is present. This
prevents situations where the pin remains in GPIO mode despite being
configured for SFIO use.

Fixes: 971dac7123c7 ("pinctrl: add a driver for NVIDIA Tegra")
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Link: https://lore.kernel.org/20250306050542.16335-1-pshete@nvidia.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index 23c19b6969d121f8c9483b1e01411abc4c5aca22..0246acba7703bc5d2bdadfd78ff641396251daa4 100644 (file)
--- a/drivers/pinctrl/tegra/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -271,6 +271,9 @@ static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
        val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
        val &= ~(0x3 << g->mux_bit);
        val |= i << g->mux_bit;
+       /* Set the SFIO/GPIO selection to SFIO when under pinmux control*/
+       if (pmx->soc->sfsel_in_mux)
+               val |= (1 << g->sfsel_bit);
        pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
 
        return 0;