]> git.ipfire.org Git - thirdparty/kernel/stable-queue.git/commitdiff
some 4.18 commit ids
authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 15 Aug 2018 12:25:52 +0000 (14:25 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 15 Aug 2018 12:25:52 +0000 (14:25 +0200)
queue-4.18/x86-speculation-l1tf-change-order-of-offset-type-in-swap-entry.patch
queue-4.18/x86-speculation-l1tf-increase-32bit-pae-__physical_page_shift.patch
queue-4.18/x86-speculation-l1tf-protect-swap-entries-against-l1tf.patch

index eac76152b7558c7ce15dac8ba354f328daa7c06c..01d9750d906599b9b51ade5d0795a0fa064d6e33 100644 (file)
@@ -5,6 +5,8 @@ Subject: x86/speculation/l1tf: Change order of offset/type in swap entry
 
 From: Linus Torvalds <torvalds@linux-foundation.org>
 
+commit 50896e180c6aa3a9c61a26ced99e15d602666a4c upstream.
+
 If pages are swapped out, the swap entry is stored in the corresponding
 PTE, which has the Present bit cleared. CPUs vulnerable to L1TF speculate
 on PTE entries which have the present bit set and would treat the swap
index 70e835d4214d02d94980ae2e2a52a2926405ee28..309f596335ca9aaece6891e8674c809019c25b8a 100644 (file)
@@ -5,6 +5,8 @@ Subject: x86/speculation/l1tf: Increase 32bit PAE __PHYSICAL_PAGE_SHIFT
 
 From: Andi Kleen <ak@linux.intel.com>
 
+commit 50896e180c6aa3a9c61a26ced99e15d602666a4c upstream.
+
 L1 Terminal Fault (L1TF) is a speculation related vulnerability. The CPU
 speculates on PTE entries which do not have the PRESENT bit set, if the
 content of the resulting physical address is available in the L1D cache.
index 407ade09addb69892cfa447ea49ab375358ecca1..9ee67e46894be3f9978ed490270716f9a0fd3d05 100644 (file)
@@ -5,6 +5,8 @@ Subject: x86/speculation/l1tf: Protect swap entries against L1TF
 
 From: Linus Torvalds <torvalds@linux-foundation.org>
 
+commit bcd11afa7adad8d720e7ba5ef58bdcd9775cf45f upstream.
+
 With L1 terminal fault the CPU speculates into unmapped PTEs, and resulting
 side effects allow to read the memory the PTE is pointing too, if its
 values are still in the L1 cache.