--- /dev/null
+From ac097aecfef0bb289ca53d2fe0b73fc7e1612a05 Mon Sep 17 00:00:00 2001
+From: Thierry Reding <treding@nvidia.com>
+Date: Fri, 19 Mar 2021 14:17:22 +0100
+Subject: drm/tegra: sor: Grab runtime PM reference across reset
+
+From: Thierry Reding <treding@nvidia.com>
+
+commit ac097aecfef0bb289ca53d2fe0b73fc7e1612a05 upstream.
+
+The SOR resets are exclusively shared with the SOR power domain. This
+means that exclusive access can only be granted temporarily and in order
+for that to work, a rigorous sequence must be observed. To ensure that a
+single consumer gets exclusive access to a reset, each consumer must
+implement a rigorous protocol using the reset_control_acquire() and
+reset_control_release() functions.
+
+However, these functions alone don't provide any guarantees at the
+system level. Drivers need to ensure that the only a single consumer has
+access to the reset at the same time. In order for the SOR to be able to
+exclusively access its reset, it must therefore ensure that the SOR
+power domain is not powered off by holding on to a runtime PM reference
+to that power domain across the reset assert/deassert operation.
+
+This used to work fine by accident, but was revealed when recently more
+devices started to rely on the SOR power domain.
+
+Fixes: 11c632e1cfd3 ("drm/tegra: sor: Implement acquire/release for reset")
+Reported-by: Jonathan Hunter <jonathanh@nvidia.com>
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/tegra/sor.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/drivers/gpu/drm/tegra/sor.c
++++ b/drivers/gpu/drm/tegra/sor.c
+@@ -2871,6 +2871,12 @@ static int tegra_sor_init(struct host1x_
+ * kernel is possible.
+ */
+ if (sor->rst) {
++ err = pm_runtime_resume_and_get(sor->dev);
++ if (err < 0) {
++ dev_err(sor->dev, "failed to get runtime PM: %d\n", err);
++ return err;
++ }
++
+ err = reset_control_acquire(sor->rst);
+ if (err < 0) {
+ dev_err(sor->dev, "failed to acquire SOR reset: %d\n",
+@@ -2904,6 +2910,7 @@ static int tegra_sor_init(struct host1x_
+ }
+
+ reset_control_release(sor->rst);
++ pm_runtime_put(sor->dev);
+ }
+
+ err = clk_prepare_enable(sor->clk_safe);
--- /dev/null
+From c971af25cda94afe71617790826a86253e88eab0 Mon Sep 17 00:00:00 2001
+From: Wang Panzhenzhuan <randy.wang@rock-chips.com>
+Date: Tue, 23 Feb 2021 18:07:25 +0800
+Subject: pinctrl: rockchip: fix restore error in resume
+
+From: Wang Panzhenzhuan <randy.wang@rock-chips.com>
+
+commit c971af25cda94afe71617790826a86253e88eab0 upstream.
+
+The restore in resume should match to suspend which only set for RK3288
+SoCs pinctrl.
+
+Fixes: 8dca933127024 ("pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume")
+Reviewed-by: Jianqun Xu <jay.xu@rock-chips.com>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
+Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
+Link: https://lore.kernel.org/r/20210223100725.269240-1-jay.xu@rock-chips.com
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/pinctrl/pinctrl-rockchip.c | 13 ++++++++-----
+ 1 file changed, 8 insertions(+), 5 deletions(-)
+
+--- a/drivers/pinctrl/pinctrl-rockchip.c
++++ b/drivers/pinctrl/pinctrl-rockchip.c
+@@ -3386,12 +3386,15 @@ static int __maybe_unused rockchip_pinct
+ static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
+ {
+ struct rockchip_pinctrl *info = dev_get_drvdata(dev);
+- int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
+- rk3288_grf_gpio6c_iomux |
+- GPIO6C6_SEL_WRITE_ENABLE);
++ int ret;
+
+- if (ret)
+- return ret;
++ if (info->ctrl->type == RK3288) {
++ ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
++ rk3288_grf_gpio6c_iomux |
++ GPIO6C6_SEL_WRITE_ENABLE);
++ if (ret)
++ return ret;
++ }
+
+ return pinctrl_force_default(info->pctl_dev);
+ }
drm-amdgpu-fix-offset-calculation-in-amdgpu_vm_bo_clear_mappings.patch
drm-amdgpu-check-alignment-on-cpu-page-for-bo-map.patch
reiserfs-update-reiserfs_xattrs_initialized-condition.patch
+drm-tegra-sor-grab-runtime-pm-reference-across-reset.patch
+vfio-nvlink-add-missing-spapr_tce_iommu-depends.patch
+pinctrl-rockchip-fix-restore-error-in-resume.patch
--- /dev/null
+From e0146a108ce4d2c22b9510fd12268e3ee72a0161 Mon Sep 17 00:00:00 2001
+From: Jason Gunthorpe <jgg@nvidia.com>
+Date: Mon, 29 Mar 2021 16:00:16 -0300
+Subject: vfio/nvlink: Add missing SPAPR_TCE_IOMMU depends
+
+From: Jason Gunthorpe <jgg@nvidia.com>
+
+commit e0146a108ce4d2c22b9510fd12268e3ee72a0161 upstream.
+
+Compiling the nvlink stuff relies on the SPAPR_TCE_IOMMU otherwise there
+are compile errors:
+
+ drivers/vfio/pci/vfio_pci_nvlink2.c:101:10: error: implicit declaration of function 'mm_iommu_put' [-Werror,-Wimplicit-function-declaration]
+ ret = mm_iommu_put(data->mm, data->mem);
+
+As PPC only defines these functions when the config is set.
+
+Previously this wasn't a problem by chance as SPAPR_TCE_IOMMU was the only
+IOMMU that could have satisfied IOMMU_API on POWERNV.
+
+Fixes: 179209fa1270 ("vfio: IOMMU_API should be selected")
+Reported-by: kernel test robot <lkp@intel.com>
+Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
+Message-Id: <0-v1-83dba9768fc3+419-vfio_nvlink2_kconfig_jgg@nvidia.com>
+Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/vfio/pci/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/vfio/pci/Kconfig
++++ b/drivers/vfio/pci/Kconfig
+@@ -42,6 +42,6 @@ config VFIO_PCI_IGD
+
+ config VFIO_PCI_NVLINK2
+ def_bool y
+- depends on VFIO_PCI && PPC_POWERNV
++ depends on VFIO_PCI && PPC_POWERNV && SPAPR_TCE_IOMMU
+ help
+ VFIO PCI support for P9 Witherspoon machine with NVIDIA V100 GPUs
projects / thirdparty / kernel / stable-queue.git / commitdiff
