*/
#include <linux/clk-provider.h>
+#include <linux/interconnect-provider.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
+#include <dt-bindings/interconnect/qcom,ipq5424.h>
#include <dt-bindings/reset/qcom,ipq5424-gcc.h>
#include "clk-alpha-pll.h"
[GCC_QUSB2_1_PHY_BCR] = { 0x3C030, 0 },
};
+#define IPQ_APPS_ID 5424 /* some unique value */
+
+static const struct qcom_icc_hws_data icc_ipq5424_hws[] = {
+ { MASTER_ANOC_PCIE0, SLAVE_ANOC_PCIE0, GCC_ANOC_PCIE0_1LANE_M_CLK },
+ { MASTER_CNOC_PCIE0, SLAVE_CNOC_PCIE0, GCC_CNOC_PCIE0_1LANE_S_CLK },
+ { MASTER_ANOC_PCIE1, SLAVE_ANOC_PCIE1, GCC_ANOC_PCIE1_1LANE_M_CLK },
+ { MASTER_CNOC_PCIE1, SLAVE_CNOC_PCIE1, GCC_CNOC_PCIE1_1LANE_S_CLK },
+ { MASTER_ANOC_PCIE2, SLAVE_ANOC_PCIE2, GCC_ANOC_PCIE2_2LANE_M_CLK },
+ { MASTER_CNOC_PCIE2, SLAVE_CNOC_PCIE2, GCC_CNOC_PCIE2_2LANE_S_CLK },
+ { MASTER_ANOC_PCIE3, SLAVE_ANOC_PCIE3, GCC_ANOC_PCIE3_2LANE_M_CLK },
+ { MASTER_CNOC_PCIE3, SLAVE_CNOC_PCIE3, GCC_CNOC_PCIE3_2LANE_S_CLK },
+ { MASTER_CNOC_USB, SLAVE_CNOC_USB, GCC_CNOC_USB_CLK },
+};
+
static const struct of_device_id gcc_ipq5424_match_table[] = {
{ .compatible = "qcom,ipq5424-gcc" },
{ }
.num_resets = ARRAY_SIZE(gcc_ipq5424_resets),
.clk_hws = gcc_ipq5424_hws,
.num_clk_hws = ARRAY_SIZE(gcc_ipq5424_hws),
+ .icc_hws = icc_ipq5424_hws,
+ .num_icc_hws = ARRAY_SIZE(icc_ipq5424_hws),
};
static int gcc_ipq5424_probe(struct platform_device *pdev)
.driver = {
.name = "qcom,gcc-ipq5424",
.of_match_table = gcc_ipq5424_match_table,
+ .sync_state = icc_sync_state,
},
};