]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
clk: qcom: ipq5424: Use icc-clk for enabling NoC related clocks
authorVaradarajan Narayanan <quic_varada@quicinc.com>
Fri, 13 Dec 2024 10:58:08 +0000 (16:28 +0530)
committerBjorn Andersson <andersson@kernel.org>
Wed, 8 Jan 2025 02:38:41 +0000 (20:38 -0600)
Use the icc-clk framework to enable few clocks to be able to
create paths and use the peripherals connected on those NoCs.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20241213105808.674620-2-quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
drivers/clk/qcom/gcc-ipq5424.c

index 92b133baec01f321459aeb6112d3028711402dbc..d5b218b76e2912678ca00b6a324f7ff9d90ab260 100644 (file)
@@ -5,6 +5,7 @@
  */
 
 #include <linux/clk-provider.h>
+#include <linux/interconnect-provider.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/of.h>
@@ -12,6 +13,7 @@
 #include <linux/regmap.h>
 
 #include <dt-bindings/clock/qcom,ipq5424-gcc.h>
+#include <dt-bindings/interconnect/qcom,ipq5424.h>
 #include <dt-bindings/reset/qcom,ipq5424-gcc.h>
 
 #include "clk-alpha-pll.h"
@@ -3230,6 +3232,20 @@ static const struct qcom_reset_map gcc_ipq5424_resets[] = {
        [GCC_QUSB2_1_PHY_BCR] = { 0x3C030, 0 },
 };
 
+#define IPQ_APPS_ID                    5424    /* some unique value */
+
+static const struct qcom_icc_hws_data icc_ipq5424_hws[] = {
+       { MASTER_ANOC_PCIE0, SLAVE_ANOC_PCIE0, GCC_ANOC_PCIE0_1LANE_M_CLK },
+       { MASTER_CNOC_PCIE0, SLAVE_CNOC_PCIE0, GCC_CNOC_PCIE0_1LANE_S_CLK },
+       { MASTER_ANOC_PCIE1, SLAVE_ANOC_PCIE1, GCC_ANOC_PCIE1_1LANE_M_CLK },
+       { MASTER_CNOC_PCIE1, SLAVE_CNOC_PCIE1, GCC_CNOC_PCIE1_1LANE_S_CLK },
+       { MASTER_ANOC_PCIE2, SLAVE_ANOC_PCIE2, GCC_ANOC_PCIE2_2LANE_M_CLK },
+       { MASTER_CNOC_PCIE2, SLAVE_CNOC_PCIE2, GCC_CNOC_PCIE2_2LANE_S_CLK },
+       { MASTER_ANOC_PCIE3, SLAVE_ANOC_PCIE3, GCC_ANOC_PCIE3_2LANE_M_CLK },
+       { MASTER_CNOC_PCIE3, SLAVE_CNOC_PCIE3, GCC_CNOC_PCIE3_2LANE_S_CLK },
+       { MASTER_CNOC_USB, SLAVE_CNOC_USB, GCC_CNOC_USB_CLK },
+};
+
 static const struct of_device_id gcc_ipq5424_match_table[] = {
        { .compatible = "qcom,ipq5424-gcc" },
        { }
@@ -3260,6 +3276,8 @@ static const struct qcom_cc_desc gcc_ipq5424_desc = {
        .num_resets = ARRAY_SIZE(gcc_ipq5424_resets),
        .clk_hws = gcc_ipq5424_hws,
        .num_clk_hws = ARRAY_SIZE(gcc_ipq5424_hws),
+       .icc_hws = icc_ipq5424_hws,
+       .num_icc_hws = ARRAY_SIZE(icc_ipq5424_hws),
 };
 
 static int gcc_ipq5424_probe(struct platform_device *pdev)
@@ -3272,6 +3290,7 @@ static struct platform_driver gcc_ipq5424_driver = {
        .driver = {
                .name   = "qcom,gcc-ipq5424",
                .of_match_table = gcc_ipq5424_match_table,
+               .sync_state = icc_sync_state,
        },
 };