]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
arm64: dts: ti: k3-am642-phyboard-electra: Add boot phase tags
authorWadim Egorov <w.egorov@phytec.de>
Wed, 5 Mar 2025 08:55:35 +0000 (09:55 +0100)
committerVignesh Raghavendra <vigneshr@ti.com>
Fri, 7 Mar 2025 13:18:05 +0000 (18:48 +0530)
The bootph-all and bootph-pre-ram tags were introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across different
boot phases.

Add boot phase tags to all required nodes to ensure boot support from
all sources, including UART, Ethernet, uSD card, eMMC, and OSPI NOR Flash.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20250305085537.3976579-3-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts

index e8d1b88651e78e57a8399201b876480ca4362443..c95f9d642f0d4dcd748164054259a48f6fb017e4 100644 (file)
@@ -27,6 +27,7 @@
        memory@80000000 {
                device_type = "memory";
                reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+               bootph-all;
        };
 
        reserved_memory: reserved-memory {
                        AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4)      /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
                        AM64X_IOPAD(0x0100, PIN_OUTPUT, 7)      /* (V7) PRG1_PRU0_GPO18.GPIO0_63 */
                >;
+               bootph-all;
        };
 
        cpsw_rgmii1_pins_default: cpsw-rgmii1-default-pins {
                        AM64X_IOPAD(0x014c, PIN_OUTPUT, 4)      /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
                        AM64X_IOPAD(0x0154, PIN_INPUT, 7)       /* (V12) PRG1_PRU1_GPO19.GPIO0_84 */
                >;
+               bootph-all;
        };
 
        eeprom_wp_pins_default: eeprom-wp-default-pins {
                        AM64X_IOPAD(0x0260, PIN_INPUT, 0)       /* (A18) I2C0_SCL */
                        AM64X_IOPAD(0x0264, PIN_INPUT, 0)       /* (B18) I2C0_SDA */
                >;
+               bootph-all;
        };
 
        ospi0_pins_default: ospi0-default-pins {
                        AM64X_IOPAD(0x0028, PIN_INPUT, 0)       /* (M17) OSPI0_D7 */
                        AM64X_IOPAD(0x002c, PIN_OUTPUT, 0)      /* (L19) OSPI0_CSn0 */
                >;
+               bootph-all;
        };
 
        rtc_pins_default: rtc-defaults-pins {
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&cpsw_mdio_pins_default>;
+       bootph-all;
 
        cpsw3g_phy1: ethernet-phy@1 {
                compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
                reset-gpios = <&main_gpio0 63 GPIO_ACTIVE_LOW>;
                reset-assert-us = <1000>;
                reset-deassert-us = <1000>;
+               bootph-all;
        };
 };
 
 &cpsw_port1 {
        phy-mode = "rgmii-rxid";
        phy-handle = <&cpsw3g_phy1>;
+       bootph-all;
        status = "okay";
 };
 
        pinctrl-names = "default";
        pinctrl-0 = <&main_i2c0_pins_default>;
        clock-frequency = <400000>;
+       bootph-all;
 
        eeprom@50 {
                compatible = "atmel,24c32";
        };
 };
 
+&main_pktdma {
+       bootph-all;
+};
+
 &main_r5fss0_core0 {
        mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
        memory-region = <&main_r5fss0_core0_dma_memory_region>,
                cdns,tchsh-ns = <60>;
                cdns,tslch-ns = <60>;
                cdns,read-delay = <0>;
+               bootph-all;
        };
 };
 
        ti,driver-strength-ohm = <50>;
        disable-wp;
        keep-power-in-suspend;
+       bootph-all;
 };
 
 &tscadc0 {
index bc8e1ce11047bbbcf64d0cdac620efaaf3973a7f..6fbd8d932396a9a5b3f82811b13ae0f386db27ce 100644 (file)
                regulator-max-microvolt = <3300000>;
                regulator-boot-on;
                regulator-always-on;
+               bootph-all;
        };
 };
 
                        AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0)        /* (J19) MMC1_CMD */
                        AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0)        /* (D19) MMC1_SDCD */
                >;
+               bootph-all;
        };
 
        main_spi0_pins_default: main-spi0-default-pins {
                        AM64X_IOPAD(0x0230, PIN_INPUT, 0)       /* (D15) UART0_RXD */
                        AM64X_IOPAD(0x0234, PIN_OUTPUT, 0)      /* (C16) UART0_TXD */
                >;
+               bootph-all;
        };
 
        main_uart1_pins_default: main-uart1-default-pins {
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&main_uart0_pins_default>;
+       bootph-all;
 };
 
 &main_uart1 {
        pinctrl-0 = <&main_mmc1_pins_default>;
        disable-wp;
        no-1-8-v;
+       bootph-all;
 };
 
 &serdes0 {