]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
ARM: dts: rockchip: Add DSI for RK3128
authorAlex Bee <knaerzche@gmail.com>
Thu, 9 May 2024 14:06:53 +0000 (16:06 +0200)
committerHeiko Stuebner <heiko@sntech.de>
Sun, 23 Jun 2024 20:04:25 +0000 (22:04 +0200)
Add the Designware MIPI DSI controller and it's port nodes.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20240509140653.168591-8-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm/boot/dts/rockchip/rk3128.dtsi

index 2e8ab8e8796a76d4b4d0268b220a8555257d37c9..a7ab0904564f0de47fdc8bb3ee4f573098808a3d 100644 (file)
                                reg = <0>;
                                remote-endpoint = <&hdmi_in_vop>;
                        };
+
+                       vop_out_dsi: endpoint@1 {
+                               reg = <1>;
+                               remote-endpoint = <&dsi_in_vop>;
+                       };
+               };
+       };
+
+       dsi: dsi@10110000 {
+               compatible = "rockchip,rk3128-mipi-dsi", "snps,dw-mipi-dsi";
+               reg = <0x10110000 0x4000>;
+               interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru PCLK_MIPI>;
+               clock-names = "pclk";
+               phys = <&dphy>;
+               phy-names = "dphy";
+               power-domains = <&power RK3128_PD_VIO>;
+               resets = <&cru SRST_VIO_MIPI_DSI>;
+               reset-names = "apb";
+               rockchip,grf = <&grf>;
+               status = "disabled";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       dsi_in: port@0 {
+                               reg = <0>;
+
+                               dsi_in_vop: endpoint {
+                                       remote-endpoint = <&vop_out_dsi>;
+                               };
+                       };
+
+                       dsi_out: port@1 {
+                               reg = <1>;
+                       };
                };
        };