clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_sel

Use CLK_SET_RATE_NO_REPARENT for the vclk{,2}_in_sel clocks. The only
parent which is actually used is vid_pll_final_div. This should be set
using assigned-clock-parents in the .dts rather than removing some
"unwanted" clock parents from the clock driver.

Suggested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20210713232510.3057750-2-martin.blumenstingl@googlemail.com

diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index a844d35b553a2b4236aa1d92fa9f4c5fca8b172f..0f8bd707217a181720637e2b2150d8faa8fa5290 100644 (file)
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -1175,7 +1175,7 @@ static struct clk_regmap meson8b_vclk_in_sel = {
                .ops = &clk_regmap_mux_ro_ops,
                .parent_hws = meson8b_vclk_mux_parent_hws,
                .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
-               .flags = CLK_SET_RATE_PARENT,
+               .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
        },
 };
 
@@ -1358,7 +1358,7 @@ static struct clk_regmap meson8b_vclk2_in_sel = {
                .ops = &clk_regmap_mux_ro_ops,
                .parent_hws = meson8b_vclk_mux_parent_hws,
                .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
-               .flags = CLK_SET_RATE_PARENT,
+               .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
        },
 };