arm64: dts: qcom: sc8180x: correct dispcc clocks

Correct the clocks being used by the display clock controller on the
SC8180X platform (to match the schema):
- Drop the sleep clock
- Add DSI clocks
- Reorder eDP / DP clocks

This changes the order of clocks, however it should be noted that the
clock list was neither correct nor followed the schema beforehand.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240512-typec-fix-sm8250-v4-2-ad153c747a97@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index a2bd808bb33027ee80387374d3a6ad6b675445b7..6f17fb7975fe7cecf9054231bd3c3050d3ddf2f2 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -3303,21 +3303,27 @@
                        compatible = "qcom,sc8180x-dispcc";
                        reg = <0 0x0af00000 0 0x20000>;
                        clocks = <&rpmhcc RPMH_CXO_CLK>,
-                                <&sleep_clk>,
+                                <&mdss_dsi0_phy 0>,
+                                <&mdss_dsi0_phy 1>,
+                                <&mdss_dsi1_phy 0>,
+                                <&mdss_dsi1_phy 1>,
                                 <&usb_prim_dpphy 0>,
                                 <&usb_prim_dpphy 1>,
-                                <&usb_sec_dpphy 0>,
-                                <&usb_sec_dpphy 1>,
                                 <&edp_phy 0>,
-                                <&edp_phy 1>;
+                                <&edp_phy 1>,
+                                <&usb_sec_dpphy 0>,
+                                <&usb_sec_dpphy 1>;
                        clock-names = "bi_tcxo",
-                                     "sleep_clk",
+                                     "dsi0_phy_pll_out_byteclk",
+                                     "dsi0_phy_pll_out_dsiclk",
+                                     "dsi1_phy_pll_out_byteclk",
+                                     "dsi1_phy_pll_out_dsiclk",
                                      "dp_phy_pll_link_clk",
                                      "dp_phy_pll_vco_div_clk",
-                                     "dptx1_phy_pll_link_clk",
-                                     "dptx1_phy_pll_vco_div_clk",
                                      "edp_phy_pll_link_clk",
-                                     "edp_phy_pll_vco_div_clk";
+                                     "edp_phy_pll_vco_div_clk",
+                                     "dptx1_phy_pll_link_clk",
+                                     "dptx1_phy_pll_vco_div_clk";
                        power-domains = <&rpmhpd SC8180X_MMCX>;
                        required-opps = <&rpmhpd_opp_low_svs>;
                        #clock-cells = <1>;