]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
mmc: Define timing macro's
authorAshok Reddy Soma <ashok.reddy.soma@xilinx.com>
Fri, 23 Oct 2020 10:58:58 +0000 (04:58 -0600)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 27 Oct 2020 07:13:33 +0000 (08:13 +0100)
Define timing macro's for all the available speeds of mmc. This is
done similar to linux. Replace speed macro's used with these new timing
macro's wherever applicable.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
board/xilinx/zynqmp/tap_delays.c
drivers/mmc/zynq_sdhci.c
include/mmc.h

index 5fde0aed7dbe7a12748f3ee24c048e232b8fb0e0..13683701f64e5da85bb24c9c6f440364364a5ba0 100644 (file)
@@ -8,6 +8,7 @@
 #include <common.h>
 #include <asm/arch/sys_proto.h>
 #include <linux/delay.h>
+#include <mmc.h>
 
 #define SD_DLL_CTRL                    0xFF180358
 #define SD_ITAP_DLY                    0xFF180314
 
 #define MMC_BANK2              0x2
 
-#define MMC_TIMING_UHS_SDR25           1
-#define MMC_TIMING_UHS_SDR50           2
-#define MMC_TIMING_UHS_SDR104          3
-#define MMC_TIMING_UHS_DDR50           4
-#define MMC_TIMING_MMC_HS200           5
-#define MMC_TIMING_SD_HS               6
-#define MMC_TIMING_MMC_DDR52           7
-#define MMC_TIMING_MMC_HS              8
-
 void zynqmp_dll_reset(u8 deviceid)
 {
        /* Issue DLL Reset */
index 88e478ee11c12b85389e512434be4c150e28841e..4f62bd008d24c3d0bb21c18c77ba04a0f75e8908 100644 (file)
@@ -32,20 +32,18 @@ struct arasan_sdhci_priv {
 };
 
 #if defined(CONFIG_ARCH_ZYNQMP)
-#define MMC_HS200_BUS_SPEED    5
-
 static const u8 mode2timing[] = {
-       [MMC_LEGACY] = UHS_SDR12_BUS_SPEED,
-       [MMC_HS] = HIGH_SPEED_BUS_SPEED,
-       [SD_HS] = HIGH_SPEED_BUS_SPEED,
-       [MMC_HS_52] = HIGH_SPEED_BUS_SPEED,
-       [MMC_DDR_52] = HIGH_SPEED_BUS_SPEED,
-       [UHS_SDR12] = UHS_SDR12_BUS_SPEED,
-       [UHS_SDR25] = UHS_SDR25_BUS_SPEED,
-       [UHS_SDR50] = UHS_SDR50_BUS_SPEED,
-       [UHS_DDR50] = UHS_DDR50_BUS_SPEED,
-       [UHS_SDR104] = UHS_SDR104_BUS_SPEED,
-       [MMC_HS_200] = MMC_HS200_BUS_SPEED,
+       [MMC_LEGACY] = MMC_TIMING_LEGACY,
+       [MMC_HS] = MMC_TIMING_MMC_HS,
+       [SD_HS] = MMC_TIMING_SD_HS,
+       [MMC_HS_52] = MMC_TIMING_UHS_SDR50,
+       [MMC_DDR_52] = MMC_TIMING_UHS_DDR50,
+       [UHS_SDR12] = MMC_TIMING_UHS_SDR12,
+       [UHS_SDR25] = MMC_TIMING_UHS_SDR25,
+       [UHS_SDR50] = MMC_TIMING_UHS_SDR50,
+       [UHS_DDR50] = MMC_TIMING_UHS_DDR50,
+       [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
+       [MMC_HS_200] = MMC_TIMING_MMC_HS200,
 };
 
 #define SDHCI_TUNING_LOOP_COUNT        40
index ac7b54f1a7e0497ca2b29a6119dd69f37efee514..1d377e0281f1e95cf698e5053a491960dd11d57f 100644 (file)
@@ -360,6 +360,19 @@ enum mmc_voltage {
 #define MMC_NUM_BOOT_PARTITION 2
 #define MMC_PART_RPMB           3       /* RPMB partition number */
 
+/* timing specification used */
+#define MMC_TIMING_LEGACY      0
+#define MMC_TIMING_MMC_HS      1
+#define MMC_TIMING_SD_HS       2
+#define MMC_TIMING_UHS_SDR12   3
+#define MMC_TIMING_UHS_SDR25   4
+#define MMC_TIMING_UHS_SDR50   5
+#define MMC_TIMING_UHS_SDR104  6
+#define MMC_TIMING_UHS_DDR50   7
+#define MMC_TIMING_MMC_DDR52   8
+#define MMC_TIMING_MMC_HS200   9
+#define MMC_TIMING_MMC_HS400   10
+
 /* Driver model support */
 
 /**