xcc->parent_reset(s);
env->exception_taken = 0;
- env->pc = env->config->exception_vector[EXC_RESET];
+ env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
env->sregs[LITBASE] &= ~1;
env->sregs[PS] = xtensa_option_enabled(env->config,
XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
enum {
/* Static vectors */
- EXC_RESET,
+ EXC_RESET0,
+ EXC_RESET1,
EXC_MEMORY_ERROR,
/* Dynamic vectors */
int64_t halt_clock;
int exception_taken;
+ unsigned static_vectors;
/* Watchpoints for DBREAK registers */
struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);
void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
+static inline void xtensa_select_static_vectors(CPUXtensaState *env,
+ unsigned n)
+{
+ assert(n < 2);
+ env->static_vectors = n;
+}
#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
#define XTENSA_OPTION_ALL (~(uint64_t)0)
#define XCHAL_VECBASE_RESET_VADDR 0
#endif
+#ifndef XCHAL_RESET_VECTOR0_VADDR
+#define XCHAL_RESET_VECTOR0_VADDR XCHAL_RESET_VECTOR_VADDR
+#endif
+
+#ifndef XCHAL_RESET_VECTOR1_VADDR
+#define XCHAL_RESET_VECTOR1_VADDR XCHAL_RESET_VECTOR_VADDR
+#endif
+
#ifndef XCHAL_HW_MIN_VERSION
#define XCHAL_HW_MIN_VERSION 0
#endif
#endif
#define EXCEPTION_VECTORS { \
- [EXC_RESET] = XCHAL_RESET_VECTOR_VADDR, \
+ [EXC_RESET0] = XCHAL_RESET_VECTOR0_VADDR, \
+ [EXC_RESET1] = XCHAL_RESET_VECTOR1_VADDR, \
WINDOW_VECTORS \
[EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \
[EXC_USER] = XCHAL_USER_VECTOR_VADDR, \