mm-make-the-vma-list-be-doubly-linked.patch
mm-make-the-mlock-stack-guard-page-checks-stricter.patch
mm-make-stack-guard-page-logic-use-vm_prev-pointer.patch
+x86-asm-clean-up-and-simplify-set_64bit.patch
+slab-fix-object-alignment.patch
+sparc64-add-missing-id-to-parport-probing-code.patch
+sparc64-fix-rwsem-constant-bug-leading-to-hangs.patch
+sparc64-fix-atomic64_t-routine-return-values.patch
+sparc-really-fix-console-for-serial-consoles.patch
--- /dev/null
+From 1ab335d8f85792e3b107ff8237d53cf64db714df Mon Sep 17 00:00:00 2001
+From: Carsten Otte <cotte@de.ibm.com>
+Date: Fri, 6 Aug 2010 18:19:22 +0200
+Subject: slab: fix object alignment
+
+From: Carsten Otte <cotte@de.ibm.com>
+
+commit 1ab335d8f85792e3b107ff8237d53cf64db714df upstream.
+
+This patch fixes alignment of slab objects in case CONFIG_DEBUG_PAGEALLOC is
+active.
+Before this spot in kmem_cache_create, we have this situation:
+- align contains the required alignment of the object
+- cachep->obj_offset is 0 or equals align in case of CONFIG_DEBUG_SLAB
+- size equals the size of the object, or object plus trailing redzone in case
+ of CONFIG_DEBUG_SLAB
+
+This spot tries to fill one page per object if the object is in certain size
+limits, however setting obj_offset to PAGE_SIZE - size does break the object
+alignment since size may not be aligned with the required alignment.
+This patch simply adds an ALIGN(size, align) to the equation and fixes the
+object size detection accordingly.
+
+This code in drivers/s390/cio/qdio_setup_init has lead to incorrectly aligned
+slab objects (sizeof(struct qdio_q) equals 1792):
+ qdio_q_cache = kmem_cache_create("qdio_q", sizeof(struct qdio_q),
+ 256, 0, NULL);
+
+Acked-by: Christoph Lameter <cl@linux.com>
+Signed-off-by: Carsten Otte <cotte@de.ibm.com>
+Signed-off-by: Pekka Enberg <penberg@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ mm/slab.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/mm/slab.c
++++ b/mm/slab.c
+@@ -2331,8 +2331,8 @@ kmem_cache_create (const char *name, siz
+ }
+ #if FORCED_DEBUG && defined(CONFIG_DEBUG_PAGEALLOC)
+ if (size >= malloc_sizes[INDEX_L3 + 1].cs_size
+- && cachep->obj_size > cache_line_size() && size < PAGE_SIZE) {
+- cachep->obj_offset += PAGE_SIZE - size;
++ && cachep->obj_size > cache_line_size() && ALIGN(size, align) < PAGE_SIZE) {
++ cachep->obj_offset += PAGE_SIZE - ALIGN(size, align);
+ size = PAGE_SIZE;
+ }
+ #endif
--- /dev/null
+From 93b9e75afdef92582a4923f9507373ee780bc4b1 Mon Sep 17 00:00:00 2001
+From: David S. Miller <davem@davemloft.net>
+Date: Sun, 15 Aug 2010 00:26:14 -0700
+Subject: sparc: Really fix "console=" for serial consoles.
+
+
+From: David S. Miller <davem@davemloft.net>
+
+[ Upstream commit 0a492896ac07336c98f37ad7fab4a6387b6ada78 ]
+
+If a video head and keyboard are hooked up, specifying "console=ttyS0"
+or similar to use a serial console will not work properly.
+
+The key issue is that we must register all serial console capable
+devices with register_console(), otherwise the command line specified
+device won't be found. The sun serial drivers would only register
+themselves as console devices if the OpenFirmware specified console
+device node matched. To fix this part we now unconditionally get
+the serial console register by setting serial_drv->cons always.
+
+Secondarily we must not add_preferred_console() using the firmware
+provided console setting if the user gaven an override on the kernel
+command line using "console=" The "primary framebuffer" matching
+logic was always triggering o n openfirmware device node match, make
+it not when a command line override was given.
+
+Reported-by: Frans Pop <elendil@planet.nl>
+Tested-by: Frans Pop <elendil@planet.nl>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+---
+ arch/sparc/include/asm/fb.h | 4 ++++
+ drivers/serial/suncore.c | 15 +++++++++------
+ 2 files changed, 13 insertions(+), 6 deletions(-)
+
+--- a/arch/sparc/include/asm/fb.h
++++ b/arch/sparc/include/asm/fb.h
+@@ -1,5 +1,6 @@
+ #ifndef _SPARC_FB_H_
+ #define _SPARC_FB_H_
++#include <linux/console.h>
+ #include <linux/fb.h>
+ #include <linux/fs.h>
+ #include <asm/page.h>
+@@ -18,6 +19,9 @@ static inline int fb_is_primary_device(s
+ struct device *dev = info->device;
+ struct device_node *node;
+
++ if (console_set_on_cmdline)
++ return 0;
++
+ node = dev->of_node;
+ if (node &&
+ node == of_console_device)
+--- a/drivers/serial/suncore.c
++++ b/drivers/serial/suncore.c
+@@ -55,7 +55,12 @@ EXPORT_SYMBOL(sunserial_unregister_minor
+ int sunserial_console_match(struct console *con, struct device_node *dp,
+ struct uart_driver *drv, int line, bool ignore_line)
+ {
+- if (!con || of_console_device != dp)
++ if (!con)
++ return 0;
++
++ drv->cons = con;
++
++ if (of_console_device != dp)
+ return 0;
+
+ if (!ignore_line) {
+@@ -69,12 +74,10 @@ int sunserial_console_match(struct conso
+ return 0;
+ }
+
+- con->index = line;
+- drv->cons = con;
+-
+- if (!console_set_on_cmdline)
++ if (!console_set_on_cmdline) {
++ con->index = line;
+ add_preferred_console(con->name, line, NULL);
+-
++ }
+ return 1;
+ }
+ EXPORT_SYMBOL(sunserial_console_match);
--- /dev/null
+From cb81a0c77c109914b1394b32f8c453c293fd5ad0 Mon Sep 17 00:00:00 2001
+From: David S. Miller <davem@davemloft.net>
+Date: Wed, 4 Aug 2010 17:30:21 -0700
+Subject: sparc64: Add missing ID to parport probing code.
+
+
+From: David S. Miller <davem@davemloft.net>
+
+[ Upstream commit bf8253bf5e7cfe17dd53e3f6340a45b11d9fb51c ]
+
+SunBlade-2500 has 'parallel' device node with compatible
+property "pnpALI,1533,3" so add that to the ID table.
+
+Reported-by: Mikael Pettersson <mikpe@it.uu.se>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+---
+ arch/sparc/include/asm/parport.h | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/sparc/include/asm/parport.h
++++ b/arch/sparc/include/asm/parport.h
+@@ -228,6 +228,10 @@ static const struct of_device_id ecpp_ma
+ .name = "parallel",
+ .compatible = "ns87317-ecpp",
+ },
++ {
++ .name = "parallel",
++ .compatible = "pnpALI,1533,3",
++ },
+ {},
+ };
+
--- /dev/null
+From eb23d7799588b46bdad9f31674ad0e589b630168 Mon Sep 17 00:00:00 2001
+From: David S. Miller <davem@davemloft.net>
+Date: Wed, 18 Aug 2010 14:47:23 -0700
+Subject: sparc64: Fix atomic64_t routine return values.
+
+
+From: David S. Miller <davem@davemloft.net>
+
+[ Upstream commits 86fa04b8742ac681d470786f55e2403ada0075b2
+ and b10f997bb0f4e5b34d447f498fb85834a40d3acb ]
+
+Should return 'long' instead of 'int'.
+
+Thanks to Dimitris Michailidis and Tony Luck.
+
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+---
+ arch/sparc/include/asm/atomic_64.h | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+--- a/arch/sparc/include/asm/atomic_64.h
++++ b/arch/sparc/include/asm/atomic_64.h
+@@ -20,14 +20,14 @@
+ #define atomic64_set(v, i) (((v)->counter) = i)
+
+ extern void atomic_add(int, atomic_t *);
+-extern void atomic64_add(int, atomic64_t *);
++extern void atomic64_add(long, atomic64_t *);
+ extern void atomic_sub(int, atomic_t *);
+-extern void atomic64_sub(int, atomic64_t *);
++extern void atomic64_sub(long, atomic64_t *);
+
+ extern int atomic_add_ret(int, atomic_t *);
+-extern int atomic64_add_ret(int, atomic64_t *);
++extern long atomic64_add_ret(long, atomic64_t *);
+ extern int atomic_sub_ret(int, atomic_t *);
+-extern int atomic64_sub_ret(int, atomic64_t *);
++extern long atomic64_sub_ret(long, atomic64_t *);
+
+ #define atomic_dec_return(v) atomic_sub_ret(1, v)
+ #define atomic64_dec_return(v) atomic64_sub_ret(1, v)
+@@ -91,7 +91,7 @@ static inline int atomic_add_unless(atom
+ ((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
+ #define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
+
+-static inline int atomic64_add_unless(atomic64_t *v, long a, long u)
++static inline long atomic64_add_unless(atomic64_t *v, long a, long u)
+ {
+ long c, old;
+ c = atomic64_read(v);
--- /dev/null
+From 87e4bc40163f0b244cab477efe50a4ff0c3ca05e Mon Sep 17 00:00:00 2001
+From: David S. Miller <davem@davemloft.net>
+Date: Tue, 17 Aug 2010 17:09:53 -0700
+Subject: sparc64: Fix rwsem constant bug leading to hangs.
+
+
+From: David S. Miller <davem@davemloft.net>
+
+[ Upstream commit ef201bebe5afc91a2b99b45dacc8c6dd88ca9e58 ]
+
+As noticed by Linus, it is critical that some of the
+rwsem constants be signed. Yet, hex constants are
+unsigned unless explicitly casted or negated.
+
+The most critical one is RWSEM_WAITING_BIAS.
+
+This bug was exacerbated by commit
+424acaaeb3a3932d64a9b4bd59df6cf72c22d8f3 ("rwsem: wake queued readers
+when writer blocks on active read lock")
+
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+---
+ arch/sparc/include/asm/rwsem-const.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/sparc/include/asm/rwsem-const.h
++++ b/arch/sparc/include/asm/rwsem-const.h
+@@ -5,7 +5,7 @@
+ #define RWSEM_UNLOCKED_VALUE 0x00000000
+ #define RWSEM_ACTIVE_BIAS 0x00000001
+ #define RWSEM_ACTIVE_MASK 0x0000ffff
+-#define RWSEM_WAITING_BIAS 0xffff0000
++#define RWSEM_WAITING_BIAS (-0x00010000)
+ #define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
+ #define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
+
--- /dev/null
+From 69309a05907546fb686b251d4ab041c26afe1e1d Mon Sep 17 00:00:00 2001
+From: H. Peter Anvin <hpa@zytor.com>
+Date: Tue, 27 Jul 2010 23:29:52 -0700
+Subject: x86, asm: Clean up and simplify set_64bit()
+
+From: H. Peter Anvin <hpa@zytor.com>
+
+commit 69309a05907546fb686b251d4ab041c26afe1e1d upstream.
+
+Clean up and simplify set_64bit(). This code is quite old (1.3.11)
+and contains a fair bit of auxilliary machinery that current versions
+of gcc handle just fine automatically. Worse, the auxilliary
+machinery can actually cause an unnecessary spill to memory.
+
+Furthermore, the loading of the old value inside the loop in the
+32-bit case is unnecessary: if the value doesn't match, the CMPXCHG8B
+instruction will already have loaded the "new previous" value for us.
+
+Clean up the comment, too, and remove page references to obsolete
+versions of the Intel SDM.
+
+Signed-off-by: H. Peter Anvin <hpa@zytor.com>
+LKML-Reference: <tip-*@vger.kernel.org>
+Tested-by: Mark Stanovich <mrktimber@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ arch/x86/include/asm/cmpxchg_32.h | 67 +++++++++++---------------------------
+ arch/x86/include/asm/cmpxchg_64.h | 4 --
+ 2 files changed, 21 insertions(+), 50 deletions(-)
+
+--- a/arch/x86/include/asm/cmpxchg_32.h
++++ b/arch/x86/include/asm/cmpxchg_32.h
+@@ -53,60 +53,33 @@ struct __xchg_dummy {
+ __xchg((v), (ptr), sizeof(*ptr))
+
+ /*
+- * The semantics of XCHGCMP8B are a bit strange, this is why
+- * there is a loop and the loading of %%eax and %%edx has to
+- * be inside. This inlines well in most cases, the cached
+- * cost is around ~38 cycles. (in the future we might want
+- * to do an SIMD/3DNOW!/MMX/FPU 64-bit store here, but that
+- * might have an implicit FPU-save as a cost, so it's not
+- * clear which path to go.)
++ * CMPXCHG8B only writes to the target if we had the previous
++ * value in registers, otherwise it acts as a read and gives us the
++ * "new previous" value. That is why there is a loop. Preloading
++ * EDX:EAX is a performance optimization: in the common case it means
++ * we need only one locked operation.
+ *
+- * cmpxchg8b must be used with the lock prefix here to allow
+- * the instruction to be executed atomically, see page 3-102
+- * of the instruction set reference 24319102.pdf. We need
+- * the reader side to see the coherent 64bit value.
++ * A SIMD/3DNOW!/MMX/FPU 64-bit store here would require at the very
++ * least an FPU save and/or %cr0.ts manipulation.
++ *
++ * cmpxchg8b must be used with the lock prefix here to allow the
++ * instruction to be executed atomically. We need to have the reader
++ * side to see the coherent 64bit value.
+ */
+-static inline void __set_64bit(unsigned long long *ptr,
+- unsigned int low, unsigned int high)
++static inline void set_64bit(volatile u64 *ptr, u64 value)
+ {
++ u32 low = value;
++ u32 high = value >> 32;
++ u64 prev = *ptr;
++
+ asm volatile("\n1:\t"
+- "movl (%1), %%eax\n\t"
+- "movl 4(%1), %%edx\n\t"
+- LOCK_PREFIX "cmpxchg8b (%1)\n\t"
++ LOCK_PREFIX "cmpxchg8b %0\n\t"
+ "jnz 1b"
+- : "=m" (*ptr)
+- : "D" (ptr),
+- "b" (low),
+- "c" (high)
+- : "ax", "dx", "memory");
+-}
+-
+-static inline void __set_64bit_constant(unsigned long long *ptr,
+- unsigned long long value)
+-{
+- __set_64bit(ptr, (unsigned int)value, (unsigned int)(value >> 32));
++ : "=m" (*ptr), "+A" (prev)
++ : "b" (low), "c" (high)
++ : "memory");
+ }
+
+-#define ll_low(x) *(((unsigned int *)&(x)) + 0)
+-#define ll_high(x) *(((unsigned int *)&(x)) + 1)
+-
+-static inline void __set_64bit_var(unsigned long long *ptr,
+- unsigned long long value)
+-{
+- __set_64bit(ptr, ll_low(value), ll_high(value));
+-}
+-
+-#define set_64bit(ptr, value) \
+- (__builtin_constant_p((value)) \
+- ? __set_64bit_constant((ptr), (value)) \
+- : __set_64bit_var((ptr), (value)))
+-
+-#define _set_64bit(ptr, value) \
+- (__builtin_constant_p(value) \
+- ? __set_64bit(ptr, (unsigned int)(value), \
+- (unsigned int)((value) >> 32)) \
+- : __set_64bit(ptr, ll_low((value)), ll_high((value))))
+-
+ extern void __cmpxchg_wrong_size(void);
+
+ /*
+--- a/arch/x86/include/asm/cmpxchg_64.h
++++ b/arch/x86/include/asm/cmpxchg_64.h
+@@ -5,13 +5,11 @@
+
+ #define __xg(x) ((volatile long *)(x))
+
+-static inline void set_64bit(volatile unsigned long *ptr, unsigned long val)
++static inline void set_64bit(volatile u64 *ptr, u64 val)
+ {
+ *ptr = val;
+ }
+
+-#define _set_64bit set_64bit
+-
+ extern void __xchg_wrong_size(void);
+ extern void __cmpxchg_wrong_size(void);
+
projects / thirdparty / kernel / stable-queue.git / commitdiff
