LoongArch: Don't emit dbar 0x700 if -mld-seq-sa

This option (CPUCFG word 0x3 bit 23) means "the hardware guarantee that
two loads on the same address won't be reordered with each other".  Thus
we can omit the "load-load" barrier dbar 0x700.

This is only a micro-optimization because dbar 0x700 is already treated
as nop if the hardware supports LD_SEQ_SA.

gcc/ChangeLog:

	* config/loongarch/loongarch.cc (loongarch_print_operand): Don't
	print dbar 0x700 if TARGET_LD_SEQ_SA.
	* config/loongarch/sync.md (atomic_load<mode>): Likewise.

diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index 9a2da89db789b93fb1b9a20d3ee20310fd7b0211..4a6a6e33e67b3d41e8f55a5e49ee780c733c3c27 100644 (file)
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -6061,7 +6061,7 @@ loongarch_print_operand (FILE *file, rtx op, int letter)
       if (loongarch_cas_failure_memorder_needs_acquire (
            memmodel_from_int (INTVAL (op))))
        fputs ("dbar\t0b10100", file);
-      else
+      else if (!TARGET_LD_SEQ_SA)
        fputs ("dbar\t0x700", file);
       break;
 

diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md
index 67848d72b875d825359c130c6e095d8e30d6715e..ce3ce89a61d7680cd934eb3a51d50d0f87236258 100644 (file)
--- a/gcc/config/loongarch/sync.md
+++ b/gcc/config/loongarch/sync.md
@@ -119,13 +119,14 @@
     case MEMMODEL_SEQ_CST:
       return "dbar\t0x11\\n\\t"
             "ld.<size>\t%0,%1\\n\\t"
-            "dbar\t0x14\\n\\t";
+            "dbar\t0x14";
     case MEMMODEL_ACQUIRE:
       return "ld.<size>\t%0,%1\\n\\t"
-            "dbar\t0x14\\n\\t";
+            "dbar\t0x14";
     case MEMMODEL_RELAXED:
-      return "ld.<size>\t%0,%1\\n\\t"
-            "dbar\t0x700\\n\\t";
+      return TARGET_LD_SEQ_SA ? "ld.<size>\t%0,%1\\n\\t"
+                             : "ld.<size>\t%0,%1\\n\\t"
+                               "dbar\t0x700";
 
     default:
       /* The valid memory order variants are __ATOMIC_RELAXED, __ATOMIC_SEQ_CST,