--- /dev/null
+From 2163e61c92d9337e721a0d067d88ae62b52e0d3e Mon Sep 17 00:00:00 2001
+From: Arnaud Ebalard <arno@natisbad.org>
+Date: Tue, 5 Nov 2013 21:46:02 +0100
+Subject: ARM: mvebu: fix second and third PCIe unit of Armada XP mv78260
+
+From: Arnaud Ebalard <arno@natisbad.org>
+
+commit 2163e61c92d9337e721a0d067d88ae62b52e0d3e upstream.
+
+mv78260 flavour of Marvell Armada XP SoC has 3 PCIe units. The
+two first units are both x4 and quad x1 capable. The third unit
+is only x4 capable. This patch fixes mv78260 .dtsi to reflect
+those capabilities.
+
+Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
+Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Signed-off-by: Jason Cooper <jason@lakedaemon.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/boot/dts/armada-xp-mv78260.dtsi | 78 +++++++++++++++++++++++++------
+ 1 file changed, 64 insertions(+), 14 deletions(-)
+
+--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
++++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+@@ -101,7 +101,7 @@
+ /*
+ * MV78260 has 3 PCIe units Gen2.0: Two units can be
+ * configured as x4 or quad x1 lanes. One unit is
+- * x4/x1.
++ * x4 only.
+ */
+ pcie-controller {
+ compatible = "marvell,armada-xp-pcie";
+@@ -119,7 +119,9 @@
+ 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
+ 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
+ 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
+- 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
++ 0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */
++ 0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */
++ 0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */
+ 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
+ 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
+
+@@ -187,35 +189,83 @@
+ status = "disabled";
+ };
+
+- pcie@9,0 {
++ pcie@5,0 {
+ device_type = "pci";
+- assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
+- reg = <0x4800 0 0 0 0>;
++ assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
++ reg = <0x2800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+- interrupt-map = <0 0 0 0 &mpic 99>;
+- marvell,pcie-port = <2>;
++ interrupt-map = <0 0 0 0 &mpic 62>;
++ marvell,pcie-port = <1>;
+ marvell,pcie-lane = <0>;
+- clocks = <&gateclk 26>;
++ clocks = <&gateclk 9>;
++ status = "disabled";
++ };
++
++ pcie@6,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
++ reg = <0x3000 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &mpic 63>;
++ marvell,pcie-port = <1>;
++ marvell,pcie-lane = <1>;
++ clocks = <&gateclk 10>;
++ status = "disabled";
++ };
++
++ pcie@7,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
++ reg = <0x3800 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &mpic 64>;
++ marvell,pcie-port = <1>;
++ marvell,pcie-lane = <2>;
++ clocks = <&gateclk 11>;
+ status = "disabled";
+ };
+
+- pcie@10,0 {
++ pcie@8,0 {
+ device_type = "pci";
+- assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
+- reg = <0x5000 0 0 0 0>;
++ assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
++ reg = <0x4000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+- interrupt-map = <0 0 0 0 &mpic 103>;
+- marvell,pcie-port = <3>;
++ interrupt-map = <0 0 0 0 &mpic 65>;
++ marvell,pcie-port = <1>;
++ marvell,pcie-lane = <3>;
++ clocks = <&gateclk 12>;
++ status = "disabled";
++ };
++
++ pcie@9,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
++ reg = <0x4800 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &mpic 99>;
++ marvell,pcie-port = <2>;
+ marvell,pcie-lane = <0>;
+- clocks = <&gateclk 27>;
++ clocks = <&gateclk 26>;
+ status = "disabled";
+ };
+ };
--- /dev/null
+From 12b69a599745fc9e203f61fbb7160b2cc5f479dd Mon Sep 17 00:00:00 2001
+From: Arnaud Ebalard <arno@natisbad.org>
+Date: Tue, 5 Nov 2013 21:45:48 +0100
+Subject: ARM: mvebu: second PCIe unit of Armada XP mv78230 is only x1 capable
+
+From: Arnaud Ebalard <arno@natisbad.org>
+
+commit 12b69a599745fc9e203f61fbb7160b2cc5f479dd upstream.
+
+Various Marvell datasheets advertise second PCIe unit of mv78230
+flavour of Armada XP as x4/quad x1 capable. This second unit is in
+fact only x1 capable. This patch fixes current mv78230 .dtsi to
+reflect that, i.e. makes 1.0 the second interface (instead of 2.0
+at the moment). This was successfully tested on a mv78230-based
+ReadyNAS 2120 platform with a x1 device (FL1009 XHCI controller)
+connected to this second interface.
+
+Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
+Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Signed-off-by: Jason Cooper <jason@lakedaemon.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/boot/dts/armada-xp-mv78230.dtsi | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
++++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+@@ -81,7 +81,7 @@
+ /*
+ * MV78230 has 2 PCIe units Gen2.0: One unit can be
+ * configured as x4 or quad x1 lanes. One unit is
+- * x4/x1.
++ * x1 only.
+ */
+ pcie-controller {
+ compatible = "marvell,armada-xp-pcie";
+@@ -94,10 +94,10 @@
+ bus-range = <0x00 0xff>;
+
+ ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
+- 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
+ 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
+ 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
+ 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
++ 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
+ 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
+ 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
+
+@@ -165,19 +165,19 @@
+ status = "disabled";
+ };
+
+- pcie@9,0 {
++ pcie@5,0 {
+ device_type = "pci";
+- assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
+- reg = <0x4800 0 0 0 0>;
++ assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
++ reg = <0x2800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 0>;
+- interrupt-map = <0 0 0 0 &mpic 99>;
+- marvell,pcie-port = <2>;
++ interrupt-map = <0 0 0 0 &mpic 62>;
++ marvell,pcie-port = <1>;
+ marvell,pcie-lane = <0>;
+- clocks = <&gateclk 26>;
++ clocks = <&gateclk 9>;
+ status = "disabled";
+ };
+ };
--- /dev/null
+From 9aa5b0181bdf335f0b731d8502e128a862884bcd Mon Sep 17 00:00:00 2001
+From: Alan Cox <alan@linux.intel.com>
+Date: Tue, 3 Dec 2013 13:56:56 -0800
+Subject: drivers/char/i8k.c: add Dell XPLS L421X
+
+From: Alan Cox <alan@linux.intel.com>
+
+commit 9aa5b0181bdf335f0b731d8502e128a862884bcd upstream.
+
+Addresses https://bugzilla.kernel.org/show_bug.cgi?id=60772
+
+Signed-off-by: Alan Cox <alan@linux.intel.com>
+Reported-by: Leho Kraav <leho@kraav.com>
+Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/char/i8k.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/drivers/char/i8k.c
++++ b/drivers/char/i8k.c
+@@ -664,6 +664,13 @@ static struct dmi_system_id __initdata i
+ DMI_MATCH(DMI_PRODUCT_NAME, "Vostro"),
+ },
+ },
++ {
++ .ident = "Dell XPS421",
++ .matches = {
++ DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
++ DMI_MATCH(DMI_PRODUCT_NAME, "XPS L421X"),
++ },
++ },
+ { }
+ };
+
mei-me-add-lynx-point-wellsburg-work-station-device-id.patch
mei-add-9-series-pch-mei-device-ids.patch
usb-pl2303-fixed-handling-of-cs5-setting.patch
+usb-ftdi_sio-fixed-handling-of-unsupported-csize-setting.patch
+usb-mos7840-correct-handling-of-cs5-setting.patch
+usb-spcp8x5-correct-handling-of-cs5-setting.patch
+usb-cdc-acm-added-support-for-the-lenovo-rd02-d400-usb-modem.patch
+drivers-char-i8k.c-add-dell-xpls-l421x.patch
+arm-mvebu-fix-second-and-third-pcie-unit-of-armada-xp-mv78260.patch
+arm-mvebu-second-pcie-unit-of-armada-xp-mv78230-is-only-x1-capable.patch
--- /dev/null
+From 3b59d16c513da258ec8f6a0b4db85f257a0380d6 Mon Sep 17 00:00:00 2001
+From: David Cluytens <david.cluytens@gmail.com>
+Date: Tue, 3 Dec 2013 14:18:57 +0100
+Subject: USB: cdc-acm: Added support for the Lenovo RD02-D400 USB Modem
+
+From: David Cluytens <david.cluytens@gmail.com>
+
+commit 3b59d16c513da258ec8f6a0b4db85f257a0380d6 upstream.
+
+Signed-off-by: David Cluytens <david.cluytens@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/usb/class/cdc-acm.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/usb/class/cdc-acm.c
++++ b/drivers/usb/class/cdc-acm.c
+@@ -1529,6 +1529,8 @@ static int acm_reset_resume(struct usb_i
+
+ static const struct usb_device_id acm_ids[] = {
+ /* quirky and broken devices */
++ { USB_DEVICE(0x17ef, 0x7000), /* Lenovo USB modem */
++ .driver_info = NO_UNION_NORMAL, },/* has no union descriptor */
+ { USB_DEVICE(0x0870, 0x0001), /* Metricom GS Modem */
+ .driver_info = NO_UNION_NORMAL, /* has no union descriptor */
+ },
--- /dev/null
+From 8704211f65a2106ba01b6ac9727cdaf9ca11594c Mon Sep 17 00:00:00 2001
+From: Colin Leitner <colin.leitner@googlemail.com>
+Date: Tue, 5 Nov 2013 18:02:34 +0100
+Subject: USB: ftdi_sio: fixed handling of unsupported CSIZE setting
+
+From: Colin Leitner <colin.leitner@googlemail.com>
+
+commit 8704211f65a2106ba01b6ac9727cdaf9ca11594c upstream.
+
+FTDI UARTs support only 7 or 8 data bits. Until now the ftdi_sio driver would
+only report this limitation for CS6 to dmesg and fail to reflect this fact to
+tcgetattr.
+
+This patch reverts the unsupported CSIZE setting and reports the fact with less
+severance to dmesg for both CS5 and CS6.
+
+To test the patch it's sufficient to call
+
+ stty -F /dev/ttyUSB0 cs5
+
+which will succeed without the patch and report an error with the patch
+applied.
+
+As an additional fix this patch ensures that the control request will always
+include a data bit size.
+
+Signed-off-by: Colin Leitner <colin.leitner@gmail.com>
+Signed-off-by: Johan Hovold <jhovold@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/usb/serial/ftdi_sio.c | 37 ++++++++++++++++++++++++-------------
+ 1 file changed, 24 insertions(+), 13 deletions(-)
+
+--- a/drivers/usb/serial/ftdi_sio.c
++++ b/drivers/usb/serial/ftdi_sio.c
+@@ -2131,6 +2131,20 @@ static void ftdi_set_termios(struct tty_
+ termios->c_cflag |= CRTSCTS;
+ }
+
++ /*
++ * All FTDI UART chips are limited to CS7/8. We won't pretend to
++ * support CS5/6 and revert the CSIZE setting instead.
++ */
++ if ((C_CSIZE(tty) != CS8) && (C_CSIZE(tty) != CS7)) {
++ dev_warn(ddev, "requested CSIZE setting not supported\n");
++
++ termios->c_cflag &= ~CSIZE;
++ if (old_termios)
++ termios->c_cflag |= old_termios->c_cflag & CSIZE;
++ else
++ termios->c_cflag |= CS8;
++ }
++
+ cflag = termios->c_cflag;
+
+ if (!old_termios)
+@@ -2167,19 +2181,16 @@ no_skip:
+ } else {
+ urb_value |= FTDI_SIO_SET_DATA_PARITY_NONE;
+ }
+- if (cflag & CSIZE) {
+- switch (cflag & CSIZE) {
+- case CS7:
+- urb_value |= 7;
+- dev_dbg(ddev, "Setting CS7\n");
+- break;
+- case CS8:
+- urb_value |= 8;
+- dev_dbg(ddev, "Setting CS8\n");
+- break;
+- default:
+- dev_err(ddev, "CSIZE was set but not CS7-CS8\n");
+- }
++ switch (cflag & CSIZE) {
++ case CS7:
++ urb_value |= 7;
++ dev_dbg(ddev, "Setting CS7\n");
++ break;
++ default:
++ case CS8:
++ urb_value |= 8;
++ dev_dbg(ddev, "Setting CS8\n");
++ break;
+ }
+
+ /* This is needed by the break command since it uses the same command
--- /dev/null
+From 78692cc3382e0603a47e1f2aaeffe0d99891994d Mon Sep 17 00:00:00 2001
+From: Colin Leitner <colin.leitner@googlemail.com>
+Date: Fri, 8 Nov 2013 22:52:34 +0100
+Subject: USB: mos7840: correct handling of CS5 setting
+
+From: Colin Leitner <colin.leitner@googlemail.com>
+
+commit 78692cc3382e0603a47e1f2aaeffe0d99891994d upstream.
+
+This patch removes an erroneous check of CSIZE, which made it impossible to set
+CS5.
+
+Compiles clean, but couldn't test against hardware.
+
+Signed-off-by: Colin Leitner <colin.leitner@gmail.com>
+Signed-off-by: Johan Hovold <jhovold@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/usb/serial/mos7840.c | 32 ++++++++++++++++----------------
+ 1 file changed, 16 insertions(+), 16 deletions(-)
+
+--- a/drivers/usb/serial/mos7840.c
++++ b/drivers/usb/serial/mos7840.c
+@@ -1875,25 +1875,25 @@ static void mos7840_change_port_settings
+ iflag = tty->termios.c_iflag;
+
+ /* Change the number of bits */
+- if (cflag & CSIZE) {
+- switch (cflag & CSIZE) {
+- case CS5:
+- lData = LCR_BITS_5;
+- break;
++ switch (cflag & CSIZE) {
++ case CS5:
++ lData = LCR_BITS_5;
++ break;
+
+- case CS6:
+- lData = LCR_BITS_6;
+- break;
++ case CS6:
++ lData = LCR_BITS_6;
++ break;
+
+- case CS7:
+- lData = LCR_BITS_7;
+- break;
+- default:
+- case CS8:
+- lData = LCR_BITS_8;
+- break;
+- }
++ case CS7:
++ lData = LCR_BITS_7;
++ break;
++
++ default:
++ case CS8:
++ lData = LCR_BITS_8;
++ break;
+ }
++
+ /* Change the Parity bit */
+ if (cflag & PARENB) {
+ if (cflag & PARODD) {
--- /dev/null
+From 711fbdfbf2bc4827214a650afe3f64767a1aba16 Mon Sep 17 00:00:00 2001
+From: Colin Leitner <colin.leitner@googlemail.com>
+Date: Fri, 8 Nov 2013 22:53:11 +0100
+Subject: USB: spcp8x5: correct handling of CS5 setting
+
+From: Colin Leitner <colin.leitner@googlemail.com>
+
+commit 711fbdfbf2bc4827214a650afe3f64767a1aba16 upstream.
+
+This patch removes an erroneous check of CSIZE, which made it impossible to set
+CS5.
+
+Compiles clean, but couldn't test against hardware.
+
+Signed-off-by: Colin Leitner <colin.leitner@gmail.com>
+Signed-off-by: Johan Hovold <jhovold@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/usb/serial/spcp8x5.c | 30 ++++++++++++++----------------
+ 1 file changed, 14 insertions(+), 16 deletions(-)
+
+--- a/drivers/usb/serial/spcp8x5.c
++++ b/drivers/usb/serial/spcp8x5.c
+@@ -346,22 +346,20 @@ static void spcp8x5_set_termios(struct t
+ }
+
+ /* Set Data Length : 00:5bit, 01:6bit, 10:7bit, 11:8bit */
+- if (cflag & CSIZE) {
+- switch (cflag & CSIZE) {
+- case CS5:
+- buf[1] |= SET_UART_FORMAT_SIZE_5;
+- break;
+- case CS6:
+- buf[1] |= SET_UART_FORMAT_SIZE_6;
+- break;
+- case CS7:
+- buf[1] |= SET_UART_FORMAT_SIZE_7;
+- break;
+- default:
+- case CS8:
+- buf[1] |= SET_UART_FORMAT_SIZE_8;
+- break;
+- }
++ switch (cflag & CSIZE) {
++ case CS5:
++ buf[1] |= SET_UART_FORMAT_SIZE_5;
++ break;
++ case CS6:
++ buf[1] |= SET_UART_FORMAT_SIZE_6;
++ break;
++ case CS7:
++ buf[1] |= SET_UART_FORMAT_SIZE_7;
++ break;
++ default:
++ case CS8:
++ buf[1] |= SET_UART_FORMAT_SIZE_8;
++ break;
+ }
+
+ /* Set Stop bit2 : 0:1bit 1:2bit */
projects / thirdparty / kernel / stable-queue.git / commitdiff
