RISC-V: Refine signed vector SAT_ADD testcase dump check to tree optimized

The sat alu related testcase check the rtl dump for the standard name
like .SAT_ADD exist or not.  But the rtl pass expand is somehow
impressionable by the middle-end change or debug information.  Like
below new appearance recently.

Replacing Expressions
_5 replace with --> _5 = .SAT_ADD (x_3(D), y_4(D)); [tail call]

After that we need to adjust the dump check time and again.  This
patch would like to switch to tree optimized pass for the standard
name check, which is more stable up to a point.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c: Take
	tree-optimized pass for standard name check, and adjust the times.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c
index 6ef8ecbc17019c8da75ac1f41ce57a9371314e3f..6147e7ab56eeed2893d15e653e534e0aa5ec4f67 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c
@@ -1,10 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_ADD_FMT_1(int16_t, uint16_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c
index 46a4b6fdbd08cc59902a56e266777f40383d4fc3..2312b5b607439a594b5d1bb0d956b7d4f5189e41 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c
@@ -1,10 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_ADD_FMT_1(int32_t, uint32_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c
index 43c0e63062497ed48848dc89db579ffb0623b138..820bbaca52a1b08915d2cf78b18d9f9050e5ba92 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c
@@ -1,10 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_ADD_FMT_1(int64_t, uint64_t, INT64_MIN, INT64_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c
index cc2bd5c9a79c29e38d93740e494f0cd499068830..5fd4741ee47f68cc3a7eab82c4a5a4f7a02be388 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c
@@ -1,10 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_ADD_FMT_1(int8_t, uint8_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c
index 4c496300d8e6926b28a1621e45d31ea9e5c3816e..f838dfc1e297ae78043a6cdb4cb2e2b9d9a48eb6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c
@@ -1,10 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_ADD_FMT_2(int16_t, uint16_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c
index 34d25f7a46dca2ebdf2b1522f42311aeb1a38b1a..64b4d953b294f99349ce65d6a1b1a9d4bd00eae9 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c
@@ -1,10 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_ADD_FMT_2(int32_t, uint32_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c
index 28544471a994ee3102adea0ddf589ad5b1effc1f..2daf299775ae04b7ac22e29db91ef86ca91eab35 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c
@@ -1,10 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_ADD_FMT_2(int64_t, uint64_t, INT64_MIN, INT64_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c
index 0bba22667e4cf5ef974609d2d8ef8452b2cb8c16..7d2c290f18ddc715976719363a33bc8ff265207b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c
@@ -1,10 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_ADD_FMT_2(int8_t, uint8_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c
index ccbe65a330e83c388d6ebe58a39960f3c4bc9c5d..de121556891b78af82fbd050f2e35a67c5e5b999 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c
@@ -1,10 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_ADD_FMT_3(int16_t, uint16_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c
index d1c67c8cbe0d92e9d91e6f6ac9c0082b9c6e7af6..187c8b1f62f53923c81678e4f4797a42be5bcddc 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c
@@ -1,10 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_ADD_FMT_3(int32_t, uint32_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c
index 49ca8d6d26e4b8ba184050eb8ca3af40ea97c23f..61ca265125a105d86de8eabe3afb57d549f39cd5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c
@@ -1,10 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_ADD_FMT_3(int64_t, uint64_t, INT64_MIN, INT64_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c
index 3a2c887983ce2a178a4d8cd84c9c07daa659200a..eaffe5f4fd104ba28d954487d6901fb8cd9da563 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c
@@ -1,10 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_ADD_FMT_3(int8_t, uint8_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c
index aa13604ca2797a1e06d588f7e29ab08c1ede8d58..9808fc5be1ef1b21fb1c8c6d5bed59a0724d7363 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c
@@ -1,10 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_ADD_FMT_4(int16_t, uint16_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c
index 2f47e5ba5498077d44080da7e49d95bee0269c29..ab691cbc2c73f7c44096956d55650c31b1336d67 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c
@@ -1,10 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_ADD_FMT_4(int32_t, uint32_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c
index 1a943d2404f3c584b0cbd42a313e2ba4ab6f4a84..30326886a80696fc7c8e7c506bbe5f893333d895 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c
@@ -1,10 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_ADD_FMT_4(int64_t, uint64_t, INT64_MIN, INT64_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c
index 9ec120df69d859f546e7467a9d6e62a218811173..928b4b66867baf33ed9ff41767ab89d9465c0e57 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c
@@ -1,10 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_ADD_FMT_4(int8_t, uint8_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */