--- /dev/null
+From 691505a803a7f223b2af621848d581259c61f77d Mon Sep 17 00:00:00 2001
+From: Mark Salter <msalter@redhat.com>
+Date: Mon, 21 Oct 2019 11:29:49 -0400
+Subject: crypto: ccp - fix uninitialized list head
+
+From: Mark Salter <msalter@redhat.com>
+
+commit 691505a803a7f223b2af621848d581259c61f77d upstream.
+
+A NULL-pointer dereference was reported in fedora bz#1762199 while
+reshaping a raid6 array after adding a fifth drive to an existing
+array.
+
+[ 47.343549] md/raid:md0: raid level 6 active with 3 out of 5 devices, algorithm 2
+[ 47.804017] md0: detected capacity change from 0 to 7885289422848
+[ 47.822083] Unable to handle kernel read from unreadable memory at virtual address 0000000000000000
+...
+[ 47.940477] CPU: 1 PID: 14210 Comm: md0_raid6 Tainted: G W 5.2.18-200.fc30.aarch64 #1
+[ 47.949594] Hardware name: AMD Overdrive/Supercharger/To be filled by O.E.M., BIOS ROD1002C 04/08/2016
+[ 47.958886] pstate: 00400085 (nzcv daIf +PAN -UAO)
+[ 47.963668] pc : __list_del_entry_valid+0x2c/0xa8
+[ 47.968366] lr : ccp_tx_submit+0x84/0x168 [ccp]
+[ 47.972882] sp : ffff00001369b970
+[ 47.976184] x29: ffff00001369b970 x28: ffff00001369bdb8
+[ 47.981483] x27: 00000000ffffffff x26: ffff8003b758af70
+[ 47.986782] x25: ffff8003b758b2d8 x24: ffff8003e6245818
+[ 47.992080] x23: 0000000000000000 x22: ffff8003e62450c0
+[ 47.997379] x21: ffff8003dfd6add8 x20: 0000000000000003
+[ 48.002678] x19: ffff8003e6245100 x18: 0000000000000000
+[ 48.007976] x17: 0000000000000000 x16: 0000000000000000
+[ 48.013274] x15: 0000000000000000 x14: 0000000000000000
+[ 48.018572] x13: ffff7e000ef83a00 x12: 0000000000000001
+[ 48.023870] x11: ffff000010eff998 x10: 00000000000019a0
+[ 48.029169] x9 : 0000000000000000 x8 : ffff8003e6245180
+[ 48.034467] x7 : 0000000000000000 x6 : 000000000000003f
+[ 48.039766] x5 : 0000000000000040 x4 : ffff8003e0145080
+[ 48.045064] x3 : dead000000000200 x2 : 0000000000000000
+[ 48.050362] x1 : 0000000000000000 x0 : ffff8003e62450c0
+[ 48.055660] Call trace:
+[ 48.058095] __list_del_entry_valid+0x2c/0xa8
+[ 48.062442] ccp_tx_submit+0x84/0x168 [ccp]
+[ 48.066615] async_tx_submit+0x224/0x368 [async_tx]
+[ 48.071480] async_trigger_callback+0x68/0xfc [async_tx]
+[ 48.076784] ops_run_biofill+0x178/0x1e8 [raid456]
+[ 48.081566] raid_run_ops+0x248/0x818 [raid456]
+[ 48.086086] handle_stripe+0x864/0x1208 [raid456]
+[ 48.090781] handle_active_stripes.isra.0+0xb0/0x278 [raid456]
+[ 48.096604] raid5d+0x378/0x618 [raid456]
+[ 48.100602] md_thread+0xa0/0x150
+[ 48.103905] kthread+0x104/0x130
+[ 48.107122] ret_from_fork+0x10/0x18
+[ 48.110686] Code: d2804003 f2fbd5a3 eb03003f 54000320 (f9400021)
+[ 48.116766] ---[ end trace 23f390a527f7ad77 ]---
+
+ccp_tx_submit is passed a dma_async_tx_descriptor which is contained in
+a ccp_dma_desc and adds it to a ccp channel's pending list:
+
+ list_del(&desc->entry);
+ list_add_tail(&desc->entry, &chan->pending);
+
+The problem is that desc->entry may be uninitialized in the
+async_trigger_callback path where the descriptor was gotten
+from ccp_prep_dma_interrupt which got it from ccp_alloc_dma_desc
+which doesn't initialize the desc->entry list head. So, just
+initialize the list head to avoid the problem.
+
+Cc: <stable@vger.kernel.org>
+Reported-by: Sahaj Sarup <sahajsarup@gmail.com>
+Signed-off-by: Mark Salter <msalter@redhat.com>
+Acked-by: Gary R Hook <gary.hook@amd.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/crypto/ccp/ccp-dmaengine.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/crypto/ccp/ccp-dmaengine.c
++++ b/drivers/crypto/ccp/ccp-dmaengine.c
+@@ -309,6 +309,7 @@ static struct ccp_dma_desc *ccp_alloc_dm
+ desc->tx_desc.flags = flags;
+ desc->tx_desc.tx_submit = ccp_tx_submit;
+ desc->ccp = chan->ccp;
++ INIT_LIST_HEAD(&desc->entry);
+ INIT_LIST_HEAD(&desc->pending);
+ INIT_LIST_HEAD(&desc->active);
+ desc->status = DMA_IN_PROGRESS;
--- /dev/null
+From 746c908c4d72e49068ab216c3926d2720d71a90d Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Thu, 31 Oct 2019 17:14:38 +0100
+Subject: crypto: crypto4xx - fix double-free in crypto4xx_destroy_sdr
+
+From: Christian Lamparter <chunkeey@gmail.com>
+
+commit 746c908c4d72e49068ab216c3926d2720d71a90d upstream.
+
+This patch fixes a crash that can happen during probe
+when the available dma memory is not enough (this can
+happen if the crypto4xx is built as a module).
+
+The descriptor window mapping would end up being free'd
+twice, once in crypto4xx_build_pdr() and the second time
+in crypto4xx_destroy_sdr().
+
+Fixes: 5d59ad6eea82 ("crypto: crypto4xx - fix crypto4xx_build_pdr, crypto4xx_build_sdr leak")
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/crypto/amcc/crypto4xx_core.c | 6 +-----
+ 1 file changed, 1 insertion(+), 5 deletions(-)
+
+--- a/drivers/crypto/amcc/crypto4xx_core.c
++++ b/drivers/crypto/amcc/crypto4xx_core.c
+@@ -400,12 +400,8 @@ static u32 crypto4xx_build_sdr(struct cr
+ dma_alloc_coherent(dev->core_dev->device,
+ dev->scatter_buffer_size * PPC4XX_NUM_SD,
+ &dev->scatter_buffer_pa, GFP_ATOMIC);
+- if (!dev->scatter_buffer_va) {
+- dma_free_coherent(dev->core_dev->device,
+- sizeof(struct ce_sd) * PPC4XX_NUM_SD,
+- dev->sdr, dev->sdr_pa);
++ if (!dev->scatter_buffer_va)
+ return -ENOMEM;
+- }
+
+ sd_array = dev->sdr;
+
--- /dev/null
+From f398243e9fd6a3a059c1ea7b380c40628dbf0c61 Mon Sep 17 00:00:00 2001
+From: Ard Biesheuvel <ardb@kernel.org>
+Date: Wed, 23 Oct 2019 11:50:44 +0200
+Subject: crypto: ecdh - fix big endian bug in ECC library
+
+From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+
+commit f398243e9fd6a3a059c1ea7b380c40628dbf0c61 upstream.
+
+The elliptic curve arithmetic library used by the EC-DH KPP implementation
+assumes big endian byte order, and unconditionally reverses the byte
+and word order of multi-limb quantities. On big endian systems, the byte
+reordering is not necessary, while the word ordering needs to be retained.
+
+So replace the __swab64() invocation with a call to be64_to_cpu() which
+should do the right thing for both little and big endian builds.
+
+Fixes: 3c4b23901a0c ("crypto: ecdh - Add ECDH software support")
+Cc: <stable@vger.kernel.org> # v4.9+
+Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ crypto/ecc.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/crypto/ecc.c
++++ b/crypto/ecc.c
+@@ -897,10 +897,11 @@ static void ecc_point_mult(struct ecc_po
+ static inline void ecc_swap_digits(const u64 *in, u64 *out,
+ unsigned int ndigits)
+ {
++ const __be64 *src = (__force __be64 *)in;
+ int i;
+
+ for (i = 0; i < ndigits; i++)
+- out[i] = __swab64(in[ndigits - 1 - i]);
++ out[i] = be64_to_cpu(src[ndigits - 1 - i]);
+ }
+
+ int ecc_is_key_valid(unsigned int curve_id, unsigned int ndigits,
--- /dev/null
+From ffdde5932042600c6807d46c1550b28b0db6a3bc Mon Sep 17 00:00:00 2001
+From: Navid Emamdoost <navid.emamdoost@gmail.com>
+Date: Fri, 4 Oct 2019 14:29:16 -0500
+Subject: crypto: user - fix memory leak in crypto_report
+
+From: Navid Emamdoost <navid.emamdoost@gmail.com>
+
+commit ffdde5932042600c6807d46c1550b28b0db6a3bc upstream.
+
+In crypto_report, a new skb is created via nlmsg_new(). This skb should
+be released if crypto_report_alg() fails.
+
+Fixes: a38f7907b926 ("crypto: Add userspace configuration API")
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Navid Emamdoost <navid.emamdoost@gmail.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ crypto/crypto_user.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/crypto/crypto_user.c
++++ b/crypto/crypto_user.c
+@@ -269,8 +269,10 @@ static int crypto_report(struct sk_buff
+ drop_alg:
+ crypto_mod_put(alg);
+
+- if (err)
++ if (err) {
++ kfree_skb(skb);
+ return err;
++ }
+
+ return nlmsg_unicast(crypto_nlsk, skb, NETLINK_CB(in_skb).portid);
+ }
--- /dev/null
+From 4f69851fbaa26b155330be35ce8ac393e93e7442 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Fri, 4 Oct 2019 13:22:51 +0300
+Subject: drm/i810: Prevent underflow in ioctl
+
+From: Dan Carpenter <dan.carpenter@oracle.com>
+
+commit 4f69851fbaa26b155330be35ce8ac393e93e7442 upstream.
+
+The "used" variables here come from the user in the ioctl and it can be
+negative. It could result in an out of bounds write.
+
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Link: https://patchwork.freedesktop.org/patch/msgid/20191004102251.GC823@mwanda
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i810/i810_dma.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/i810/i810_dma.c
++++ b/drivers/gpu/drm/i810/i810_dma.c
+@@ -723,7 +723,7 @@ static void i810_dma_dispatch_vertex(str
+ if (nbox > I810_NR_SAREA_CLIPRECTS)
+ nbox = I810_NR_SAREA_CLIPRECTS;
+
+- if (used > 4 * 1024)
++ if (used < 0 || used > 4 * 1024)
+ used = 0;
+
+ if (sarea_priv->dirty)
+@@ -1043,7 +1043,7 @@ static void i810_dma_dispatch_mc(struct
+ if (u != I810_BUF_CLIENT)
+ DRM_DEBUG("MC found buffer that isn't mine!\n");
+
+- if (used > 4 * 1024)
++ if (used < 0 || used > 4 * 1024)
+ used = 0;
+
+ sarea_priv->dirty = 0x7f;
--- /dev/null
+From de1fca5d6e0105c9d33924e1247e2f386efc3ece Mon Sep 17 00:00:00 2001
+From: Paolo Bonzini <pbonzini@redhat.com>
+Date: Mon, 18 Nov 2019 12:23:00 -0500
+Subject: KVM: x86: do not modify masked bits of shared MSRs
+
+From: Paolo Bonzini <pbonzini@redhat.com>
+
+commit de1fca5d6e0105c9d33924e1247e2f386efc3ece upstream.
+
+"Shared MSRs" are guest MSRs that are written to the host MSRs but
+keep their value until the next return to userspace. They support
+a mask, so that some bits keep the host value, but this mask is
+only used to skip an unnecessary MSR write and the value written
+to the MSR is always the guest MSR.
+
+Fix this and, while at it, do not update smsr->values[slot].curr if
+for whatever reason the wrmsr fails. This should only happen due to
+reserved bits, so the value written to smsr->values[slot].curr
+will not match when the user-return notifier and the host value will
+always be restored. However, it is untidy and in rare cases this
+can actually avoid spurious WRMSRs on return to userspace.
+
+Cc: stable@vger.kernel.org
+Reviewed-by: Jim Mattson <jmattson@google.com>
+Tested-by: Jim Mattson <jmattson@google.com>
+Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/x86/kvm/x86.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/arch/x86/kvm/x86.c
++++ b/arch/x86/kvm/x86.c
+@@ -273,13 +273,14 @@ int kvm_set_shared_msr(unsigned slot, u6
+ struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
+ int err;
+
+- if (((value ^ smsr->values[slot].curr) & mask) == 0)
++ value = (value & mask) | (smsr->values[slot].host & ~mask);
++ if (value == smsr->values[slot].curr)
+ return 0;
+- smsr->values[slot].curr = value;
+ err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
+ if (err)
+ return 1;
+
++ smsr->values[slot].curr = value;
+ if (!smsr->registered) {
+ smsr->urn.on_user_return = kvm_on_user_return;
+ user_return_notifier_register(&smsr->urn);
--- /dev/null
+From cbbaa2727aa3ae9e0a844803da7cef7fd3b94f2b Mon Sep 17 00:00:00 2001
+From: Paolo Bonzini <pbonzini@redhat.com>
+Date: Mon, 18 Nov 2019 18:58:26 +0100
+Subject: KVM: x86: fix presentation of TSX feature in ARCH_CAPABILITIES
+
+From: Paolo Bonzini <pbonzini@redhat.com>
+
+commit cbbaa2727aa3ae9e0a844803da7cef7fd3b94f2b upstream.
+
+KVM does not implement MSR_IA32_TSX_CTRL, so it must not be presented
+to the guests. It is also confusing to have !ARCH_CAP_TSX_CTRL_MSR &&
+!RTM && ARCH_CAP_TAA_NO: lack of MSR_IA32_TSX_CTRL suggests TSX was not
+hidden (it actually was), yet the value says that TSX is not vulnerable
+to microarchitectural data sampling. Fix both.
+
+Cc: stable@vger.kernel.org
+Tested-by: Jim Mattson <jmattson@google.com>
+Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/x86/kvm/x86.c | 9 +++++++--
+ 1 file changed, 7 insertions(+), 2 deletions(-)
+
+--- a/arch/x86/kvm/x86.c
++++ b/arch/x86/kvm/x86.c
+@@ -1075,10 +1075,15 @@ u64 kvm_get_arch_capabilities(void)
+ * If TSX is disabled on the system, guests are also mitigated against
+ * TAA and clear CPU buffer mitigation is not required for guests.
+ */
+- if (boot_cpu_has_bug(X86_BUG_TAA) && boot_cpu_has(X86_FEATURE_RTM) &&
+- (data & ARCH_CAP_TSX_CTRL_MSR))
++ if (!boot_cpu_has(X86_FEATURE_RTM))
++ data &= ~ARCH_CAP_TAA_NO;
++ else if (!boot_cpu_has_bug(X86_BUG_TAA))
++ data |= ARCH_CAP_TAA_NO;
++ else if (data & ARCH_CAP_TSX_CTRL_MSR)
+ data &= ~ARCH_CAP_MDS_NO;
+
++ /* KVM does not emulate MSR_IA32_TSX_CTRL. */
++ data &= ~ARCH_CAP_TSX_CTRL_MSR;
+ return data;
+ }
+
tty-vt-keyboard-reject-invalid-keycodes.patch
can-slcan-fix-use-after-free-read-in-slcan_open.patch
jbd2-fix-possible-overflow-in-jbd2_log_space_left.patch
+drm-i810-prevent-underflow-in-ioctl.patch
+kvm-x86-do-not-modify-masked-bits-of-shared-msrs.patch
+kvm-x86-fix-presentation-of-tsx-feature-in-arch_capabilities.patch
+crypto-crypto4xx-fix-double-free-in-crypto4xx_destroy_sdr.patch
+crypto-ccp-fix-uninitialized-list-head.patch
+crypto-ecdh-fix-big-endian-bug-in-ecc-library.patch
+crypto-user-fix-memory-leak-in-crypto_report.patch
+spi-atmel-fix-cs-high-support.patch
--- /dev/null
+From 7cbb16b2122c09f2ae393a1542fed628505b9da6 Mon Sep 17 00:00:00 2001
+From: Gregory CLEMENT <gregory.clement@bootlin.com>
+Date: Thu, 17 Oct 2019 16:18:41 +0200
+Subject: spi: atmel: Fix CS high support
+
+From: Gregory CLEMENT <gregory.clement@bootlin.com>
+
+commit 7cbb16b2122c09f2ae393a1542fed628505b9da6 upstream.
+
+Until a few years ago, this driver was only used with CS GPIO. The
+only exception is CS0 on AT91RM9200 which has to use internal CS. A
+limitation of the internal CS is that they don't support CS High.
+
+So by using the CS GPIO the CS high configuration was available except
+for the particular case CS0 on RM9200.
+
+When the support for the internal chip-select was added, the check of
+the CS high support was not updated. Due to this the driver accepts
+this configuration for all the SPI controller v2 (used by all SoCs
+excepting the AT91RM9200) whereas the hardware doesn't support it for
+infernal CS.
+
+This patch fixes the test to match the hardware capabilities.
+
+Fixes: 4820303480a1 ("spi: atmel: add support for the internal chip-select of the spi controller")
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
+Link: https://lore.kernel.org/r/20191017141846.7523-3-gregory.clement@bootlin.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/spi/spi-atmel.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+--- a/drivers/spi/spi-atmel.c
++++ b/drivers/spi/spi-atmel.c
+@@ -1209,10 +1209,8 @@ static int atmel_spi_setup(struct spi_de
+ as = spi_master_get_devdata(spi->master);
+
+ /* see notes above re chipselect */
+- if (!atmel_spi_is_v2(as)
+- && spi->chip_select == 0
+- && (spi->mode & SPI_CS_HIGH)) {
+- dev_dbg(&spi->dev, "setup: can't be active-high\n");
++ if (!as->use_cs_gpios && (spi->mode & SPI_CS_HIGH)) {
++ dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
+ return -EINVAL;
+ }
+
projects / thirdparty / kernel / stable-queue.git / commitdiff
