Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a7ca6d91239d042d3e4abb1a7d364012a673957a..e4a4ed4fc5dad6c857c6cf9233325dd0e13d7b4d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,33 @@
+2023-05-29  Die Li  <lidie@eswincomputing.com>
+
+       * config/riscv/riscv.cc (riscv_expand_conditional_move_onesided):
+       Delete.
+       (riscv_expand_conditional_move):  Reuse the TARGET_SFB_ALU expand
+       process for TARGET_XTHEADCONDMOV
+
+2023-05-29  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/110021
+       * config/i386/i386-expand.cc (ix86_expand_vecop_qihi2): Also require
+       TARGET_AVX512BW to generate truncv16hiv16qi2.
+
+2023-05-29  Jivan Hakobyan  <jivanhakobyan9@gmail.com>
+
+       * config/riscv/riscv.md (and<mode>3): New expander.
+       (*and<mode>3) New pattern.
+       * config/riscv/predicates.md (arith_operand_or_mode_mask): New
+       predicate.
+
+2023-05-29  Pan Li  <pan2.li@intel.com>
+
+       * config/riscv/riscv-v.cc (emit_vlmax_insn): Remove unnecessary
+       comments and rename local variables.
+       (emit_nonvlmax_insn): Diito.
+       (emit_vlmax_merge_insn): Ditto.
+       (emit_vlmax_cmp_insn): Ditto.
+       (emit_vlmax_cmp_mu_insn): Ditto.
+       (emit_scalar_move_insn): Ditto.
+
 2023-05-29  Pan Li  <pan2.li@intel.com>
 
        * config/riscv/riscv-v.cc (emit_vlmax_insn): Eliminate the

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 5f5439b6a420e26018065c226616dff2d968ee05..9de50cecbd7eac354b9077fb52e646e69c09fd8d 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230529
+20230530

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 406e6dee0a5d1964ab6c18f5bb2f6ae9c2bb7ee0..281b91cdc6c8c2ea66bd7a4d4987c7b65c33df90 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+2023-05-29  Die Li  <lidie@eswincomputing.com>
+
+       * gcc.target/riscv/xtheadcondmov-indirect-rv32.c: Update the output.
+       * gcc.target/riscv/xtheadcondmov-indirect-rv64.c: Likewise.
+
+2023-05-29  Jivan Hakobyan  <jivanhakobyan9@gmail.com>
+
+       * gcc.target/riscv/and-extend-1.c: New test
+       * gcc.target/riscv/and-extend-2.c: New test
+
 2023-05-29  Pan Li  <pan2.li@intel.com>
 
        * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-1.c: New test.