Correct vcmpsq, vcmpuq and xvtlsbb BF field

These shouldn't be optional.  The record form of vector instructions
set CR6, giving an expectation that omitting BF should be the same as
specifying CR6.

opcodes/
	* ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
	vcmpuq and xvtlsbb.
gas/
	* testsuite/gas/ppc/int128.s: Correct vcmpuq.
	* testsuite/gas/ppc/int128.d: Update.
	* testsuite/gas/ppc/xvtlsbb.d: Update.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index f624a68f5408333c24308f7a03161c8e0f780d6f..2746361c87b4af5e97f2de07a02514c98813c4a7 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2020-08-19  Alan Modra  <amodra@gmail.com>
+
+       * testsuite/gas/ppc/int128.s: Correct vcmpuq.
+       * testsuite/gas/ppc/int128.d: Update.
+       * testsuite/gas/ppc/xvtlsbb.d: Update.
+
 2020-08-18  Peter Bergner  <bergner@linux.ibm.com>
 
        * testsuite/gas/ppc/vsx4.s: Update test to use new mnemonic.

diff --git a/gas/testsuite/gas/ppc/int128.d b/gas/testsuite/gas/ppc/int128.d
index c9f14d3360d93e2470c9434c4947e5376afaad50..d7410345ad769641e88f111b2fd78176c89d1aa5 100644 (file)
--- a/gas/testsuite/gas/ppc/int128.d
+++ b/gas/testsuite/gas/ppc/int128.d
@@ -20,7 +20,7 @@ Disassembly of section \.text:
 .*:    (13 9d f7 0b|0b f7 9d 13)       vmodsq  v28,v29,v30
 .*:    (13 e0 0e 0b|0b 0e e0 13)       vmoduq  v31,v0,v1
 .*:    (10 5b 1e 02|02 1e 5b 10)       vextsd2q v2,v3
-.*:    (10 04 29 01|01 29 04 10)       vcmpuq  v4,v5
+.*:    (10 04 29 01|01 29 04 10)       vcmpuq  cr0,v4,v5
 .*:    (10 86 39 41|41 39 86 10)       vcmpsq  cr1,v6,v7
 .*:    (11 09 51 c7|c7 51 09 11)       vcmpequq v8,v9,v10
 .*:    (11 6c 6d c7|c7 6d 6c 11)       vcmpequq. v11,v12,v13

diff --git a/gas/testsuite/gas/ppc/int128.s b/gas/testsuite/gas/ppc/int128.s
index 4dce648c36f85f5100a2122350306fafd63c2aaf..4561cfe9ee646c7fc02f6df35305358300aa2507 100644 (file)
--- a/gas/testsuite/gas/ppc/int128.s
+++ b/gas/testsuite/gas/ppc/int128.s
@@ -12,7 +12,7 @@ _start:
        vmodsq  28,29,30
        vmoduq  31,0,1
        vextsd2q 2,3
-       vcmpuq  4,5
+       vcmpuq  0,4,5
        vcmpsq  1,6,7
        vcmpequq 8,9,10
        vcmpequq. 11,12,13

diff --git a/gas/testsuite/gas/ppc/xvtlsbb.d b/gas/testsuite/gas/ppc/xvtlsbb.d
index 1627d7afc6dbfeadb59e35cd2d4cd7a0b83d6a4f..8aa83dd62c7d9cc235f7afa6d7c693009657d2dc 100644 (file)
--- a/gas/testsuite/gas/ppc/xvtlsbb.d
+++ b/gas/testsuite/gas/ppc/xvtlsbb.d
@@ -7,7 +7,7 @@
 Disassembly of section \.text:
 
 0+0 <_start>:
-.*:    (f0 02 ff 6e|6e ff 02 f0)       xvtlsbb vs63
+.*:    (f0 02 ff 6e|6e ff 02 f0)       xvtlsbb cr0,vs63
 .*:    (f0 82 07 6c|6c 07 82 f0)       xvtlsbb cr1,vs0
 .*:    (f1 02 f7 6e|6e f7 02 f1)       xvtlsbb cr2,vs62
 .*:    (f1 82 0f 6c|6c 0f 82 f1)       xvtlsbb cr3,vs1

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e6a849a2e5893f201ff60dfed260e3c91d639491..40caaf97b7f20ba63d7547dce4db561f5cdeddf2 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2020-08-19  Alan Modra  <amodra@gmail.com>
+
+       * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
+       vcmpuq and xvtlsbb.
+
 2020-08-18  Peter Bergner  <bergner@linux.ibm.com>
 
        * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index cdaffdf149c7d2e43c5417557a4ca3ac33853e73..f23d142c0e14767d783839280606c710b3a92aa2 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -4441,7 +4441,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"nmachhws",   XO (4, 110,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
 {"nmachhws.",  XO (4, 110,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
 {"vadduqm",    VX (4, 256),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
-{"vcmpuq",     VX (4, 257),    VXBF_MASK,   POWER10,   0,              {OBF, VA, VB}},
+{"vcmpuq",     VX (4, 257),    VXBF_MASK,   POWER10,   0,              {BF, VA, VB}},
 {"vmaxsb",     VX (4, 258),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
 {"vslb",       VX (4, 260),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
 {"vslq",       VX (4, 261),    VX_MASK,     POWER10,   0,              {VD, VA, VB}},
@@ -4459,7 +4459,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"macchwu",    XO (4, 140,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
 {"macchwu.",   XO (4, 140,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
 {"vaddcuq",    VX (4, 320),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
-{"vcmpsq",     VX (4, 321),    VXBF_MASK,   POWER10,   0,              {OBF, VA, VB}},
+{"vcmpsq",     VX (4, 321),    VXBF_MASK,   POWER10,   0,              {BF, VA, VB}},
 {"vmaxsh",     VX (4, 322),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
 {"vslh",       VX (4, 324),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
 {"vrlqnm",     VX (4, 325),    VX_MASK,     POWER10,   0,              {VD, VA, VB}},
@@ -8458,7 +8458,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"xxgenpcvdm", X(60,949),      XX1_MASK,    POWER10,   PPCVLE,         {XT6, VB, UIMM}},
 {"xvxexpdp",   XX2VA(60,475,0),XX2_MASK,    PPCVSX3,   PPCVLE,         {XT6, XB6}},
 {"xvxsigdp",   XX2VA(60,475,1),XX2_MASK,    PPCVSX3,   PPCVLE,         {XT6, XB6}},
-{"xvtlsbb",    XX2VA(60,475,2),XX2BF_MASK,  POWER10,   PPCVLE,         {OBF, XB6}},
+{"xvtlsbb",    XX2VA(60,475,2),XX2BF_MASK,  POWER10,   PPCVLE,         {BF, XB6}},
 {"xxbrh",      XX2VA(60,475,7),XX2_MASK,    PPCVSX3,   PPCVLE,         {XT6, XB6}},
 {"xvxexpsp",   XX2VA(60,475,8),XX2_MASK,    PPCVSX3,   PPCVLE,         {XT6, XB6}},
 {"xvxsigsp",   XX2VA(60,475,9),XX2_MASK,    PPCVSX3,   PPCVLE,         {XT6, XB6}},