[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 1 "const0_operand" ""))
(clobber (reg:CC FLAGS_REG))]
- "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
+ "reload_completed"
"xor{l}\t%0, %0"
[(set_attr "type" "alu1")
(set_attr "mode" "SI")
(match_operand:SI 1 "immediate_operand" "i"))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
- && operands[1] == constm1_rtx
- && (TARGET_MOVE_M1_VIA_OR || optimize_size)"
+ && operands[1] == constm1_rtx"
{
operands[1] = constm1_rtx;
return "or{l}\t{%1, %0|%0, %1}";
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
(match_operand:HI 1 "const0_operand" ""))
(clobber (reg:CC FLAGS_REG))]
- "reload_completed
- && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
+ "reload_completed"
"xor{w}\t%0, %0"
[(set_attr "type" "alu1")
(set_attr "mode" "HI")
[(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
(match_operand:QI 1 "const0_operand" ""))
(clobber (reg:CC FLAGS_REG))]
- "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
+ "reload_completed"
"xor{b}\t%0, %0"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:DI 1 "const0_operand" ""))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
+ "TARGET_64BIT
&& reload_completed"
"xor{l}\t%k0, %k0";
[(set_attr "type" "alu1")
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:DI 1 "const_int_operand" "i"))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && (TARGET_MOVE_M1_VIA_OR || optimize_size)
+ "TARGET_64BIT
&& reload_completed
&& operands[1] == constm1_rtx"
{
(use (match_dup 2))
(clobber (match_scratch:<ssevecmode> 3 ""))
(clobber (match_scratch:<ssevecmode> 4 ""))])]
- "!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH && !optimize_size"
+ "!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH"
{
enum machine_mode mode = <MODE>mode;
enum machine_mode vecmode = <ssevecmode>mode;
REAL_VALUE_TYPE TWO31r;
rtx two31;
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
real_ldexp (&TWO31r, &dconst1, 31);
two31 = const_double_from_real_value (TWO31r, mode);
two31 = ix86_build_const_vector (mode, true, two31);
(match_operand:SF 2 "nonimmediate_operand" "")))]
"TARGET_80387 || TARGET_SSE_MATH"
{
- if (TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
+ if (TARGET_SSE_MATH && TARGET_RECIP && optimize_insn_for_speed_p ()
&& flag_finite_math_only && !flag_trapping_math
&& flag_unsafe_math_optimizations)
{
UNSPEC_FPATAN))
(clobber (match_scratch:XF 6 ""))])]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
int i;
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
for (i = 2; i < 6; i++)
operands[i] = gen_reg_rtx (XFmode);
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
rtx op1 = gen_reg_rtx (XFmode);
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_asinxf2 (op0, op1));
emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
UNSPEC_FPATAN))
(clobber (match_scratch:XF 6 ""))])]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
int i;
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
for (i = 2; i < 6; i++)
operands[i] = gen_reg_rtx (XFmode);
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
rtx op1 = gen_reg_rtx (XFmode);
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_acosxf2 (op0, op1));
emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
ix86_emit_i387_log1p (operands[0], operands[1]);
DONE;
})
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op0 = gen_reg_rtx (XFmode);
+ rtx op0;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op0 = gen_reg_rtx (XFmode);
operands[1] = gen_rtx_FLOAT_EXTEND (XFmode, operands[1]);
[(use (match_operand:SI 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
+ rtx op0, op1;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op0 = gen_reg_rtx (XFmode);
+ op1 = gen_reg_rtx (XFmode);
emit_insn (gen_fxtractxf3_i387 (op0, op1, operands[1]));
emit_insn (gen_fix_truncxfsi2 (operands[0], op1));
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
+ rtx op0, op1;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op0 = gen_reg_rtx (XFmode);
+ op1 = gen_reg_rtx (XFmode);
emit_insn (gen_fxtract_extend<mode>xf3_i387 (op0, op1, operands[1]));
emit_insn (gen_fix_truncxfsi2 (operands[0], op1));
(unspec:XF [(match_dup 8) (match_dup 4)]
UNSPEC_FSCALE_EXP))])]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
int i;
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
for (i = 3; i < 10; i++)
operands[i] = gen_reg_rtx (XFmode);
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op2 = gen_reg_rtx (XFmode);
+ rtx op2;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op2 = gen_reg_rtx (XFmode);
emit_move_insn (op2, standard_80387_constant_rtx (5)); /* fldl2e */
emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2));
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
+ rtx op0, op1;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op0 = gen_reg_rtx (XFmode);
+ op1 = gen_reg_rtx (XFmode);
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_expxf2 (op0, op1));
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op2 = gen_reg_rtx (XFmode);
+ rtx op2;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op2 = gen_reg_rtx (XFmode);
emit_move_insn (op2, standard_80387_constant_rtx (6)); /* fldl2t */
emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2));
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
+ rtx op0, op1;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op0 = gen_reg_rtx (XFmode);
+ op1 = gen_reg_rtx (XFmode);
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_exp10xf2 (op0, op1));
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op2 = gen_reg_rtx (XFmode);
+ rtx op2;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op2 = gen_reg_rtx (XFmode);
emit_move_insn (op2, CONST1_RTX (XFmode)); /* fld1 */
emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2));
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
+ rtx op0, op1;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op0 = gen_reg_rtx (XFmode);
+ op1 = gen_reg_rtx (XFmode);
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_exp2xf2 (op0, op1));
(set (match_operand:XF 0 "register_operand" "")
(plus:XF (match_dup 12) (match_dup 7)))]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
int i;
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
for (i = 2; i < 13; i++)
operands[i] = gen_reg_rtx (XFmode);
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
+ rtx op0, op1;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op0 = gen_reg_rtx (XFmode);
+ op1 = gen_reg_rtx (XFmode);
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_expm1xf2 (op0, op1));
(unspec:XF [(match_dup 1) (match_dup 3)]
UNSPEC_FSCALE_EXP))])]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
operands[3] = gen_reg_rtx (XFmode);
operands[4] = gen_reg_rtx (XFmode);
})
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
+ rtx op0, op1;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op0 = gen_reg_rtx (XFmode);
+ op1 = gen_reg_rtx (XFmode);
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_ldexpxf3 (op0, op1, operands[2]));
(unspec:XF [(match_dup 1) (match_dup 2)]
UNSPEC_FSCALE_EXP))])]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
operands[3] = gen_reg_rtx (XFmode);
})
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
- rtx op2 = gen_reg_rtx (XFmode);
+ rtx op0, op1, op2;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op0 = gen_reg_rtx (XFmode);
+ op1 = gen_reg_rtx (XFmode);
+ op2 = gen_reg_rtx (XFmode);
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_extend<mode>xf2 (op2, operands[2]));
|| TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations)
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
- && !flag_trapping_math
- && (TARGET_ROUND || !optimize_size))"
+ && !flag_trapping_math)"
{
if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
- && !flag_trapping_math
- && (TARGET_ROUND || !optimize_size))
+ && !flag_trapping_math)
{
+ if (!TARGET_ROUND && optimize_insn_for_size_p ())
+ FAIL;
if (TARGET_ROUND)
emit_insn (gen_sse4_1_round<mode>2
(operands[0], operands[1], GEN_INT (0x04)));
[(match_operand:MODEF 0 "register_operand" "")
(match_operand:MODEF 1 "nonimmediate_operand" "")]
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
- && !flag_trapping_math && !flag_rounding_math
- && !optimize_size"
+ && !flag_trapping_math && !flag_rounding_math"
{
+ if (optimize_insn_for_size_p ())
+ FAIL;
if (TARGET_64BIT || (<MODE>mode != DFmode))
ix86_expand_round (operand0, operand1);
else
(match_operand:MODEF 1 "register_operand" "")]
"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& ((<SSEMODEI24:MODE>mode != DImode) || TARGET_64BIT)
- && !flag_trapping_math && !flag_rounding_math
- && !optimize_size"
+ && !flag_trapping_math && !flag_rounding_math"
{
+ if (optimize_insn_for_size_p ())
+ FAIL;
ix86_expand_lround (operand0, operand1);
DONE;
})
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
+ if (optimize_insn_for_size_p ())
+ FAIL;
emit_insn (gen_frndintxf2_floor (operands[0], operands[1]));
DONE;
})
"(TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size)
+ && flag_unsafe_math_optimizations)
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
- && !flag_trapping_math
- && (TARGET_ROUND || !optimize_size))"
+ && !flag_trapping_math)"
{
if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
&& !flag_trapping_math
- && (TARGET_ROUND || !optimize_size))
+ && (TARGET_ROUND || optimize_insn_for_speed_p ()))
{
+ if (!TARGET_ROUND && optimize_insn_for_size_p ())
+ FAIL;
if (TARGET_ROUND)
emit_insn (gen_sse4_1_round<mode>2
(operands[0], operands[1], GEN_INT (0x01)));
}
else
{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
+ rtx op0, op1;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+ op0 = gen_reg_rtx (XFmode);
+ op1 = gen_reg_rtx (XFmode);
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_frndintxf2_floor (op0, op1));
[(match_operand:DI 0 "nonimmediate_operand" "")
(match_operand:MODEF 1 "register_operand" "")]
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH && TARGET_64BIT
- && !flag_trapping_math
- && !optimize_size"
+ && !flag_trapping_math"
{
+ if (optimize_insn_for_size_p ())
+ FAIL;
ix86_expand_lfloorceil (operand0, operand1, true);
DONE;
})
[(match_operand:SI 0 "nonimmediate_operand" "")
(match_operand:MODEF 1 "register_operand" "")]
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
- && !flag_trapping_math
- && (!optimize_size || !TARGET_64BIT)"
+ && !flag_trapping_math"
{
+ if (optimize_insn_for_size_p () && TARGET_64BIT)
+ FAIL;
ix86_expand_lfloorceil (operand0, operand1, true);
DONE;
})
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
+ if (optimize_insn_for_size_p ())
+ FAIL;
emit_insn (gen_frndintxf2_ceil (operands[0], operands[1]));
DONE;
})
"(TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size)
+ && flag_unsafe_math_optimizations)
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
- && !flag_trapping_math
- && (TARGET_ROUND || !optimize_size))"
+ && !flag_trapping_math)"
{
if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
&& !flag_trapping_math
- && (TARGET_ROUND || !optimize_size))
+ && (TARGET_ROUND || optimize_insn_for_speed_p ()))
{
if (TARGET_ROUND)
emit_insn (gen_sse4_1_round<mode>2
(operands[0], operands[1], GEN_INT (0x02)));
+ else if (optimize_insn_for_size_p ())
+ FAIL;
else if (TARGET_64BIT || (<MODE>mode != DFmode))
ix86_expand_floorceil (operand0, operand1, false);
else
}
else
{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
+ rtx op0, op1;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+ op0 = gen_reg_rtx (XFmode);
+ op1 = gen_reg_rtx (XFmode);
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_frndintxf2_ceil (op0, op1));
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
+ if (optimize_insn_for_size_p ())
+ FAIL;
emit_insn (gen_frndintxf2_trunc (operands[0], operands[1]));
DONE;
})
"(TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size)
+ && flag_unsafe_math_optimizations)
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
- && !flag_trapping_math
- && (TARGET_ROUND || !optimize_size))"
+ && !flag_trapping_math)"
{
if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
&& !flag_trapping_math
- && (TARGET_ROUND || !optimize_size))
+ && (TARGET_ROUND || optimize_insn_for_speed_p ()))
{
if (TARGET_ROUND)
emit_insn (gen_sse4_1_round<mode>2
(operands[0], operands[1], GEN_INT (0x03)));
+ else if (optimize_insn_for_size_p ())
+ FAIL;
else if (TARGET_64BIT || (<MODE>mode != DFmode))
ix86_expand_trunc (operand0, operand1);
else
}
else
{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
+ rtx op0, op1;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+ op0 = gen_reg_rtx (XFmode);
+ op1 = gen_reg_rtx (XFmode);
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_frndintxf2_trunc (op0, op1));
operands[6] = gen_rtx_PLUS (Pmode, operands[2], adjust);
/* Can't use this if the user has appropriated esi or edi. */
- if ((TARGET_SINGLE_STRINGOP || optimize_size)
+ if ((TARGET_SINGLE_STRINGOP || optimize_insn_for_size_p ())
&& !(fixed_regs[SI_REG] || fixed_regs[DI_REG]))
{
emit_insn (gen_strmov_singleop (operands[0], operands[1],
(match_operand 4 "" ""))
(set (match_operand 2 "register_operand" "")
(match_operand 5 "" ""))])]
- "TARGET_SINGLE_STRINGOP || optimize_size"
+ ""
"ix86_current_function_needs_cld = 1;")
(define_insn "*strmovdi_rex_1"
(set (match_operand:DI 1 "register_operand" "=S")
(plus:DI (match_dup 3)
(const_int 8)))]
- "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "TARGET_64BIT && TARGET_SINGLE_STRINGOP"
"movsq"
[(set_attr "type" "str")
(set_attr "mode" "DI")
(set (match_operand:SI 1 "register_operand" "=S")
(plus:SI (match_dup 3)
(const_int 4)))]
- "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "!TARGET_64BIT && TARGET_SINGLE_STRINGOP"
"movs{l|d}"
[(set_attr "type" "str")
(set_attr "mode" "SI")
(set (match_operand:DI 1 "register_operand" "=S")
(plus:DI (match_dup 3)
(const_int 4)))]
- "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "TARGET_64BIT && TARGET_SINGLE_STRINGOP"
"movs{l|d}"
[(set_attr "type" "str")
(set_attr "mode" "SI")
(set (match_operand:SI 1 "register_operand" "=S")
(plus:SI (match_dup 3)
(const_int 2)))]
- "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "!TARGET_64BIT && TARGET_SINGLE_STRINGOP"
"movsw"
[(set_attr "type" "str")
(set_attr "memory" "both")
(set (match_operand:DI 1 "register_operand" "=S")
(plus:DI (match_dup 3)
(const_int 2)))]
- "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "TARGET_64BIT && TARGET_SINGLE_STRINGOP"
"movsw"
[(set_attr "type" "str")
(set_attr "memory" "both")
(set (match_operand:SI 1 "register_operand" "=S")
(plus:SI (match_dup 3)
(const_int 1)))]
- "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "!TARGET_64BIT && TARGET_SINGLE_STRINGOP"
"movsb"
[(set_attr "type" "str")
(set_attr "memory" "both")
(set (match_operand:DI 1 "register_operand" "=S")
(plus:DI (match_dup 3)
(const_int 1)))]
- "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "TARGET_64BIT && TARGET_SINGLE_STRINGOP"
"movsb"
[(set_attr "type" "str")
(set_attr "memory" "both")
operands[3] = gen_rtx_PLUS (Pmode, operands[0],
GEN_INT (GET_MODE_SIZE (GET_MODE
(operands[2]))));
- if (TARGET_SINGLE_STRINGOP || optimize_size)
+ if (TARGET_SINGLE_STRINGOP || optimize_insn_for_size_p ())
{
emit_insn (gen_strset_singleop (operands[0], operands[1], operands[2],
operands[3]));
(match_operand 2 "register_operand" ""))
(set (match_operand 0 "register_operand" "")
(match_operand 3 "" ""))])]
- "TARGET_SINGLE_STRINGOP || optimize_size"
+ "TARGET_SINGLE_STRINGOP"
"ix86_current_function_needs_cld = 1;")
(define_insn "*strsetdi_rex_1"
(set (match_operand:DI 0 "register_operand" "=D")
(plus:DI (match_dup 1)
(const_int 8)))]
- "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "TARGET_64BIT && TARGET_SINGLE_STRINGOP"
"stosq"
[(set_attr "type" "str")
(set_attr "memory" "store")
(set (match_operand:SI 0 "register_operand" "=D")
(plus:SI (match_dup 1)
(const_int 4)))]
- "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "!TARGET_64BIT && TARGET_SINGLE_STRINGOP"
"stos{l|d}"
[(set_attr "type" "str")
(set_attr "memory" "store")
(set (match_operand:DI 0 "register_operand" "=D")
(plus:DI (match_dup 1)
(const_int 4)))]
- "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "TARGET_64BIT && TARGET_SINGLE_STRINGOP"
"stos{l|d}"
[(set_attr "type" "str")
(set_attr "memory" "store")
(set (match_operand:SI 0 "register_operand" "=D")
(plus:SI (match_dup 1)
(const_int 2)))]
- "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "!TARGET_64BIT && TARGET_SINGLE_STRINGOP"
"stosw"
[(set_attr "type" "str")
(set_attr "memory" "store")
(set (match_operand:DI 0 "register_operand" "=D")
(plus:DI (match_dup 1)
(const_int 2)))]
- "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "TARGET_64BIT && TARGET_SINGLE_STRINGOP"
"stosw"
[(set_attr "type" "str")
(set_attr "memory" "store")
(set (match_operand:SI 0 "register_operand" "=D")
(plus:SI (match_dup 1)
(const_int 1)))]
- "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "!TARGET_64BIT && TARGET_SINGLE_STRINGOP"
"stosb"
[(set_attr "type" "str")
(set_attr "memory" "store")
(set (match_operand:DI 0 "register_operand" "=D")
(plus:DI (match_dup 1)
(const_int 1)))]
- "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "TARGET_64BIT && TARGET_SINGLE_STRINGOP"
"stosb"
[(set_attr "type" "str")
(set_attr "memory" "store")
(match_operand:BLK 2 "general_operand" "")))
(use (match_operand 3 "general_operand" ""))
(use (match_operand 4 "immediate_operand" ""))]
- "! optimize_size || TARGET_INLINE_ALL_STRINGOPS"
+ ""
{
rtx addr1, addr2, out, outlow, count, countreg, align;
+ if (optimize_insn_for_size_p () && !TARGET_INLINE_ALL_STRINGOPS)
+ FAIL;
+
/* Can't use this if the user has appropriated esi or edi. */
if (fixed_regs[SI_REG] || fixed_regs[DI_REG])
FAIL;