RISC-V: Eliminate redundant zero extension of minu/maxu operands

RV64 the following code:

  unsigned Min(unsigned a, unsigned b) {
      return a < b ? a : b;
  }

Compiles to:
  Min:
       zext.w  a1,a1
       zext.w  a0,a0
       minu    a0,a1,a0
       sext.w  a0,a0
       ret

This patch removes unnecessary zero extensions of minu/maxu operands.

gcc/ChangeLog:

	* config/riscv/bitmanip.md: Added expanders for minu/maxu instructions

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zbb-min-max-02.c: Updated scanning check.
	* gcc.target/riscv/zbb-min-max-03.c: New tests.

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index c21247aa3fa9e8e201451c450b7285a99044a03b..6617876bb0b3c81389c473f7cc3cec3525568d16 100644 (file)
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -401,7 +401,30 @@
   DONE;
 })
 
-(define_insn "<bitmanip_optab><mode>3"
+(define_expand "<bitmanip_optab>di3"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (bitmanip_minmax:DI (match_operand:DI 1 "register_operand" "r")
+                            (match_operand:DI 2 "register_operand" "r")))]
+  "TARGET_64BIT && TARGET_ZBB")
+
+(define_expand "<bitmanip_optab>si3"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (bitmanip_minmax:SI (match_operand:SI 1 "register_operand" "r")
+                            (match_operand:SI 2 "register_operand" "r")))]
+  "TARGET_ZBB"
+{
+  if (TARGET_64BIT)
+    {
+      rtx t = gen_reg_rtx (DImode);
+      operands[1] = force_reg (DImode, gen_rtx_SIGN_EXTEND (DImode, operands[1]));
+      operands[2] = force_reg (DImode, gen_rtx_SIGN_EXTEND (DImode, operands[2]));
+      emit_insn (gen_<bitmanip_optab>di3 (t, operands[1], operands[2]));
+      emit_move_insn (operands[0], gen_lowpart (SImode, t));
+      DONE;
+    }
+})
+
+(define_insn "*<bitmanip_optab><mode>3"
   [(set (match_operand:X 0 "register_operand" "=r")
         (bitmanip_minmax:X (match_operand:X 1 "register_operand" "r")
                           (match_operand:X 2 "reg_or_0_operand" "rJ")))]

diff --git a/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c b/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c
index b462859f10f2c47ae4bf79800af466981e9ee534..edfbf807d450f0779e776e35ea557f552be5aa5a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c
+++ b/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gc_zba_zbb -mabi=lp64" } */
-/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
 
 int f(unsigned int* a)
 {
@@ -9,6 +9,6 @@ int f(unsigned int* a)
 }
 
 /* { dg-final { scan-assembler-times "minu" 1 } } */
-/* { dg-final { scan-assembler-times "sext.w" 1 } } */
+/* { dg-final { scan-assembler-not "sext.w" } } */
 /* { dg-final { scan-assembler-not "zext.w" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/zbb-min-max-03.c b/gcc/testsuite/gcc.target/riscv/zbb-min-max-03.c
index c7de1004048920a4ebedc10212f3fa20c189ce6b..38c932b9580065722c411a1f8e7cabedc3f9659d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/zbb-min-max-03.c
+++ b/gcc/testsuite/gcc.target/riscv/zbb-min-max-03.c
@@ -6,5 +6,18 @@ int f(int x) {
  return x >= 0 ? x : 0;
 }
 
+unsigned f2(unsigned x, unsigned y) {
+  return x > y ? x : y;
+}
+
+unsigned f3(unsigned x, unsigned y) {
+  return x < y ? x : y;
+}
+
 /* { dg-final { scan-assembler-times "max\t" 1 } } */
 /* { dg-final { scan-assembler-not "li\t" } } */
+/* { dg-final { scan-assembler-times "maxu\t" 1 } } */
+/* { dg-final { scan-assembler-times "minu\t" 1 } } */
+/* { dg-final { scan-assembler-not "zext.w" } } */
+/* { dg-final { scan-assembler-not "sext.w" } } */
+