pci: pcie-rcar-gen4: Add missing 1ms delay after PWR reset assertion

R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025 page 585
Figure 9.3.2 Software Reset flow (B) indicates that for peripherals in HSC
domain, after reset has been asserted by writing a matching reset bit into
register SRCR, it is mandatory to wait 1ms.

Because it is the controller driver which can determine whether or not the
controller is in HSC domain based on its compatible string, add the missing
delay into the controller driver.

This 1ms delay is documented on R-Car V4H and V4M, it is currently unclear
whether S4 is affected as well. This patch does apply the extra delay on
R-Car S4 as well.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

diff --git a/drivers/pci/pci-rcar-gen4.c b/drivers/pci/pci-rcar-gen4.c
index 6e093829861782778a17d52e892a67a8371e0c6d..1f41ce28b0b00c619f8bb48063641b18b0d3d3b5 100644 (file)
--- a/drivers/pci/pci-rcar-gen4.c
+++ b/drivers/pci/pci-rcar-gen4.c
@@ -306,6 +306,8 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
        if (ret)
                goto err_unprepare;
 
+       mdelay(1);
+
        setbits_le32(rcar->app_base + PCIEMSR0,
                     DEVICE_TYPE_RC |
                     ((rcar->num_lanes < 4) ? BIFUR_MOD_SET_ON : 0));